Patents Issued in July 15, 2014
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Patent number: 8778790Abstract: A rewiring is formed by forming a Cu seed layer of copper over an opening and insulating films, forming a photoresist film over the Cu seed layer, a step of forming copper film by plating-growth over the Cu seed layer, and forming a Ni film. After forming an Au film in an opening (pad region) over the rewiring, the photoresist film is removed and passivation processing is performed on the Ni film. Then, the Cu seed layer other than the formation region of the rewiring is etched. According to these steps, a passivation film is formed on the surface of the Ni film and the reduction in film thickness of the Ni film by the etching can be reduced. Furthermore, it is possible to reduce trouble due to distortion of a substrate resulting from an increase in thickness of the Ni film in view of reduction in film thickness.Type: GrantFiled: January 27, 2012Date of Patent: July 15, 2014Assignee: Renesas Electronics CorporationInventors: Tota Maitani, Yutaro Ebata
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Patent number: 8778791Abstract: The present invention relates to a semiconductor structure and a method for making the same. The method includes the following steps: (a) providing a first wafer and a second wafer; (b) disposing the first wafer on the second wafer; (c) removing part of the first wafer, so as to form a groove; (d) forming a through via in the groove; and (e) forming at least one electrical connecting element on the first wafer. Therefore, the wafers are penetrated and electrically connected by forming only one conductive via, which leads to a simplified process and a low manufacturing cost.Type: GrantFiled: February 5, 2013Date of Patent: July 15, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Meng-Jen Wang
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Patent number: 8778792Abstract: Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.Type: GrantFiled: February 4, 2013Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Ekta Misra, Christopher D. Muzzy, Wolfgang Sauter, George J. Scott
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Patent number: 8778793Abstract: A barrier insulating film is constituted from a first SiCN film formed with a tetramethylsilane gas flow rate lower than usual, a second SiCN film formed over the first SiCN film and formed with a usual tetramethylsilane gas flow rate, and a SiCO film formed over the second SiCN film.Type: GrantFiled: February 9, 2012Date of Patent: July 15, 2014Assignee: Renesas Electronics CorporationInventors: Takahisa Furuhashi, Naohito Suzumura
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Patent number: 8778794Abstract: Disclosed are a method to fabricate interconnection wires of a semiconductor device in a way to utilize benefits of copper interconnection and low k dielectric insulation while avoiding the problem of low k damage due to etching processes, and so fabricated interconnection wires. The method saves fabrication time and cost by reduced number of steps and also resolves metal gap fill issue. The method may comprise providing layers of a substrate, an etch stop layer and a sacrificial layer, forming first spacers, forming first copper interconnecting wires, removing the first spacers; forming polymer-like second spacers by depositing plasma gases in an etching chamber, forming second metal interconnecting wires, removing the second spacers to define channels interwoven with alternating first and second metal interconnecting wires, forming an anti-diffusion barrier around each of the first and second metal interconnecting wires, and filling the channels with a dielectric material for insulation.Type: GrantFiled: December 21, 2012Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sunil Kumar Singh, Hsin-Chieh Yao, Chung-Ju Lee, Hsiang-Huan Lee
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Patent number: 8778795Abstract: In sophisticated metallization systems of semiconductor devices, a sensitive core metal, such as copper, may be efficiently confined by a conductive barrier material comprising a copper/silicon compound, such as a copper silicide, which may provide superior electromigration behavior and higher electrical conductivity compared to conventionally used tantalum/tantalum nitride barrier systems.Type: GrantFiled: July 27, 2011Date of Patent: July 15, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Ronny Pfuetzner, Jens Heinrich
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Patent number: 8778796Abstract: Substantially simultaneous plasma etching of polysilicon and oxide layers in multilayer lines in semiconductors allows for enhanced critical dimensions and aspect ratios of the multilayer lines. Increasing multilayer line aspect ratios may be possible, allowing for increased efficiency, greater storage capacity, and smaller critical dimensions in semiconductor technologies.Type: GrantFiled: October 10, 2012Date of Patent: July 15, 2014Assignee: Macronix International Co., Ltd.Inventor: Lo Yueh Lin
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Patent number: 8778797Abstract: A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.Type: GrantFiled: September 23, 2011Date of Patent: July 15, 2014Assignee: Novellus Systems, Inc.Inventors: Juwen Gao, Rajkumar Jakkaraju, Michal Danek, Wei Lei
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Patent number: 8778798Abstract: An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.Type: GrantFiled: March 12, 2014Date of Patent: July 15, 2014Inventors: Shu-Ming Chang, Bai-Yao Lou, Ying-Nan Wen, Chien-Hung Liu
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Patent number: 8778799Abstract: A method for making conductive traces and interconnects on a surface of a substrate includes, for an embodiment, forming a dielectric or polymer layer on the surface of the substrate, forming a seed layer of an electrically conductive material on the dielectric or polymer layer, patterning a photoresist on the seed layer, forming the conductive traces on the patterned photoresist and seed layer, removing the photoresist from the substrate, and irradiating the surface of the substrate with a fluence of laser light effective to ablate the seed layer from areas of the substrate surface exclusive of the conductive traces.Type: GrantFiled: January 11, 2012Date of Patent: July 15, 2014Assignee: Tamarack Scientific Co. Inc.Inventor: Matthew E. Souter
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Patent number: 8778800Abstract: This invention provides a micro-supercapacitor with high energy density and high power density. In some variations, carbon nanostructures, such as carbon nanotubes, coated with a metal oxide, such as ruthenium oxide, are grown in a supercapacitor cavity that contains no separator. A lid is bonded to the cavity using a bonding process to form a hermetic seal. These micro-supercapacitors may be fabricated from silicon-on-insulator wafers according to the disclosed methods. An exemplary micro-supercapacitor is cubic with a length of about 50-100 ?m. The absence of a separator translates to higher energy storage volume and less wasted space within the supercapacitor cell. The energy density of the micro-supercapacitor may exceed 150 J/cm3 and the peak output power density may be in the range of about 2-20 W/cm3, in various embodiments.Type: GrantFiled: May 6, 2013Date of Patent: July 15, 2014Assignee: HRL Laboratories, LLCInventors: David T. Chang, Pamela R. Patterson, Ping Liu
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Patent number: 8778801Abstract: A seed layer comprises a bottom seed layer portion formed on the bottom of a via opening, a sidewall seed layer portion formed on an upper portion of the sidewall of the via opening and a corner seed layer portion formed between the bottom seed layer portion and the sidewall seed layer portion. The sidewall seed layer portion is of a first thickness. The corner seed layer portion is of a second thickness and the second thickness is greater than the first thickness.Type: GrantFiled: September 21, 2012Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Bin Chiang, Hung-Chih Wang, Kuei-Pin Lee, Chi-Yu Chou, Yao Hsiang Liang
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Patent number: 8778802Abstract: A polishing method includes causing a polishing pad arranged on a turn table to rotate together with the turn table, and polishing a surface of a substrate by using the rotating polishing pad while supplying a chemical fluid to a surface of the polishing pad on a fore side of the substrate from an oblique direction with respect to the surface of the polishing pad.Type: GrantFiled: May 23, 2007Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Dai Fukushima, Gaku Minamihaba, Hiroyuki Yano
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Patent number: 8778803Abstract: Disclosed is a CMP slurry for silicon film polishing, comprising abrasive grains, an oxidizing agent, a cationic surfactant, and water. This CMP slurry is suitable for the CMP step of a silicon film of semiconductor devices, since it enables to obtain excellent planarity and excellent performance of controlling the remaining film thickness, while improving the yield and reliability of the semiconductor devices. This CMP slurry also enables to reduce the production cost.Type: GrantFiled: June 6, 2008Date of Patent: July 15, 2014Assignee: Hitachi Chemical Company, Ltd.Inventor: Takenori Narita
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Patent number: 8778804Abstract: A method and apparatus for selective etching a substrate using a focused beam. For example, multiple gases may be used that are involved in competing beam-induced and spontaneous reactions, with the result depending on the materials on the substrate. The gases may include, for example, an etchant gas and an auxiliary gas that inhibits etching.Type: GrantFiled: January 30, 2009Date of Patent: July 15, 2014Assignee: FEI CompanyInventors: Steven Randolph, Clive D. Chandler
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Patent number: 8778805Abstract: In a method for manufacturing a semiconductor device, an opening formed in a semiconductor substrate by using a mask and covering an inner side face of the opening with a sidewall protective film. The mask is removed, while a part of the sidewall protective film remains.Type: GrantFiled: January 30, 2012Date of Patent: July 15, 2014Assignee: PS4 Luxco S.A.R.L.Inventor: Seiya Fujii
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Patent number: 8778806Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.Type: GrantFiled: April 17, 2012Date of Patent: July 15, 2014Assignee: Plasma-Therm LLCInventors: Chris Johnson, David Johnson, David Pays-Volard, Linnell Martinez, Russell Westerman, Gordon M. Grivna
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Patent number: 8778807Abstract: A method of forming an integrated circuit structure includes providing a substrate; forming a first hard mask layer over the substrate; forming a second hard mask layer over the first hard mask layer; patterning the second hard mask layer to form a hard mask; and, after the step of patterning the second hard mask layer, baking the substrate, the first hard mask layer, and the hard mask. After the step of baking, a spacer layer is formed, which includes a first portion on a top of the hard mask, and a second portion and a third portion on opposite sidewalls of the hard mask. The method further includes removing the first portion of the spacer layer; removing the hard mask; and using the second portion and the third portion of the spacer layer as masks to pattern the first hard mask layer.Type: GrantFiled: October 5, 2011Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yu Lai, Cheng-Ta Wu, Neng-Kuo Chen, Cheng-Yuan Tsai
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Patent number: 8778808Abstract: The invention relates to semiconductor devices and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked over a semiconductor substrate. The gate electrode layer, the second conductive layer, the dielectric layer, and the first conductive layer are patterned so that the first conductive layer partially remains to prevent the tunnel insulating layer from being exposed. Sidewalls of the gate electrode layer are etched. A first passivation layer is formed on the entire surface including the sidewalls of the gate electrode layer. At this time, a thickness of the first passivation layer formed on the sidewalls of the gate electrode layer is thicker than that of the first passivation layer formed in other areas.Type: GrantFiled: August 10, 2011Date of Patent: July 15, 2014Assignee: SK hynix Inc.Inventor: Kwang Seok Jeon
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Patent number: 8778809Abstract: A device having three evaporation sources and a unit for moving the respective evaporation sources in one chamber is used, whereby it becomes possible to increase efficiency of use of an evaporation material. Consequently, manufacturing cost can be reduced, and a uniform thickness can be obtained over an entire surface of a substrate even in the case in which a large area substrate is used.Type: GrantFiled: March 14, 2013Date of Patent: July 15, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideaki Kuwabara
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Patent number: 8778810Abstract: A method for manufacturing a semiconductor device having fluorocarbon layers as insulating layers includes the steps of forming a first fluorocarbon (CFx1) layer using plasma excited by microwave power and forming a second fluorocarbon (CFx2) layer using plasma excited by an RF power.Type: GrantFiled: June 25, 2010Date of Patent: July 15, 2014Assignee: Tokyo Electron LimitedInventor: Hiroyuki Takaba
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Patent number: 8778811Abstract: Epitaxial films are grown by alternately exposed to precursor dosing regions, inert gas plasma regions, hydrogen-containing plasma regions, chlorine-containing plasma and metrology regions, or regions where an atomic hydrogen source is located. Alternately, laser irradiation techniques may be substituted for the plasma energy in some of the processing regions. The film growth process can be implemented at substrate temperatures between about 25 C and about 600 C, together with optional exposures to laser irradiation to cause the surface of the film to melt or to experience a near-melt condition.Type: GrantFiled: August 18, 2011Date of Patent: July 15, 2014Assignee: Intermolecular, Inc.Inventors: Philip A. Kraus, Dipankar Pramanik, Boris Borisov
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Patent number: 8778812Abstract: A film deposition method includes an adsorption step of adsorbing a first reaction gas onto a substrate by supplying the first reaction gas from a first gas supplying portion for a predetermined period without supplying a reaction gas from a second gas supplying portion while separating a first process area and a second process area by supplying a separation gas from a separation gas supplying portion and rotating a turntable; and a reaction step of having the first reaction gas adsorbed onto the substrate react with a second reaction gas by supplying the second reaction gas from the second gas supplying portion for a predetermined period without supplying a reaction gas from the first gas supplying portion while separating the first process area and the second process area by supplying the separation gas from the separation gas supplying portion and rotating the turntable.Type: GrantFiled: December 26, 2012Date of Patent: July 15, 2014Assignee: Tokyo Electron LimitedInventors: Haruhiko Furuya, Jun Ogawa, Masahiko Kaminishi, Yoshinobu Ise, Yoshitaka Enoki
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Patent number: 8778813Abstract: An apparatus for plasma processing a substrate is provided. The apparatus comprises a processing chamber, a substrate support disposed in the processing chamber, a shield member disposed in the processing chamber below the substrate support, and a lid assembly coupled to the processing chamber. The lid assembly comprises a conductive gas distributor coupled to a power source, and an electrode separated from the conductive gas distributor and the chamber body by electrical insulators. The electrode is also coupled to a source of electric power. The substrate support is formed with a stiffness that permits very little departure from parallelism. The shield member thermally shields a substrate transfer opening in the lower portion of the chamber body. A pumping plenum is located below the substrate support processing position, and is spaced apart therefrom.Type: GrantFiled: May 6, 2011Date of Patent: July 15, 2014Assignee: Applied Materials, Inc.Inventors: Ramprakash Sankarakrishnan, Ganesh Balasubramanian, Juan Carlos Rocha-Alvarez, Dale R. Du Bois, Mark Fodor, Jianhua Zhou, Amit Bansal, Mohamad A. Ayoub, Shahid Shaikh, Patrick Reilly, Deenesh Padhi, Thomas Nowak
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Patent number: 8778814Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing an underlying structure having a silicon carbide layer covering a copper wiring, and growing silicon oxycarbide on the underlying structure by vapor deposition using, as source gas, tetramethylcyclotetrasiloxane, carbon dioxide gas and oxygen gas, a flow rate of said oxygen gas being at most 3% of a flow rate of the carbon dioxide gas. The surface of the silicon carbide layer of the underlying structure may be treated with a plasma of weak oxidizing gas which contains oxygen and has a molecular weight larger than that of O2 to bring the surface more hydrophilic. Film peel-off and cracks in the interlayer insulating layer decrease.Type: GrantFiled: August 14, 2013Date of Patent: July 15, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Tamotsu Owada, Shun-ichi Furuyama, Hirofumi Watantani, Kengo Inoue, Atsuo Shimizu
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Patent number: 8778815Abstract: A method of forming a polyimide film on a surface of a substrate by dehydration condensation of a first monomer including a bifunctional acid anhydride and a second monomer including a bifunctional amine is disclosed. The method includes loading the substrate into a processing chamber, heating the substrate at a temperature at which a polyimide film is formed, and performing a cycle a predetermined number of times. The cycle comprises supplying a first processing gas containing the first monomer to the substrate, supplying a second processing gas containing the second monomer to the substrate. The method further includes supplying a replacement gas in the processing chamber between supplying the first processing gas and supplying the second processing gas thereby replacing atmosphere in the processing chamber by the replacement gas, and evacuating the first and/or the second processing gas out of the processing chamber.Type: GrantFiled: May 24, 2013Date of Patent: July 15, 2014Assignee: Tokyo Electron LimitedInventors: Tatsuya Yamaguchi, Reiji Niino
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Patent number: 8778816Abstract: Methods for preparing a substrate for a subsequent film formation process are described. Methods for preparing a substrate for a subsequent film formation process, without immersion in an aqueous solution, are also described. A process is described that includes disposing a substrate into a process chamber, the substrate having a thermal oxide surface with substantially no reactive surface terminations. The thermal oxide surface is exposed to a partial pressure of water below the saturated vapor pressure at a temperature of the substrate to convert the dense thermal oxide with substantially no reactive surface terminations to a surface with hydroxyl surface terminations. This can occur in the presence of a Lewis base such as ammonia.Type: GrantFiled: July 27, 2011Date of Patent: July 15, 2014Assignee: Applied Materials, Inc.Inventors: Tatsuya E. Sato, David Thompson, Jeffrey W. Anthis, Vladimir Zubkov, Steven Verhaverbeke, Roman Gouk, Maitreyee Mahajani, Patricia M. Liu, Malcolm J. Bevan
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Patent number: 8778817Abstract: A method of making a cover material for an absorbent article including the steps of providing a fibrous nonwoven substrate, the substrate having a tortuousity value in the range of about 0.8 to about 3.0, applying a particulate skin care material to the substrate, the particulate skin care comprising a particulate material having a particle size in the range of about 1 micron to about 75 microns, and applying a compressive force to the substrate to impregnate the substrate with the particulate skin care material.Type: GrantFiled: October 30, 2006Date of Patent: July 15, 2014Assignee: McNeil-PPC, Inc.Inventors: Krystyna M. Borysewicz, Ricky Ray Burrow, Jenny G. Du, Joseph Michael Luizzi, Maria Cristina Niciporciukas, Kenneth A. Pelley, John Poccia
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Patent number: 8778818Abstract: An anti-vandalism fabric having at least one thread intertwined with itself forming a mesh, the thread in turn being formed by a bundle of between 3 and 14 filaments or a combination of filaments and yarns not plaited with one another, of which at least 3 are metal filaments, the metal filaments of the bundle having a diameter between 0.05 mm and 0.09 mm. The fabric can include more than one mesh. In one variant the mesh or meshes are embedded in a panel of non woven fabric.Type: GrantFiled: March 27, 2013Date of Patent: July 15, 2014Assignee: Fabricacion Asientos Vehiculos Industriales, S.A.Inventor: Juan Singla Casasayas
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Patent number: 8778819Abstract: Disclosed is a dielectric ceramic composition which has high dielectric constant and suppressed low thermal expansion coefficient. Also disclosed are a multilayer dielectric substrate using the dielectric ceramic composition, and an electronic component. Specifically disclosed is a dielectric ceramic composition which contains an ATiO3 (wherein A represents either Ca and/or Sr) phase and an AAl2Si2O8 phase, said dielectric ceramic composition being characterized in that the dielectric constant is not less than 10 at 3 GHz and the average thermal expansion coefficient over the temperature range of 40-600° C. is less than 7 ppm/° C.Type: GrantFiled: March 19, 2010Date of Patent: July 15, 2014Assignee: Hitachi Metals, Ltd.Inventors: Junichi Masukawa, Koji Ichikawa
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Patent number: 8778820Abstract: Glasses having a low softening point and high toughness. The glasses are alkali aluminoborosilicate glasses having softening points of less than 900° C. and, in some embodiments, in a range from about 650° C. up to about 825° C., and an indenter damage threshold of at least 300 g for glasses that are not chemically strengthened. The glasses are free of alkaline earth metals, lead, arsenic, antimony, and, in some embodiments, lithium.Type: GrantFiled: May 27, 2010Date of Patent: July 15, 2014Assignee: Corning IncorporatedInventors: Sinue Gomez, Lisa Ann Lamberson, Robert Michael Morena
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Patent number: 8778821Abstract: The invention discloses an optical glass and an optical element. The optical glass comprises 0.1 wt % -8 wt % of SiO2, 20 wt % -32 wt % of B2O3, 20 wt % -35 wt % of La2O3, 15 wt % -30 wt % of Gd2O3, 1-6 wt % of Ta2O5, 1 wt % -15 wt % of ZnO, and 0.1 wt % -2 wt % of Li2O. The optical glass claimed in the invention has a refractive index of 1.75-1.8, an Abbe number of 45-52, a transformation temperature of less than 610° C., and a wavelength of less than 390 nm at 80% transmittance. Thus the claimed optical glass meets the requirements for a modern imaging device.Type: GrantFiled: October 2, 2012Date of Patent: July 15, 2014Assignee: CDGM Glass Co., Ltd.Inventor: Wei Sun
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Patent number: 8778822Abstract: The present invention provides a ceramic porous body for in-vitro and in-vivo use comprising a composition comprising a calcium aluminate (CA) containing phase and optionally at least one of an accelerator, a retarder, a surfactant, a foaming agent, a reactive alumina, water, a fiber, and a biologically active material, and combinations thereof. Ceramic compositions are provides as well as method of using the ceramic compositions and methods of manufacturing a ceramic porous body. The ceramic porous bodies of this invention may be used as artificial bones, joints, in-vitro support structures, and in-vivo support structures for cells, tissues, organs, and nerve growth and regeneration.Type: GrantFiled: August 9, 2010Date of Patent: July 15, 2014Assignee: Cabertech, Inc.Inventor: Kenneth A. McGowan
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Patent number: 8778823Abstract: The process involves the use of specifically selected coke precursor compounds from the front end of oil distillate fractions that contain C11 to C14 hydrocarbons and their use as additives in the processing of naphtha in a catalytic reformer. The C11 to C14 compounds additives enhance coke make in continuous catalytic regeneration (CCR) reformers to levels higher than those which are usually produced in low coke naphtha reforming operations. With the increase of ethanol blending in gasoline and low reformate octane severity operations, reformers do not produce the necessary amount of coke to permit sustaining steady state white burn operations.Type: GrantFiled: November 20, 2012Date of Patent: July 15, 2014Assignee: Marathon Petroleum Company LPInventors: Soni O. Oyekan, Kenneth D. Rhodes, Nicholas K. Newlon
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Patent number: 8778824Abstract: This invention relates to aggregates of small primary crystallites of zeolite Y that are clustered into larger secondary particles. At least 80% of the secondary particles may comprise at least 5 primary crystallites. The size of the primary crystallites may be at most about 0.5 micron, or at most about 0.3 micron, and the size of the secondary particles may be at least about 0.8 micron, or at least about 1.0 ?m. The silica to alumina ratio of the resulting stabilized aggregated Y zeolite may be 4:1 or more.Type: GrantFiled: March 6, 2012Date of Patent: July 15, 2014Assignee: ExxonMobil Research and Engineering CompanyInventors: Wenyih Frank Lai, Robert E. Kay
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Patent number: 8778825Abstract: Partition walls are provided with small pores and large pores, a porosity of the partition walls is from 50 to 70%, a porosity of the large pores of the partition walls is 30% or larger, a ratio of a total volume of the small pores to a total volume of the large pores is 20% or larger, and in a graph showing a pore diameter distribution of the partition walls, the pore diameter at a maximum peak value of the large pores is from 20 to 200 ?m, and the pore diameter at a maximum peak value of the small pores is from 0.1 to 8 ?m. Furthermore, a value obtained by dividing a porosity value (%) of the large pores by a thickness value (?m) of the partition walls is 0.2 or larger in a honeycomb structure.Type: GrantFiled: September 4, 2012Date of Patent: July 15, 2014Assignee: NGK Insulators, Ltd.Inventors: Shogo Hirose, Yukio Miyairi
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Patent number: 8778826Abstract: Disclosed herein are processes for preparing procatalyst compositions and polymers, i.e., propylene-based polymers, produced therefrom. The present procatalyst compositions improve catalyst selectivity and also increase the bulk density of the formant polymer.Type: GrantFiled: December 31, 2009Date of Patent: July 15, 2014Assignee: W. R. Grace & Co.-Conn.Inventors: Kelly Gonzalez, Clark C. Williams, Linfeng Chen
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Patent number: 8778827Abstract: The present invention relates to a catalyst composition comprising: (a) a binuclear chromium(II) complex; (b) a ligand of the general structure (A) R1R2P—N(R3)—P(R4)—N(R5)—H or (B) R1R2P—N(R3)—P(R4)—N(R5)—PR6R7, wherein R1, R2, R3, R4, R5, R6 and R7 are independently selected from halogen, amino, trimethylsilyl, C1-C10-alkyl, aryl and substituted aryl, wherein the PNPN- or PNPNP-unit is optionally part of a ring system; and (c) an activator or co-catalyst, as well as to a process for oligomerization of ethylene.Type: GrantFiled: November 5, 2008Date of Patent: July 15, 2014Assignees: Saudi Basic Industries Corporation, Linde AGInventors: Vugar Aliyev, Mohammed Al-Hazmi, Fuad Mosa, Peter M. Fritz, Heinz Bölt, Anina Wöhl, Wolfgang Müller, Florian Winkler, Anton Wellenhofer, Uwe Rosenthal, Bernd H. Müller, Marko Hapke, Normen Peulecke
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Patent number: 8778828Abstract: A process for preparing a slurry catalyst for the upgrade of heavy oil feedstock is provided. The process employs a pressure leach solution obtained from a metal recovery process as part of the metal precursor feed. In one embodiment, the process comprises: sulfiding a pressure leach solution having at least a Group VIB metal precursor compound in solution forming a catalyst precursor, and mixing the sulfided catalyst precursor with a hydrocarbon diluent to form the slurry catalyst. In another embodiment, the pressure leach solution is mixed with a hydrocarbon diluent under high shear mixing conditions to form an emulsion, which emulsion can be sulfided in-situ upon contact with a heavy oil feedstock in the heavy oil upgrade process.Type: GrantFiled: December 20, 2011Date of Patent: July 15, 2014Assignee: Chevron U.S.A. Inc.Inventors: Oleg Mironov, Alexander E. Kuperman, Rahul Shankar Bhaduri, Julie Chabot, Shuwu Yang, Ling Jiao, Joseph V. Nguyen, Bruce Edward Reynolds
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Patent number: 8778829Abstract: The active methanol electro-oxidation catalysts include nano-oxides of transition metals (i.e., iron, cobalt and nickel) and platinum-ruthenium alloy nano-particles. The nano-oxides of the transition metals are dispersed during synthesis of a support material, such as mesoporous carbon. The catalyst includes a support material formed from mesoporous carbon, a nano-oxide of a transition metal dispersed in the support material, and platinum-ruthenium alloy nano-particles supported on the nano-oxide of the transition metal, the platinum-ruthenium alloy nano-particles (in a 1:1 molar ratio) forming about 15 wt % of the methanol electro-oxidation catalyst, the transition metals forming about 15 wt % of the methanol electro-oxidation catalyst, and carbon and oxygen forming the balance of about 70 wt % of the methanol electro-oxidation catalyst.Type: GrantFiled: January 3, 2012Date of Patent: July 15, 2014Assignee: King Fahd University of Petroleum and MineralsInventors: Syed Mohammed Javaid Zaidi, Saleem Ur Rahman, Shakeel Ahmed, Mukhtar Bello
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Patent number: 8778830Abstract: Solid-supported gold nanoparticles for use as a catalyst for the synthesis of quinolines from anilines and aldehydes using oxygen as an oxidant are provided. Also provided are a method for the preparation of SiO2-supported gold nanoparticles by in situ deposition of gold nanoparticles to silica gel and a method for synthesizing quinolines from anilines and aldehydes using oxygen as an oxidant.Type: GrantFiled: May 13, 2011Date of Patent: July 15, 2014Assignee: The University of Hong KongInventors: Chi-Ming Che, Man-Ho So
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Patent number: 8778831Abstract: There is described a base metal modified Cerium containing oxide materials and their application as catalysts for the oxidation of CO and HC emissions from a compression ignition/diesel engine. These materials provide effective promotion of CO and HC oxidation function in the presence or absence of PGM and are based upon OIC/OS materials having a stable cubic crystal structure, and most especially to promoted OIC/OS materials wherein the promotion is achieved by the post-synthetic introduction of non-precious metals via a basic (alkaline) exchange process.Type: GrantFiled: March 20, 2009Date of Patent: July 15, 2014Assignee: Umicore AG & Co. KGInventors: Barry W. L. Southward, Curt Ellis
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Patent number: 8778832Abstract: The present invention is directed to a catalyst suitable for catalyzing a Fischer-Tropsch reaction, said catalyst comprising cobalt metal supported on zinc-oxide and having the following particle size distribution by volume: <10% having a particle size below 1 micron, 70-99% having a particle size between 1 and 5 micron, and <20% having a particle size above 5 micron.Type: GrantFiled: November 11, 2008Date of Patent: July 15, 2014Assignee: BASF CorporationInventors: Tjalling Rekker, Cornelis Roeland Baijense
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Patent number: 8778833Abstract: Catalysts and methods for their manufacture and use for the dehydrogenation of alcohols are disclosed. The catalysts and methods utilize a highly dispersible alumina, for example, boehmite or pseudoboehmite, to form catalysts that exhibit high dehydrogenation activities. Specifically, the catalysts include Cu that is highly dispersed by reaction of an alumina formed by peptizing of boehmite or pseudoboehmite and precursors of ZrO2, ZnO and CuO.Type: GrantFiled: November 11, 2010Date of Patent: July 15, 2014Assignee: BASF CorporationInventors: Rostam Jal Madon, Peter Nagel, Deepak S. Thakur
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Patent number: 8778834Abstract: A multi-layer card-shaped data carrier has a marking layer containing a hidden marking, and a thermochromic cover layer arranged over the marking layer at least in the area of the hidden marking. The thermochromic cover layer is opaque below its change temperature, hides the marking, and is translucent or transparent above its change temperature, enabling viewing of the marking. The thermochromic cover layer is pervious to radiation outside the visible spectral range and the marking layer absorbs radiation energy outside the visible spectral range, so that the hidden marking can be incorporated into the marking layer through the thermochromic cover layer by laser radiation of a wavelength outside the visible spectral range.Type: GrantFiled: November 9, 2010Date of Patent: July 15, 2014Assignee: Giesecke & Devrient GmbHInventors: Günter Endres, Tobias Salzer
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Patent number: 8778835Abstract: A composition comprising at least a pyridylethylbenzamide derivative of general formula (I) (a) and an insecticide compound (b) in a (a)/(b) weight ratio of from 1/1000 to 1000/1. A composition further comprising an additional fungicidal compound. A method for preventively or curatively combating the pests and diseases of crops by using this composition.Type: GrantFiled: July 5, 2007Date of Patent: July 15, 2014Assignee: Bayer Cropscience AGInventors: Heike Hungenberg, Gilbert Labourdette, Albert Schirring, Burkhard Schuetz, Anne Suty-Heinze, Wolfgang Thielert, Martin Vaupel
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Patent number: 8778836Abstract: This invention relates to a new herbicidal composition comprising desmedipham and optionally phenmedipham and/or ethofumesate.Type: GrantFiled: April 25, 2013Date of Patent: July 15, 2014Assignee: Bayer Cropscience LPInventor: David A. Long
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Patent number: 8778837Abstract: The invention relates to the novel use of known active substance combinations which consist firstly of 3,4-dichloro-2?-cyano-1,2-thiazole-5-carboxanilide, of the formula which is known, and secondly further known insecticidal active substances, for controlling animal pests, especially arthropods, in particular insects.Type: GrantFiled: November 27, 2008Date of Patent: July 15, 2014Assignee: Bayer CropScience AGInventors: Lutz Assmann, Ulrike Wachendorff-Neumann, Heike Hungenberg, Wolfgang Thielert
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Patent number: 8778838Abstract: The present invention relates to aqueous concentrate formulations for plant protection comprising: 2-chloro-5-[3,6-dihydro-3-methyl-2,6-dioxo-4-(trifluoromethyl)-1-(2H)pyrimidinyl]-4-fluoro-N-[[methyl(1-methylethyl)amino]sulfonyl]benzamide in the form of its anhydrate; N-(phosphonomethyl)glycine in the form of its free acid, in the form of the ammonium salt or a substituted ammonium salt or a mixture thereof; at least two different non-ionic surfactants with at least one of them comprising an ethylene oxide polymer moiety or an ethylene oxide/C3-C4-alkylene oxide block copolymer moiety, and water; wherein the pH-value of the formulation is below 6.Type: GrantFiled: August 26, 2010Date of Patent: July 15, 2014Assignee: BASF SEInventors: Michael Krapp, Wolfgang Gregori, Sven Adam, Klaus Kolb, Juergen Jakob, Bernd Sievernich, Joerg Steuerwald, Steven Bowe, Joseph Zawierucha, Rex Liebl
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Patent number: 8778839Abstract: Improvement of the effect of a herbicidally active ingredient and reduction of its dosage are required so as to reduce the environment load on a site where the herbicide is applied or the periphery thereof, more than ever. A herbicidal composition comprising (1) a herbicidal sulfonylurea compound or its salt and (2) a polyoxyalkylene alkyl ether phosphate or its salt. A method for controlling undesired plants or inhibiting their growth, by applying such a herbicidal composition.Type: GrantFiled: March 13, 2007Date of Patent: July 15, 2014Assignee: Ishihara Sangyo Kaisha, Ltd.Inventors: Hiroshi Yoshii, Ryu Yamada