Abstract: A package includes a device die including a first plurality of metal pillars at a top surface of the device die. The package further includes a die stack including a plurality of dies bonded together, and a second plurality of metal pillars at a top surface of the die stack. A polymer region includes first portions encircling the device die and the die stack, wherein a bottom surface of the polymer region is substantially level with a bottom surface of the device die and a bottom surface of the die stack. A top surface of the polymer region is level with top ends of the first plurality of metal pillars and top ends of the second plurality of metal pillars. Redistribution lines are formed over and electrically coupled to the first and the second plurality of metal pillars.

Abstract: Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter.

Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Abstract: A method for packaging a quad flat non-leaded (QFN) package body. The method includes: etching an upper surface of a metal plate to process a groove to form a bond wire bench, a component bench, and a bump; processing the bump to a preset height, and assembling a component on the component bench; packaging the processed metal plate to form a package body, and exposing the surface of the processed bump on an upper surface of the package body to form a top lead; and etching a lower surface of the package body to process a bottom lead. In the present invention, large passive components can be stacked on the QFN package body with a top lead; the structure is simplified while the reliability of the welding joints is improved; a plurality of components can be stacked through the top lead to overcome the limitations of component stacking.

Abstract: Methods and structures for thermoelectric cooling of 3D semiconductor structures are disclosed. Thermoelectric vias (TEVs) to form a thermoelectric cooling structure. The TEVs are formed with an etch process similar to that used in forming electrically active through-silicon vias (TSVs). However, the etched cavities are filled with materials that exhibit the thermoelectric effect, instead of a conductive metal as with a traditional electrically active TSV. The thermoelectric materials are arranged such that when a voltage is applied to them, the thermoelectric cooling structure carries heat away from the interior of the structure from the junction where the thermoelectric materials are electrically connected.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a precursor. A decomposable polymer layer (DPL) is deposited between the conductive features of the precursor. The DPL is annealed to form an ordered periodic pattern of different types of polymer nanostructures. One type of polymer nanostructure is decomposed by a first selectively to form a trench. The trench is filled by a dielectric layer to form a dielectric block. The remaining types of polymer nanostructures are decomposed by a second selectively etching to form nano-air-gaps.

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.

Abstract: A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs.

Abstract: Methods and apparatuses for forming an under-bump metallization (UBM) pad above a dielectric layer are disclosed. The dielectric layer may be above a metal layer and comprises a first opening and a second opening surrounding the first opening, which divide the dielectric layer into a first area and a second area. An UBM pad extends into and fills the first opening of the dielectric layer, above the first area between the first opening and the second opening, and may further extends down at least partly into the second opening covering a part or the whole of the second opening of the dielectric layer. The UBM pad may further extend over a part of the second area of the dielectric layer if the UBM pad fills the whole of the second opening of the dielectric layer. A solder ball may be mounted on the UBM pad.

Abstract: A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

Abstract: A microelectronic assembly may include a substrate having an opening extending between first and second oppositely facing surfaces of the substrate, the opening elongated in a first direction; and at least one microelectronic element having a front face facing and attached to the first surface of the substrate and a plurality of contacts at the front face overlying the opening, the microelectronic element having first and second opposite peripheral edges extending away from the front face. The first peripheral edge extends beyond, or is aligned in the first direction with, an inner edge of the opening, and the opening extends beyond the second peripheral edge.

Abstract: Possible to form an opening having a sufficient opening diameter in a region sandwiched between a pair of bit lines and thereby provide a semiconductor device in which a high-quality contact using the opening is formed. The semiconductor device includes a first conductive layer, a first interlayer insulating film, a bit line, a first insulating film, a second interlayer insulating film, and a second conductive layer. The first insulating film that covers a side surface of the bit line has a portion perpendicular to a main surface of a semiconductor substrate in a region lower than a position lower than an uppermost portion of the first insulating film by a thickness, in a direction along the main surface of the semiconductor substrate, of the first insulating film that covers the side surface of the bit line at a lowermost portion of the bit line.

Abstract: Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the upper wordline in a transverse direction and the lower wordline may include a wiring area exposed by the recessed portion of the upper wordline. The wiring structures may also include an upper contact plug contacting the upper wordline and a lower contact plug contacting the wiring area. The upper and lower contact plugs may extend in a vertical direction.

Abstract: A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.

Abstract: One or more techniques or systems for mitigating pattern collapse are provided herein. For example, a semiconductor structure for mitigating pattern collapse is formed. In some embodiments, the semiconductor structure includes an extreme low-k (ELK) dielectric region associated with a via or a metal line. For example, a first metal line portion and a second metal line portion are associated with a first lateral location and a second lateral location, respectively. In some embodiments, the first portion is formed based on a first stage of patterning and the second portion is formed based on a second stage of patterning. In this manner, pattern collapse associated with the semiconductor structure is mitigated, for example.

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress, thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract: A dielectric material stack including at least a via level dielectric material layer, at least one patterned etch stop dielectric material portion, a line level dielectric material layer, and optionally a dielectric cap layer is formed over a substrate. At least one patterned hard mask layer including a first pattern can be formed above the dielectric material stack. A second pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure. The first pattern is transferred through the line level dielectric material layer employing the at least one etch stop dielectric material portion as an etch stop structure while the second pattern is transferred through the via level dielectric material layer to form integrated line and via trenches, which are filled with a conductive material to form integrated line and via structures.

Abstract: Randomized coded arrays and methods of forming a randomized coded array. The methods include: forming a dielectric layer on a semiconductor substrate; forming an array of openings extending through the dielectric layer; introducing particles into a random set of less than all of the openings; and forming a conductive material in each opening of the array of openings, thereby creating the randomized coded array, wherein a first resistance of a pathway through the conductive material in openings containing the particles is different from a second resistance of a path through openings not containing the particles. Also, a physically unclonable function embodied in a circuit.

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein, in which a plurality of semiconductor devices is formed on a semiconductor substrate. At least one through-semiconductor via is formed in the semiconductor substrate and an interlayer dielectric layer is formed overlying the at least one through-semiconductor via and the plurality of semiconductor devices. A first pattern is etched in the interlayer dielectric layer over the at least one through-semiconductor via, and a second pattern different from the first pattern is etched in the interlayer dielectric layer over the same through-semiconductor via as the first pattern. At least one interconnect via is embedded within the interlayer dielectric layer, in electrical communication with one of the at least one through-semiconductor vias. A metal-containing material is deposited in the first pattern and the second pattern to form a first metal layer in electrical communication with the at least one interconnect via.

Abstract: A semiconductor package is provided, including a substrate having a top surface, a bottom surface opposing the top surface, a via communicating the top surface with the bottom surface, and a stator set formed by circuits; an axial tube axially installed in the via of the substrate; a plurality of electronic components mounted on the top surface of the substrate and electrically connected to the substrate; an encapsulant formed on the top surface of the substrate for encapsulating the electronic components and the axial tube; and an impeller axially coupled to the axial tube via the bottom surface of the substrate. In the semiconductor package, the stator set is formed in the substrate by a patterning process. Therefore, the thickness of the semiconductor package is reduced significantly.

Abstract: The present application provides an electronic device package. The package includes a packaging substrate having first and second surfaces opposing one another. First and second electrode patterns are formed on the first surface and first and second external terminals connected to the first and second electrode patterns. The second electrode pattern is electrically insulated from the first electrode pattern and surrounds the first electrode pattern An electronic device is mounted on the first surface of the packaging substrate and includes first and second electrodes disposed on a surface thereof facing the packaging substrate. The first and second electrodes are positioned on the first and second electrode patterns, respectively.

Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

Abstract: A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.

Abstract: A semiconductor device includes an analog integrated circuit and a digital integrated circuit provided on a major surface of a substrate. An analog ground terminal is provided for the analog integrated circuit, and digital ground terminals are provided for the digital integrated circuit. An analog ground layer is stacked on the substrate so as to face the analog integrated circuit, and digital ground layers are stacked on the substrate so as to face the digital integrated circuit. The analog ground terminal is connected to the analog ground layer, and the digital ground terminals are connected to the digital ground layers, respectively.

Abstract: Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer.

Abstract: A structure includes a first package component, and a second package component over and bonded to the first package component. A supporting material is disposed in a gap between the first package component and the second package component. A molding material is disposed in the gap and encircling the supporting material.

Abstract: A stacked die package includes a package substrate, a first die mounted on the package substrate and electrically connected to the package substrate, a second die electrically connected to the package substrate, and an interposer mounted on the package substrate and including a plurality of vertical electrical connection means electrically connecting the package substrate to the second die. At least part of the first die is disposed between the second die and the package substrate in a vertical direction.

Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, including a film for flip chip type semiconductor back surface for protecting a back surface of a semiconductor element flip chip-connected onto an adherend, and a dicing tape, the dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material, the film for flip chip type semiconductor back surface being formed on the pressure-sensitive adhesive layer, in which the pressure-sensitive adhesive layer is a radiation-curable pressure-sensitive adhesive layer whose pressure-sensitive adhesive force toward the film for flip chip type semiconductor back surface is decreased by irradiation with a radiation ray.

Abstract: A steam distribution apparatus having a heat exchanger header defining a chamber; steam distribution apparatus communicating with the heat exchanger chamber; a source of steam at a pressure higher than atmospheric; a heat exchanger having one end communicating with the source of steam and another end for communicating with the chamber and steam dispersion apparatus; and a valve. The valve operates the heat exchanger in an open-loop configuration which supplies humidification steam to the steam distribution apparatus at atmospheric pressure and operates the heat exchanger in a closed-loop at the steam pressure higher than atmospheric for heating the heat exchanger chamber wherein condensate within the chamber or steam distribution apparatus can be converted back to humidification steam.

Abstract: The invention relates to remotely operated laser sintering systems and methods for manufacturing pellets containing highly radioactive elements. The highly radioactive elements can be recovered from used nuclear fuels. The systems and methods of the invention employ a feed composition including one or more highly radioactive elements and a ceramic matrix material. The feed composition is distributed in the form of a layer and sintered by directing at least one laser beam to form a pattern in the layer of the feed composition. The pattern corresponds to the shape of the pellet. Further, the sintering process can be repeated as necessary to achieve a pre-determined pellet height.

Abstract: A method is provided for producing an article which is transparent to visible and infrared radiation. The method includes the steps of forming a green body from a population of nanoparticles; depositing a layer of ZnS powder over the green body, thereby producing a covered green body; and sintering the covered green body, thereby producing a sintered product.

Abstract: A method of manufacturing a plate workpiece with surface microstructures is provided. Before press-molding, a preform is placed between a first mold with a pattern and a second mold, and is disposed on the second mold. Next, the first mold and the second mold are heated to a transition temperature of the preform, and then pressed against the preform to impress the pattern onto the preform to obtain a patterned preform. Finally, the patterned preform is cooled with the second mold and shrunk to obtain the plate workpiece with surface microstructures. Since the patterned preform is uniformly cooled from bottom to top by thermal conduction, the temperature field is isothermal in a horizontal distribution. Therefore, a plate workpiece with high accuracy surface microstructures is obtained, and is useful for carrying multiple optical fibers in optical communication.

Abstract: A drill guide employs multiple layers of materials with different mechanical properties in order to achieve concurrent goals of rigidity, fit and retention. For example, a rigid exterior shell and a soft interior may be used together to securely and precisely fit a drill guide to a surgical site.

Abstract: A method of forming a nanopore in a lipid bilayer is disclosed. A nanopore forming solution is deposited over a lipid bilayer. The nanopore forming solution has a concentration level and a corresponding activity level of pore molecules such that nanopores are substantially not formed un-stimulated in the lipid bilayer. Formation of a nanopore in the lipid bilayer is initiated by applying an agitation stimulus level to the lipid bilayer. In some embodiments, the concentration level and the corresponding activity level of pore molecules are at levels such that less than 30 percent of a plurality of available lipid bilayers have nanopores formed un-stimulated therein.

Abstract: A multi-layered wiper for removing a product (e.g., a cosmetic product) from an applicator. The multi-layered wiper comprises a wiping body having a wiping face, an acute wiping tip, and vertical slits, formed of a first material, over-molded to a retention body, formed of another material harder than the first material. By virtue of having a multi-layered wiper comprising a wiping body, formed of a first material, over-molded to a retention body, formed of another material, harder than the first material, the multi-layered wiper is capable of providing exceptional installation characteristics, while simultaneously providing exceptional wiping characteristics.

Abstract: A method and apparatus of controlling commencement of an injection of a melt stream of moldable material from an auxiliary injection unit. A sensor is placed in an injection molding system to sense a condition related to an injection of a first melt stream of a first moldable material provided by a primary injection unit. Commencement of a second melt stream of a second moldable material from the auxiliary injection unit is initiated upon the sensed condition related to the injection of the first melt stream being detected at a preselected value. The sensed condition may be a pressure, velocity or temperature of the first melt stream as provided by a direct sensor, a force or strain on a hot runner component as provided by an indirect sensor or the occurrence of a function of the injection molding system as provided by a functional sensor.

Abstract: A method of reducing the diameter of pores formed in a graphene sheet includes forming at least one pore having a first diameter in the graphene sheet such that the at least one pore is surrounded by passivated edges of the graphene sheet. The method further includes chemically reacting the passivated edges with a chemical compound. The method further includes forming a molecular brush at the passivated edges in response to the chemical reaction to define a second diameter that is less than the initial diameter of the at least one pore.

Abstract: The present disclosure pertains to resins/filler composites that are formed via a resin infusion process. Certain embodiments are directed to methods and systems that may be used to produce a moulded composite article. An exemplary method comprising: a) filling to a predetermined level a mould tool with particles; b) infusing a resin composition into the mould tool filled with the particles in order to form a composite; c) vibrating the mould tool for a portion of time at one or more of the following stages: during the filling with the particles, after the filling with particles, during the infusing of the resin composition and after the infusions of the resin composition; wherein the composite comprises between 10% to 50% by weight of the resin composition and between 50% to 90% by weight of the particles; and d) curing the composite to form a moulded composite article.

Abstract: Rechargeable lithium-sulfur batteries having a cathode that includes a graphene-sulfur nanocomposite can exhibit improved characteristics. The graphene-sulfur nanocomposite can be characterized by graphene sheets with particles of sulfur adsorbed to the graphene sheets. The sulfur particles have an average diameter less than 50 nm.

Abstract: The invention relates to an apparatus for forming a layered mat of non-oriented particles in a particle board production process, comprising first rollers for size-fractionating a continuous stream of particles into a first and a second fraction; second rollers arranged lower than the first rollers, to receive the first fraction, the second rollers being capable of further size-fractionating said first fraction; and third rollers arranged lower than the second rollers, for receiving said second fraction, the third rollers being capable for further size-fractionating said second fraction; the apparatus further comprising a receiving surface, movable along a longitudinal dimension of the apparatus, and arranged to receive said fractionated first fraction and said fractionated second fraction from said second and third rollers, at different longitudinal positions; wherein the first rollers and the third rollers are pin-type rollers.

Abstract: A method is for molding a gas hydrate pellet for improving convenience of handling of a natural gas hydrate during transportation and storage, and thereby improving the practical use of the natural gas hydrate. Gas hydrate slurry is fed in a compression chamber, and pressure and compression are applied to the gas hydrate slurry by advancing a compression plunger. At that time, a stroking speed of the compression plunger is set minimum, preferably less than a value expressed by a stroke length of the compression plunger at compression×10?2 (m/min). By advancing the compression plunger at low speed, binding between particles of the gas hydrate is tightened, thereby the gas hydrate pellet with increased shearing strength can be molded.

Abstract: The disclosure generally relates to a solid state non-proportional, adjustable, tapered drawing die and an oriented polymer article formed therefrom. More specifically, embodiments relate to a non-proportional draw die used to produce oriented, dimensionally accurate, symmetric or asymmetric polymer composite profiles having simple profiles or complicated profiles with multiple edges. Moreover, the draw die of the disclosure prevents natural flattening of the edges of the final profile during the solid state die drawing process of the oriented polymer composite.

Abstract: The invention describes a flexible tubular article for transport of volatile hydrocarbons comprising: (a) an inner layer of a polyvinylidene difluoride (PVDF) polymer or a polyvinylidene difluoride copolymer; (b) an intermediate thermoplastic polyurethane (TPU) layer extruded in tubular form over the inner PVDF layer, and (c) a polyvinyl chloride polymer extruded in tubular form over the outside surface of the intermediate layer and being coextensive therewith. The tubular articles of the invention have a maximum permeation rating of 15 g/m2/day under SAE J1737 test conditions.

Abstract: The present invention relates to a device for coating electrically conductive wires, comprising multiple units in the following arrangement: a unit (1) for feeding in the wires, a unit (2) for the pretreatment of the wires, a unit (5) for applying a coating agent, a unit (6) for the post-treatment of the coated wires, a unit (8) for winding up the coated wire.

Abstract: An antimicrobial, molded laminate shopping cart part and method of manufacturing same are provided. The part, such as a small child seat, includes a structural carrier made from a thermoplastic resin and having an outer surface. The part further includes a formed plastic film sheet having upper and lower surfaces. The lower surface is bonded to the outer surface of the carrier. The film sheet includes an outer clear plastic layer including at least one antimicrobial agent disbursed throughout the plastic layer. The antimicrobial agent exhibits controlled migration through the clear plastic to the outer surface of the clear plastic layer.

Abstract: A method of treating a net (2) formed from interconnecting strands (4a, 4b) of ultra-high-molecular-weight polyethylene (UHMWPE), the net (2) being formed with knotless intersections (6), comprising the steps of: a) heating the net (2) to a temperature of from 80° to 135° C.; b) applying tension to the net (2); c) reducing the temperature to below 80° C.; and d) removing tension from the net (2).

Abstract: Method and tooling apparatus for forming a composite charge into a stringer having an I-shaped cross-section. A substantially flat composite charge is placed on a die set and pressed formed into a die set cavity to form a stringer hat. A stringer base is formed by press forming the composite charge against the die set. The die set is used to compress the stringer hat into a stringer web having a bulb on one end thereof. A stringer cap is formed by press forming the bulb within a recess in the die set.

Abstract: Systems and methods for molding shells for fluid-filled prosthetic implants, including spinning and rotating dip- or spray-mandrels during a devolatilization step to ensure an even covering. The mandrels may be spun during the dipping or spraying step, and/or afterward while a solvent evaporates until a gum state is formed. The techniques are particularly useful for forming hollow shells from silicone dispersions for soft implants, such as breast implants.