Abstract: A test structure and method are provided to facilitate developing or optimizing a fabrication process by determining values of one or more lithography process parameters for use in semiconductor device fabrication. The test structure is configured to facilitate determining values of the one or more fabrication process parameters, and includes a plurality of test structure components arranged on a substrate according to a test pattern. The test pattern may be based on: varying distances between the test structure components according to a first rule; varying distances between centers of the test structure components according to a second rule; and/or varying at least one dimension of the test structure components according to a third rule. The method may further include determining dimensions of one or more components of the test structure using, for example, scatterometry, and using the dimensions of the components to ascertain one or more fabrication process parameters.

Abstract: A test structure includes an active region formed in a semiconducting substrate, a first line formed above and extending over an upper surface of the active region, and a first isolation region formed in the semiconducting substrate, wherein the active region surrounds the first isolation region. The test structure further includes a first extension formed above the active region and on and in contact with an upper surface of the first isolation region, wherein the first extension extends laterally over the upper surface of the active region from a first side of the first line. Additionally, the first line and the first extension are comprised of at least one of a high-k layer of insulating material and a metal layer.

Abstract: A display device having repair and detect structure includes a substrate, a pixel array, a first shorting bar and a first repair line. The pixel array disposed on the substrate includes a plurality of data lines and a plurality of gate lines. The first shorting bar disposed on the substrate is connected to the gate lines for testing the gate lines, and the first shorting bar includes a first shorting segment. The first repair line is disposed on the substrate for repairing at least one of the data lines. The first shorting segment of the first shorting bar is electrically connected to the first repair line. Furthermore, another repair and detect structure of a display device is disclosed, wherein the first shorting bar includes a first shorting segment, the first repair line includes a first repair segment, and the first shorting segment overlaps with the first repair segment.

Abstract: A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes.

Abstract: A flat panel detector comprises a photoelectric conversion layer and a pixel detecting element disposed under the photoelectric conversion layer. The pixel detecting element comprises: a pixel electrode for receiving charges, a storage capacitor for storing the received charges, and a thin film transistor for controlling outputting of the stored charges. The storage capacitor comprises a first electrode and a second electrode. The first electrode comprises an upper electrode and a bottom electrode that are disposed opposite to each other and electrically connected. A second electrode is sandwiched between the upper electrode and the bottom electrode. It is insulated between the upper electrode and the second electrode and between the second electrode and the bottom electrode.

Abstract: A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.

Abstract: An electrooptic device substrate includes a scan line that is provided on an element substrate, a foundation insulating layer, a semiconductor layer provided on the foundation insulating layer, a gate insulating layer, recesses that are provided at both sides of the semiconductor layer so as to penetrate through the foundation insulating layer and the gate insulating layer, a gate electrode that is provided on the gate insulating layer and is electrically connected to the scan line in the recesses, an insulating interlayer that covers the gate insulating layer, the gate electrode, and the recesses, and a data line that is provided on the insulating interlayer so as to overlap with the scan line, the semiconductor layer, the gate electrode, and the recesses. The recesses include first recesses that overlap with the scan line and second recesses that extend to outer sides of the scan line.

Abstract: An object of the present invention is to provide an EL display device, which has a high operating performance and reliability. A third passivation film 45 is disposed so as to be in contact with an EL element 203 which comprises a pixel electrode (anode) 46, an EL layer 47 and a cathode 48, to make a structure in which heat generated by the EL element 203 is radiated. Further, the third passivation film 45 prevents alkali metals within the EL element 203 from diffusing into the TFTs side, and prevents moisture and oxygen of the TFTs side from penetrating into the EL element 203. More preferably, heat radiating effect is given to a fourth passivation film 50 to make the EL element 203 to be enclosed by heat radiating layers.

Abstract: A nitride light emitting device comprises a current blocking Schottky junction zone formed below the p-electrode and above the active region so that current injection from the p-electrode to the area of the active region that is vertically shaded by the p-electrode is blocked by the Schottky junction zone. A method for fabricating the same is also provided.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a buffer layer on a substrate, an graded aluminum gallium nitride (AlGaN) layer disposed on the buffer layer, a gallium nitride (GaN) layer disposed on the graded AlGaN layer, a second AlGaN layer disposed on the GaN layer and a gate stack disposed on the second AlGaN layer. The gate stack includes one or more of a III-V compound p-doped layer, a III-V compound n-doped layer, an aluminum nitride (AlN) layer between the III-V compound p-doped and n-doped layers, and a metal layer formed over the p-doped, AlN, and n-doped layers. A dielectric layer can also underlie the metal layer.

Abstract: The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of AlzGa(1-z)N, a resistance-reducing layer of AlxGa(1-x)N disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the HEMT. A channel layer of GaN is disposed beneath the mobility-enhancing layer, wherein a 2DEG resides, forming the channel of the HEMT.

Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.

Abstract: A semiconductor device includes: an FET chip; pads provided on an upper surface of the FET chip; bumps provided on at least one of the pads; leads having first portions that are connected to the FET chip by the bumps and extend along the upper surface of the FET chip, and second portions that contact surfaces of the first portions along the upper surface of the FET chip and extend along a side surface of the FET chip, the first and second portions being formed by press or cutting; and a seal layer that seals the FET chip and the leads and a surface from which the second portions of the leads are exposed, the surface of the seal layer being on a lower surface side of the FET chip.

Abstract: A semiconductor light emitting device includes a light-transmissive substrate, a light-transmissive buffer layer disposed on the light-transmissive substrate, and a light emitting structure. The light-transmissive buffer layer includes a first layer and a second layer having different refractive indices and disposed alternately at least once. The light emitting structure includes a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially disposed on the buffer layer.

Abstract: A nitride semiconductor light emitting device includes a substrate, a multi-layer structure, a light-transmitting concave-convex structure and a light emitting structure. The multi-layer structure has layers of a first layer and a second layer such that the first and second layers have different refractive indexes and are alternately stacked. The concave-convex structure is disposed in an upper surface of the multi-layer structure and includes a light-transmitting material. The light emitting structure is disposed on the multi-layer structure and includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer.

Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

Abstract: A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die.

Abstract: According to an embodiment, a semiconductor light emitting device includes a light emitting body including a semiconductor light emitting layer, a support substrate supporting the light emitting body, and a bonding layer provided between the light emitting body and the support substrate, the bonding layer bonding the light emitting body and the support substrate together. The device also includes a first barrier metal layer provided between the light emitting body and the bonding layer, and an electrode provided between the light emitting body and the first barrier metal layer. The first barrier layer includes a first layer made of nickel and a second layer made of a metal having a smaller linear expansion coefficient than nickel, and the first layer and the second layer are alternately disposed in a multiple-layer structure. The electrode is electrically connected to the light emitting body.

Abstract: This invention relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a chlorosilane gas, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C. but less than 2000° C.; with the proviso that the pressure within the reaction chamber is maintained in the range of 0.1 to 760 torr. This invention also relates to a method for depositing silicon carbide material onto a substrate such that the resulting substrate has a carrier lifetime of 0.5-1000 microseconds, the method comprising a. introducing a gas mixture comprising a non-chlorinated silicon-containing gas, hydrogen chloride, a carbon-containing gas, and hydrogen gas into a reaction chamber containing a substrate; and b. heating the substrate to a temperature of greater than 1000° C.

Abstract: A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors.

Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.

Abstract: Provided are a technology that simply forms a particular crystal surface such as a {03-38} surface having high carrier mobility in trench sidewalls and a SiC semiconductor element where most of the trench sidewalls appropriate for a channel member are formed from {03-38} surfaces. A trench structure formed in a (0001) surface or an off-oriented surface of a (0001) surface with an offset angle 8° or lower of SiC is provided. The channel member is in the trench structure. At least 90% of the area of the channel member is a {03-38} surface or a surface that a {03-38} surface offset by an angle from ?8° to 8° in the <1-100> direction. Specifically, the trench sidewalls are finished to {03-38} surfaces by applying a thermal etching to a trench with (0001) surfaces of SiC. Thermal etching is conducted in a chlorine atmosphere above 800° C. with nitrogen gas as the carrier.

Abstract: A display device includes a substrate and pixels arranged on the substrate in a matrix form. The substrate includes a display area in which the pixels are arranged and a non-display area disposed adjacent to a side of the display area. Each pixel includes a cover layer that extends in a row direction that includes a sidewall portion connected to the substrate and a cover portion spaced apart from the substrate and connected to the sidewall portion to define a tunnel-shaped cavity on the substrate. A width of the sidewall portion between adjacent pixels is less than a width of the sidewall portion disposed at an outermost position, and the cover layer seals one side of the tunnel-shaped cavity in the pixels arranged in a first row and a last row.

Abstract: A pixel structure of a display panel includes a gate line, a first data line, a second data line, a first active switching device, a second active switching device, a first pixel electrode and a second pixel electrode. The first pixel electrode is electrically connected to the first active switching device. The first pixel electrode includes a first main electrode disposed adjacent to one side of the first data line, and a second main electrode disposed adjacent to one side of the second data line. The second pixel electrode is electrically connected to the second active switching device. The second pixel electrode is disposed between the first main electrode and the second main electrode of the first pixel electrode.

Abstract: A light-emitting diode (LED) display substrate, a method for manufacturing the same, and a display device are provided and involve the display field. The method for manufacturing the LED display substrate comprises: forming a transparent conductive anode (201) on a substrate (200); forming a pixel region defined by a first PDL (202) and a second PDL (203) on the substrate (200) on which the anode (201) is formed, in which the second PDL (203) made of a hydrophobic material is disposed on the first PDL (201) made of a hydrophilic material; filling a luminescent material into the pixel region to form an emission layer (204) with the luminescent material; and forming a conductive cathode (205) on the substrate (200) on which the emission layer (204) is formed. The manufacturing method allows the luminescent materials to be flatly laid on the LED display substrate so as to improve the luminous quality of the LED display substrate.

Abstract: Provided is a light-emitting device package strip that includes a lead frame strip, a plurality of resin molding products that are injection-molded in the lead frame strip, and runner and gate members that are formed between adjacent resin molding products and on end sides of a line of adjacent resin molding products, each runner and gate member having a smaller thickness than a thickness of the resin molding products to facilitate cutting thereof.

Abstract: The light emitting device is provided with a substrate, semiconductor light emitting elements mounted on the substrate, a mold frame that surrounds the periphery of the light emitting elements on the substrate, and resin layers that fill the inside of the mold frame. The mold frame includes a first mold frame, and a second mold frame formed on top of the first mold frame. The resin layers include a first resin layer that embeds the light emitting elements in resin and is formed with a height approximately equal to the height of the top of the first mold frame, and a second resin layer on top of the first resin layer that is formed with a height approximately equal to the height of the top of the second mold frame. At least one of the resin layers (which are the first resin layer and the second resin layer) includes wavelength-shifting material to change the wavelength of light emitted from the semiconductor light emitting elements.

Abstract: A semiconductor light-emitting device can include a wavelength converting layer including a surrounding portion, which covers at least one semiconductor light-emitting chip in order to emit various colored lights including white light. The semiconductor light-emitting device can include a substrate, a frame located on the substrate, the chip mounted on the substrate, a transparent material layer located on the wavelength converting layer so as to reduce from the wavelength converting layer toward a light-emitting surface thereof, and a reflective material layer disposed at least between the frame and both side surfaces of the wavelength converting layer and the transparent material layer.

Abstract: An embodiment of the invention provides a display panel, which includes a substrate having a pixel region and a peripheral region, a control element overlying the pixel region of the substrate, a conducting layer overlying the substrate in the peripheral region, a first insulating layer overlying the conducting layer in the peripheral region, wherein a ratio between an area of the first insulating layer and an area of the conducting layer in the peripheral region is between about 0.27 and 0.99, a lower electrode layer overlying the first insulating layer, and a second insulating layer overlying the lower electrode layer.

Abstract: In accordance with certain embodiments, semiconductor dies are embedded within polymeric binder to form, e.g., light-emitting dies and/or composite wafers containing multiple light-emitting dies embedded in a single volume of binder.

Abstract: Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.

Abstract: A display panel includes: a mounting substrate including light-emitting elements that are mounted for each pixel on a wiring substrate, in which the light-emitting elements have different luminescence wavelengths from each other; and a counter substrate provided in opposition to a surface, of the mounting substrate, on which the pixels are disposed, and including a light-shielding layer and a light diffusion layer. The light-shielding layer is provided on a surface, of a light transmissive substrate, that faces the pixels and has apertures at respective positions that face the light-emitting elements. The light diffusion layer blocks up the apertures, is provided on a surface, of the light-shielding layer, that faces the pixels, is at least in contact with end edges of the respective apertures, and forms a gap together with the light-emitting elements between the light diffusion layer and the light-emitting elements.

Abstract: In various embodiments, a rigid lens is attached to a light-emitting semiconductor die via a layer of encapsulant having a thickness insufficient to prevent propagation of thermal expansion mismatch-induced strain between the rigid lens and the semiconductor die.

Abstract: Disclosed is a mixed light LED structure which is a solid-state phosphor plate manufactured by mixing phosphor and resin, and the solid-state phosphor plate is installed in a carrier and covered onto the top of a light emitting chip, and a specific ratio relation between the area of the solid-state phosphor plate and the area of the light emitting chip area or a specific ratio relation between the area of the solid-state phosphor plate and the area a light emitting hole are used. and also the relation of limiting the distance between the solid-state phosphor plate and the light emitting chip is satisfied, so as to achieve a better mixed light effect and a longer service life of the mixed light LED structure.

Abstract: According to one embodiment, a semiconductor light emitting device includes: a mounting substrate; a semiconductor light emitting element; a first resin; and a second resin. The semiconductor light emitting element includes: a semiconductor layer including a light emitting layer; a p-side electrode; a p-side interconnection unit; an n-side electrode; and an n-side interconnection unit. The first resin covers a periphery of the semiconductor light emitting element on the substrate and contains a phosphorescent substance capable of being excited by emission light of the light emitting layer. The second resin is provided on the first resin layer and the semiconductor light emitting element and contains a fluorescent body capable of being excited by emission light of the light emitting layer to emit light of a different peak wavelength from emission light of the light emitting layer.

Abstract: According to one embodiment, a semiconductor light emitting device includes: a semiconductor layer; a p-side electrode; an n-side electrode; and a fluorescent body layer. The p-side electrode is provided on a second surface side of the semiconductor layer. The n-side electrode is provided on the second surface side of the semiconductor layer. The fluorescent body layer is provided on a first surface side of the semiconductor layer and contains a plurality of fluorescent bodies configured to be excited by emission light of the light emitting layer and emit light of a different wavelength from the emission light and a bonding material integrating the plurality of fluorescent bodies and configured to transmit the emission light. An average spacing between adjacent ones of the fluorescent bodies is narrower than a peak wavelength of emission light of the light emitting layer.

Abstract: A light emitting diode (LED) lens comprises a light incident surface on a bottom surface of the LED lens facing a light source. A light exit surface, having a size greater than the bottom surface, is defined by a top surface of the LED lens. A planar portion, emitting light incident through the light incident surface, is in a central region of the light exit surface. At least one protrusion portion, protruding to be stepped with respect to the planar portion, is in a region of the light exit surface except for the central region. A reflective surface, defined by lateral surfaces of the LED lens between the top surface of the LED lens and the bottom surface thereof, guides the light incident through the light incident surface, and contacts a lower portion of the light exit surface corresponding to a boundary between the protrusion and the planar portions.

Abstract: LED dies, emitting blue light, are provided on a first support substrate to form a light emitting layer. A mixture of a transparent binder, yellow phosphor powder, magenta-colored glass beads, and cyan-colored glass beads is printed over the light emitting surface. The mixture forms a wavelength conversion layer when cured. The beads are sized so that the tops of the beads protrude completely through the conversion layer. When the LED dies are on, the combination of the yellow phosphor light and the blue LED light creates white light. When the LEDs are off, white ambient light, such as sunlight, causes the conversion layer to appear to be a mixture of yellow light, magenta light, and cyan light. The percentage of the magenta and cyan beads in the mixture is selected to create a desired off-state color, such as a neutral color, of the conversion layer for aesthetic purposes.

Abstract: There is provided a semiconductor light emitting device including a substrate having light transmission properties and including a first surface and a second surface opposed to the first surface, a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer sequentially disposed on the first surface of the substrate, a first electrode and a second electrode connected to the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, and a window layer disposed on the second surface of the substrate, the window layer being formed of a light transmissive material which is different from a material of the substrate and including inclined side surfaces.

Abstract: A light emitting element includes: a sapphire substrate having a front surface and a rear surface opposite the front surface; a first conductive type semiconductor layer stacked on the front surface of the sapphire substrate; a light emitting layer stacked on the first conductive type semiconductor layer; a second conductive type semiconductor layer stacked on the light emitting layer; a reflective layer which contains Ag and is disposed on the rear surface of the sapphire substrate, the reflective layer reflecting light from the sapphire substrate toward the front surface of the sapphire substrate; and an adhesive layer which is interposed between the sapphire substrate and the reflective layer and is made of ITO, the adhesive layer being adhered to the reflective layer.

Abstract: An article, such as a light emitting device, can include a first material and a second material, wherein the first material is capable of emitting first radiation having a first emission maximum at a first wavelength, and the second material is capable of emitting second radiation in response to capturing the first radiation. The second material can have a second emission maximum at a second wavelength within the visible light spectrum. In an embodiment, the second material can be different from the first material. In another embodiment, a difference between the first wavelength and the second wavelength can be at least approximately 70 nm. Additionally, the second material can include a luminescent material having a formula of Gd3(x)Y3(1-x)Al5(y)Ga5(1-y)O12, where x is at least approximately 0.2 and no greater than approximately 0.99 and y is at least approximately 0.05 and no greater than approximately 0.99.

Abstract: A high efficiency light emitting diode with a composite high reflectivity layer integral to said LED to improve emission efficiency. One embodiment of a light emitting diode (LED) chip comprises an LED and a composite high reflectivity layer integral to the LED to reflect light emitted from the active region. The composite layer comprises a first layer, and alternating plurality of second and third layers on the first layer, and a reflective layer on the topmost of said plurality of second and third layers. The second and third layers have a different index of refraction, and the first layer is at least three times thicker than the thickest of the second and third layers. For composite layers internal to the LED chip, conductive vias can be included through the composite layer to allow an electrical signal to pass through the composite layer to the LED.

Abstract: A light emitting diode package having heat dissipating slugs is provided. The light emitting diode package comprises first and second heat dissipating slugs formed of a conductive material and spaced apart from each other; a package main body coupled to the first and second heat dissipating slugs to support the first and second heat dissipating slugs; and a light emitting diode die electrically connected to the first and second heat dissipating slugs, wherein the respective first and second heat dissipating slugs are exposed to the outside through lower and side surfaces of the package main body. As such, the first and second heat dissipating slugs can be used as external leads.

Abstract: An optical electrical device comprises a base and a transparent conductive structure on the base is disclosed. The base further comprises a light-emitting device and the transparent conductive structure comprises a transparent conductive oxide layer and a passivation layer on the transparent conductive oxide layer. The material of the transparent conductive oxide layer comprises transparent conductive metal oxide, such as ZnO. Furthermore, the transparent conductive metal oxide also comprises impurities, such as a carrier e.g. gallium.

Abstract: The invention provides a primer composition which adheres a substrate mounting an optical semiconductor device and a cured material of an addition reaction curing silicone composition that encapsulates the optical semiconductor device, includes (A) silazane compound or polysilazane compounds that has one or more silazane bonds in the molecule, (B) acrylic resin containing either one or both of acrylate ester and methacrylate ester that contains one or more SiH groups in the molecule, and (C) solvent. There can be provided a primer composition in which the adhesion between a substrate mounting an optical semiconductor device and a cured material of an addition reaction curing silicone composition that encapsulates the optical semiconductor device can be improved, the corrosion of a metal electrode on the substrate can be prevented, and the heat resistance and flexibility of a primer can be improved.

Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof, belonging to a field of field effect transistor logic device and the circuit in CMOS ultra large scale integrated circuit (ULSI). The tunneling field effect transistor includes a control gate, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, where the highly-doped source region and the highly-doped drain region lie on both sides of the control gate, respectively, the control gate has a strip-shaped structure with a gate length greater than a gate width, and at one side thereof is connected to the highly-doped drain region and at the other side thereof extends laterally into the highly-doped source region; a region located below the control gate is a channel region; and the gate width of the control gate is less than twice width of a source depletion layer.

Abstract: A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.

Abstract: Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

Abstract: A semiconductor device includes a III-nitride substrate and a first III-nitride epitaxial layer coupled to the III-nitride substrate and comprising a drift region, a channel region, and an extension region. The channel region is separated from the III-nitride substrate by the drift region. The channel region is characterized by a first width. The extension region is separated from the drift region by the channel region. The extension region is characterized by a second width less than the first width. The semiconductor device also includes a second III-nitride epitaxial layer coupled to a top surface of the extension region, a III-nitride gate structure coupled to a sidewall of the channel region and laterally self-aligned with respect to the extension region, and a gate metal structure in electrical contact with the III-nitride gate structure and laterally self-aligned with respect to the extension region.