Abstract: A method of manufacturing an array substrate for an FFS mode LCD device includes forming a gate line, a gate electrode and a pixel electrode on a substrate; forming a gate insulating layer; forming a data line, source and drain electrodes, and a semiconductor layer on the gate insulating layer, the drain electrode overlapping the pixel electrode; forming a passivation layer on the data line, the source and drain electrodes; forming a contact hole exposing the drain electrode and the pixel electrode by patterning the passivation layer and the gate insulating layer; and forming a common electrode and a connection pattern on the passivation layer, wherein the common electrode includes bar-shaped openings and a hole corresponding to the contact hole, and the connection pattern is disposed in the hole, is spaced apart from the common electrode and contacts the drain electrode and the pixel.

Abstract: One object is to provide a method for manufacturing a display device in which shift of the threshold voltage of a thin film transistor including an oxide semiconductor layer can be suppressed even when ultraviolet light irradiation is performed in the process for manufacturing the display device. In the method for manufacturing a display device, ultraviolet light irradiation is performed at least once, a thin film transistor including an oxide semiconductor layer is used for a switching element, and heat treatment for repairing damage to the oxide semiconductor layer caused by the ultraviolet light irradiation is performed after all the steps of ultraviolet light irradiation are completed.

Abstract: A method of fabricating an (Al,Ga,In)N laser diode, comprising depositing one or more III-N layers upon a growth substrate at a first temperature, depositing an indium containing laser core at a second temperature upon layers deposited at a first temperature, and performing all subsequent fabrication steps under conditions that inhibit degradation of the laser core, wherein the conditions are a substantially lower temperature than the second temperature.

Abstract: A manufacturing method of a semiconductor element comprises the steps of (a) preparing a growth substrate, (b) forming a semiconductor layer on the growth substrate, (c) dividing the semiconductor layer into a plurality of elements while leaving at least a part of the semiconductor layer between each element to form a sacrificial layer around each element, (d) forming a metal layer on the semiconductor layer, (e) bonding a supporting substrate to the semiconductor layer via the metal layer, and (f) removing the growth substrate from the semiconductor layer by irradiating a laser whose area of irradiation covers each element within an outline of the sacrificial layer of each element.

Abstract: A nitride semiconductor device includes a silicon substrate, a nitride semiconductor layer formed on the silicon substrate, and metal electrodes formed in contact with the silicon substrate. The metal electrodes has first metal layers which are formed in a shape of discrete islands and in contact with the silicon substrate, and second metal layers which are in contact with the silicon substrate exposed among the islands of the first metal layers and are formed to cover the first metal layers. Further, the second metal layers are made of a metal capable of forming ohmic contact with silicon, and the first metal layers are made of an alloy containing a metal and silicon, in which the metal is different than that in the second metal layer.

Abstract: A method includes bonding a first bond layer to a second bond layer through eutectic bonding. The step of bonding includes heating the first bond layer and the second bond layer to a temperature higher than a eutectic temperature of the first bond layer and the second bond layer, and performing a pumping cycle. The pumping cycle includes applying a first force to press the first bond layer and the second bond layer against each other. After the step of applying the first force, a second force lower than the first force is applied to press the first bond layer and the second bond layer against each other. After the step of applying the second force, a third force higher than the second force is applied to press the first bond layer and the second bond layer against each other.

Abstract: A nano-scale tower structure array having increased surface area on each tower for gathering incident light is provided for use in three-dimensional solar cells. Embodiments enhance surface roughness of each tower structure to increase the surface area available for light gathering. Enhanced roughness can be provided by manipulating passivation layer etching parameters used during a formation process of the nano-scale tower structures, in order to affect surface roughness of a photoresist layer used for the etch. Manipulable etching parameters can include power, gas pressure, and etching compound chemistry.

Abstract: In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.

Abstract: A solid state imaging device includes: a substrate; a photoelectric conversion unit that is formed on the substrate to generate and accumulate signal charges according to light quantity of incident light; a vertical transmission gate electrode that is formed to be embedded in a groove portion formed in a depth direction from one side face of the substrate according to a depth of the photoelectric conversion unit; and an overflow path that is formed on a bottom portion of the transmission gate to overflow the signal charges accumulated in the photoelectric conversion unit.

Abstract: A method of manufacturing an optical sensor includes providing a semiconductor wafer including a plurality of pixel areas, providing a light transmissive substrate including a light transmissive wafer with a plurality of light transmissive members attached thereto, the plurality of light transmissive members being arranged on a first main surface of the light transmissive wafer and each of plurality of light transmissive members emitting ? rays, an amount of the ? rays being smaller than or equal to 0.05 c/cm2·h, fixing the light transmissive substrate onto the semiconductor wafer together by a fixing member, and dividing the semiconductor wafer and the light transmissive substrate that are fixed together into individual pieces.

Abstract: A carrier assembly is provided for solar cell laminates that include an encapsulating layer and that are conveyed through a lamination plant having a conveying surface. The assembly includes a housing of heat conductive material defining an inner volume, the housing having an upper plate for receiving the laminates and a lower plate defining a plurality of apertures, the inner volume including at least one connecting element interconnecting the first and second plates. An air supply system provides a continuous outward air flow through the apertures when the lower plate is received on the conveying surface, wherein the airflow yields an elevated pressure on the lower plate for providing lift to the housing, allowing substantially friction-free movement of the housing relative to the conveying surface. A thermal transfer system provides thermal energy to the upper plate for melting and curing the encapsulating layer.

Abstract: A manufacturing method forms a photoelectric conversion device having a photoreceiving portion provided in a substrate and an interlayer film arranged over the substrate. The method includes forming a layer of a lower etching rate rather than the interlayer film so that the layer of the lower etching rate covers a whole surface of the photoreceiving portion, forming the interlayer film over the layer of the lower etching rate, etching a portion of the interlayer film corresponding to the photoreceiving portion to form a hole penetrating through the interlayer film and reaching the layer of the lower etching rate, and disposing in the hole a material of a higher refractive index rather than the interlayer film.

Abstract: The surface of silicon is textured to create black silicon on a nano-micro scale by electrochemical reduction of a silica layer on silicon in molten salts. The silica layer can be a coating, or a layer caused by the oxidation of the silicon.

Abstract: An integrated circuit device is provided. The integrated circuit device can include a substrate; a first radiation-sensing element disposed over a first portion of the substrate; and a second radiation-sensing element disposed over a second portion of the substrate. The first portion comprises a first radiation absorption characteristic, and the second portion comprises a second radiation absorption characteristic different from the first radiation absorption characteristic.

Abstract: Semiconductor photovoltaic cells have surfaces that are textured for processing and photovoltaic reasons. The absorbing regions may have parallel grooves that reduce loss of solar energy that would otherwise be lost by reflection. One form of texturing has parallel grooves and ridges. The cell also includes regions of metallization for collecting the generated electrical carriers and conducting them away, which may be channels. The topography is considered during production, using a process that takes advantage of the topography to govern what locations upon will receive a specific processing, and which locations will not receive such a processing. Liquids are treated directly into zones of the cell. They migrate throughout a zone and act upon the locations contacted. They do not migrate to other zones, due to impediments to fluid flow that are features of the surface texture, such as edges, walls and ridges.

Abstract: Techniques for using electrodeposition to form absorber layers in diodes (e.g., solar cells) are provided. In one aspect, a method for fabricating a diode is provided. The method includes the following steps. A substrate is provided. A backside electrode is formed on the substrate. One or more layers are electrodeposited on the backside electrode, wherein at least one of the layers comprises copper, at least one of the layers comprises zinc and at least one of the layers comprises tin. The layers are annealed in an environment containing a sulfur source to form a p-type CZTS absorber layer on the backside electrode. An n-type semiconductor layer is formed on the CZTS absorber layer. A transparent conductive layer is formed on the n-type semiconductor layer. A diode is also provided.

Abstract: Methods of fabricating back-contact solar cells and devices thereof are described. A method of fabricating a back-contact solar cell includes forming an N-type dopant source layer and a P-type dopant source layer above a material layer disposed above a substrate. The N-type dopant source layer is spaced apart from the P-type dopant source layer. The N-type dopant source layer and the P-type dopant source layer are heated. Subsequently, a trench is formed in the material layer, between the N-type and P-type dopant source layers.

Abstract: A quantum dot organic light emitting device and a method of manufacturing the same are disclosed. A first electrode layer is formed on a substrate. A block copolymer film which can cause phase separation on the first electrode layer is formed. The block copolymer film is phase-separated into a plurality of first domains, each having a nano size column shape, and a second domain which surrounds the first domains. A quantum dot template film of the second domain, which comprises a plurality of nano size through holes, is formed by selectively removing the first domains. Quantum dot structures, each of which comprises an organic light emitting layer in the through hole of the quantum dot template film, is formed.

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Abstract: A semiconductor device including an oxide semiconductor with stable electric characteristics and high reliability is provided. An island-shaped oxide semiconductor layer is formed by using a resist mask, the resist mask is removed, oxygen is introduced (added) to the oxide semiconductor layer, and heat treatment is performed. The removal of the resist mask, introduction of the oxygen, and heat treatment are performed successively without exposure to the air. Through the oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, whereby the oxide semiconductor layer is highly purified. Chlorine may be introduced to an insulating layer over which the oxide semiconductor layer is formed before formation of the oxide semiconductor layer.

Abstract: A bottom-gate transistor with a short channel length and a method for manufacturing the transistor are provided. A bottom-gate transistor with a short channel length in which portions of a source electrode and a drain electrode which are proximate to a channel formation region are thinner than other portions thereof was devised. In addition, the portions of the source electrode and the drain electrode which are proximate to the channel formation region are formed in a later step than the other portions thereof, whereby a bottom-gate transistor with a short channel length can be manufactured.

Abstract: A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.

Abstract: A light emitting diode array includes a first light emitting diode having a first electrode and a second light emitting diode having a second electrode. The first and second light emitting diodes are separated. A first polymer layer is positioned between the light emitting diodes. An interconnect located at least partially on the first polymer layer connects the first electrode to the second electrode. A permanent substrate is coupled to the light emitting diodes. The permanent substrate is coupled to the side of the light emitting diodes opposite the interconnect. A second polymer layer at least partially encapsulates the side of the light emitting diodes with the interconnect.

Abstract: A device comprising a substrate, an integrated circuit (IC) die attached to the substrate on one side, a plurality of contact pads on an active side of the IC die, a plurality of thermally and electrically conductive legs, each of the legs attached to a respective one of the contact pads, and an encapsulating material formed around the substrate, the IC die, and a portion of the legs. A contact end of each of the legs is exposed, and one of the contact ends conducts a signal from a transistor in the IC die.

Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.

Abstract: A method of forming a device is disclosed. The method includes providing a substrate having a device region. The device region includes a source region, a gate region and a drain region defined thereon. The substrate is prepared with gate layers on the substrate. The gate layers are patterned to form a gate in the gate region and a field structure surrounding the drain region. A source and a drain are formed in the source region and drain region respectively. The drain is separated from the gate on a second side of the gate and the source is adjacent to a first side of the gate. An interconnection to the field structure is formed. The interconnection is coupled to a potential which distributes the electric field across the substrate between the second side of the gate and the drain.

Abstract: A method of fabricating a polycrystalline silicon layer includes: forming an amorphous silicon layer on a substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal; forming a metal layer pattern or metal silicide layer pattern in contact with an upper or lower region of the polycrystalline silicon layer corresponding to a region excluding a channel region in the polycrystalline silicon layer; and annealing the substrate to getter the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer to the region in the polycrystalline silicon layer having the metal layer pattern or metal silicide layer pattern. Accordingly, the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer can be effectively removed, and thus a thin film transistor having an improved leakage current characteristic and an OLED display device including the same can be fabricated.

Abstract: Embodiments of a manufacturing process for recessed gate devices on silicon-on-insulator (SOI) substrate with self-aligned lateral isolation are described. This allows the creation of true in-pitch recessed gate devices without requiring an extra isolation dimension. A lateral isolation trench is formed between pairs of recessed gate devices by etching the silicon-on-insulator area down to a buried oxide layer on which the silicon-on-insulator layer is formed. The position of the trench is self-aligned and defined by the gate width and the dimension of spacers disposed on either side of the gate. The isolation trench is filled with a dielectric material and then etched back to the middle of the SOI body and the remaining volume is filled with a doped conductive material. The doped conductor is subject to a thermal cycle to create source and drain regions of the device through out-diffusion of the doped material.

Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

Abstract: A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

Abstract: A method of fabricating a super junction transistor is provided. A drain substrate is provided. An epitaxial layer is formed on the drain substrate. A plurality of trenches is formed in the epitaxial layer. A buffer layer is formed and is in direct contact with the interior surface of the trenches. A dopant source layer is filled into the trenches. An etching process is performed to form a plurality of recessed structures above the respective trenches. A gate oxide layer is formed on the surface of each recessed trench and the dopants inside the dopant source layer are diffused into the epitaxial layer through the buffer layer to thereby form at least a body diffusion layer of the first conductivity type. A gate conductor is filled into the recessed structures to form a plurality of gate structure units. A doped source region having the first conductivity type is formed.

Abstract: Methods of forming integrated circuit devices include forming a PMOS transistor having a SiGe channel region therein and then exposing at least a portion of the PMOS transistor to a hydrogen plasma. A tensile stress layer may be formed on the PMOS transistor. The exposing step may include exposing source and drain regions of the PMOS transistor to the hydrogen plasma.

Abstract: Transistor devices are formed with a pMOS and an nMOS workfunction stack of substantially equal thickness after gate patterning. Embodiments include forming n-type and p-type areas in a substrate, forming a pMOS workfunction metal stack layer on both areas, forming a hardmask layer on the pMOS workfunction metal stack layer on the n-type area, removing the pMOS workfunction metal stack layer from the p-type area, forming an nMOS workfunction metal stack layer on the p-type area and on the hardmask layer, and removing the nMOS workfunction metal stack layer from the hardmask layer.

Abstract: A method of manufacturing a semiconductor integrated circuit device which includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.

Abstract: When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow.

Abstract: A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

Abstract: Trenches are formed into semiconductive material. Masking material is formed laterally over at least elevationally inner sidewall portions of the trenches. Conductivity modifying impurity is implanted through bases of the trenches into semiconductive material there-below. Such impurity is diffused into the masking material received laterally over the elevationally inner sidewall portions of the trenches and into semiconductive material received between the trenches below a mid-channel portion. An elevationally inner source/drain is formed in the semiconductive material below the mid-channel portion. The inner source/drain portion includes said semiconductive material between the trenches which has the impurity therein. A conductive line is formed laterally over and electrically coupled to at least one of opposing sides of the inner source/drain. A gate is formed elevationally outward of and spaced from the conductive line and laterally adjacent the mid-channel portion. Other embodiments are disclosed.

Abstract: A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a fin in an upper surface of a semiconductor substrate to extend in a first direction, forming a mask film, making a plurality of first trenches in the mask film to extend in a second direction to reach the fin, filling sidewall members into the first trenches, making a second trench by removing the mask film from a portion of a space between the sidewall members, forming a gate insulating film and a gate electrode on a surface of a first portion of the fin disposed inside the second trench, making a third trench by removing the mask film from the remaining space between the sidewall members, and causing a second portion of the fin disposed inside the third trench to become a conductor.

Abstract: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.

Abstract: A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life.

Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then reoxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

Abstract: A semiconductor device according to an embodiment includes a silicon carbide, a metal silicide formed on the silicon carbide and including a first layer and a second layer having a carbon ratio lower than that of the first layer, and a metallic electrode formed on the metal silicide, wherein the second layer is formed on the first layer, and the second layer is in contact with the metallic electrode, and an average grain diameter of a metal silicide in the second layer is larger than an average grain diameter of a metal silicide in the first layer.

Abstract: An NPN bipolar junction transistor is disclosed that exhibits a collector-to-emitter breakdown voltage greater than 10 volts and a beta greater than 300. The large value of beta is obtained by fabricating the transistor with an extra N-type layer that reduces recombination of electrons and holes.

Abstract: The disclosed invention provides a structure and method for providing a high lateral voltage resistance between the electrical networks, sharing a lateral plane, of conductive elements (e.g., having different high voltage potentials) comprising a coupler. In one embodiment, an integrated coupler providing a high lateral voltage resistance comprises a primary conductive element and a secondary conductive element. An isolating material is laterally configured between the electrical network of the primary conductive element and an electrical network of the secondary conductive element. The isolating material may comprise a low-k dielectric layer and prevents any lateral barrier layers (e.g., etch stop layers, diffusion barrier layers, etc.) from extending between the first conductive element and the electrical network of the second conductive element. The structure therefore provides a galvanically isolated integrated coupler which avoids electrical shorting between circuits (e.g.

Abstract: A method of manufacturing a semiconductor device, the method including: preparing a semiconductor substrate including a mold layer and a support layer disposed on the mold layer; forming multiple holes that pass through the mold layer and the support layer; forming multiple bottom electrodes in the holes; exposing at least a portion of the bottom electrodes by removing at least a portion of the mold layer; removing a portion of the bottom electrodes from an exposed surface of the bottom electrodes; and sequentially forming a dielectric layer and a top electrode layer on the bottom electrodes.

Abstract: Some embodiments include methods of forming electrical components. First and second exposed surface configurations are formed over a first structure, and material is then formed across the surface configurations. The material is sub-divided amongst two or more domains, with a first of the domains being induced by the first surface configuration, and with a second of the domains being induced by the second surface configuration. A second structure is then formed over the material. The first domains of the material are incorporated into electrical components. The second domains may be replaced with dielectric material to provide isolation between adjacent electrical components, or may be utilized as intervening regions between adjacent electrical components.

Abstract: A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.

Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

Abstract: Provided is a silica-based film forming material for formation of air gaps, the material being capable of forming air gaps without employing a CVD method. A silica-based film forming material for formation of air gaps including (a) a certain siloxane polymer, (b) an alkanolamine, and (c) an organic solvent is used when a silica-based film is formed with a spin coating method. According to this silica-based film forming material for formation of air gaps, air gaps with a great degree of opening can be formed even when coated with a spin coating method, without filling the recessed parts.