Abstract: A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.

Abstract: The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or substrate, involving the formation of a surface layer, known as the bonding layer, on each substrate, at least one of these bonding layers being formed at a temperature less than or equal to 300° C.; conducting a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature but below 450° C.; forming an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers, and conducting an annealing of the assembled structure at a bonding interface strengthening temperature below 450° C.

Abstract: A method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.

Abstract: It is an object of the present invention to reduce the cost of a wireless chip, further, to reduce the cost of a wireless chip by enabling the mass production of a wireless chip, and furthermore, to provide a downsized and lightweight wireless chip. A wireless chip in which a thin film integrated circuit peeled from a glass substrate or a quartz substrate is formed between a first base material and a second base material is provided according to the invention. As compared with a wireless chip formed from a silicon substrate, the wireless chip according to the invention realizes downsizing, thinness, and lightweight. The thin film integrated circuit included in the wireless chip according to the invention at least has an n-type thin film transistor having an LDD (Lightly Doped Drain) structure, a p-type thin film transistor having a single drain structure, and a conductive layer functioning as an antenna.

Abstract: According to one embodiment, a substrate processing method is disclosed. The above method includes: grinding an outer edge portion on a back surface of a semiconductor wafer with a semiconductor element formed on its front surface with a first grindstone or blade to thereby form an annular groove; grinding a projecting portion on an inner side of the groove with a second grindstone to thereby form a recessed portion integrally with the groove on the back surface of the semiconductor wafer; and grinding a bottom surface of the recessed portion including a ground surface made by the second grindstone with a third grindstone.

Abstract: Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate.

Abstract: While reliably cutting an object to be processed, the strength of the resulting chips is improved. An object to be processed 1 is irradiated with laser light L, so as to form modified regions 17, 27, 37, 47 extending along lines to cut 5 and aligning in the thickness direction in the object 1. Here, modified regions 17 are formed such that modified region formed parts 17a and modified region unformed parts 17b alternate along the lines, and modified regions 47 are formed such that modified region formed parts 47a and modified region unformed parts 47b alternate along the lines. This can inhibit formed modified regions 7 from lowering the strengths on the rear face 21 side and front face 3 side of chips obtained by cutting. On the other hand, modified regions 27, 37 located between the modified regions 17, 47 are formed continuously from one end side of the lines 5 to the other end side thereof, whereby the cuttability of the object 1 can be secured reliably.

Abstract: Example embodiments relate to a method of forming a core-shell structure. According to a method, a region in which the core-shell structure will be formed is defined on a substrate, and a core and a shell layer may be sequentially stacked in the defined region. A first shell layer may further be formed between the substrate and the core. When the core and the shell layer are sequentially stacked in the core-shell region, the method may further include forming a groove on the substrate, forming the first shell layer covering surfaces of the groove, forming the core in the groove of which surfaces are covered by the first shell layer, and forming a second shell layer covering the core.

Abstract: According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor crystal layer. The method can include forming the nitride semiconductor crystal layer having a first thickness on a silicon crystal layer. The silicon crystal layer is provided on a base body. The silicon crystal layer has a second thickness before the forming the nitride semiconductor crystal layer. The second thickness is thinner than the first thickness. The forming the nitride semiconductor crystal layer includes making at least a portion of the silicon crystal layer incorporated into the nitride semiconductor crystal layer to reduce a thickness of the silicon crystal layer from the second thickness.

Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.

Abstract: The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on substrate; forming a patterned photoresist layer on the first material layer; applying an etching process to the first material layer using the patterned photoresist layer as a mask; and applying a nitrogen-containing plasma to the substrate to remove the patterned photoresist layer.

Abstract: A fabrication method for a semiconductor device includes the step of forming a gate insulating film on the side of a trench, the bottom thereof, and the periphery thereof. The step of forming a gate insulating film includes a step of forming a first insulating film on the side of the trench and a step of forming a second insulating film on the bottom and periphery of the trench using a high-density plasma chemical vapor deposition method. The thickness of the portions of the gate insulating film formed on the bottom and periphery of the trench is made larger than that of the portion of the gate insulating film formed on the side of the trench.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a gate structure on the semiconductor substrate. The gate includes a high-k dielectric material. In the method, a fluorine-containing liquid is contacted with the high-k dielectric material and fluorine is incorporated into the high-k dielectric material.

Abstract: A non-transitory computer readable medium encoded with a program for fabricating a gate stack for a transistor is disclosed. The program includes instructions configured to perform a method. The method includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.

Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.

Abstract: A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer.

Abstract: Wire bonds are formed at an integrated circuit device so that multiple wires are bonded to a single bond pad. In a particular embodiment, the multiple wires are bonded by first applying a stud bump to the pad and successively bonding each of the wires to the stud bump. Another stud bump can be placed over the bonded wires to provide additional connection security.

Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.

Abstract: A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.

Abstract: A method of forming a memory device. A first thickness of dielectric material overlies a surface region of a substrate. A first wiring material including a first lining material and a silver material are formed overlying the dielectric material. A first adhesion material and an amorphous silicon switching material including a contact material are deposited overlying the first wiring material. The method forms one or more first structures configured to spatially extend in a first direction from the amorphous silicon switching material, the contact material, and the first wiring material. A thickness of second dielectric material is deposited overlying the one or more first structures. The method forms a second wiring structure comprising at least a second silver material and a second lining material spatially extending in a second direction orthogonal to the first direction overlying the second dielectric material and in electrical contact with the switching material.

Abstract: In a process, an opening is formed to extend from a front surface of a semiconductor substrate through a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A block layer is formed on only a portion of the metal seed layer. A metal layer is formed on the block layer and the metal seed layer to fill the opening.

Abstract: In accordance with the teachings of the present disclosure, methods and apparatus are provided for a semiconductor device having thin anti-reflective layer(s) operable to absorb radiation that may otherwise reflect off surfaces disposed inwardly from the anti-reflective layer(s). In a method embodiment, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first outer sidewall surface has a first minimum refractive index. The method further includes forming an anti-reflective layer outwardly from the first outer sidewall surface. The anti-reflective layer has: a second outer sidewall surface that is not parallel with the substrate, a second refractive index that is greater than the first minimum refractive index, and a second thickness that is less than the first thickness.

Abstract: A pattern forming method is disclosed. The method includes the steps of: forming a dielectric layer on a substrate; forming a first patterned mask on the dielectric layer, wherein the first patterned mask comprises an opening; forming a material layer on the dielectric layer and covering the first patterned mask; forming a second patterned mask on the material layer, wherein the second patterned mask comprises a first aperture; forming a second aperture in the second patterned mask after forming the first aperture, wherein the second aperture and the first aperture comprise a gap therebetween and overlap the opening; and utilizing the second patterned mask as an etching mask for partially removing the material layer and the dielectric layer through the first aperture and the second aperture.

Abstract: Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the opening in the layer of insulating material that exposes a portion of an underlying copper-containing structure, performing a wet etching process to remove the patterned metal hard mask layer, performing a selective metal deposition process through the opening in the layer of insulating material to selectively form a metal region on the copper-containing structure and, after forming the metal region, forming a copper-containing structure in the opening above the metal region.

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a non-active area of the semiconductor wafer. A plurality of contact pads is formed on an active surface of the semiconductor die. A first insulating layer is formed over the semiconductor wafer. A portion of the first insulating layer is removed to expose the contact pads on the semiconductor die. An opening is formed partially through the semiconductor wafer in the active surface of the semiconductor die or in the non-active area of the semiconductor wafer. A second insulating layer is formed in the opening in the semiconductor wafer. A shielding layer is formed over the active surface. The shielding layer extends into the opening of the semiconductor wafer to form a conductive via. A portion of a back surface of the semiconductor wafer is removed to singulate the semiconductor die.

Abstract: Disclosed herein are through silicon vias (TSVs) and contacts formed on a semiconductor material, methods of manufacturing, and design structures. The method includes forming a contact hole in a dielectric material formed on a substrate. The method further includes forming a via in the substrate and through the dielectric material. The method further includes lining the contact hole and the dielectric material with a metal liner using a deposition technique that will avoid formation of the liner in the via formed in the substrate. The method further includes filling the contact hole and the via with a metal such that the metal is formed on the liner in the contact hole and directly on the substrate in the via.

Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique. In one example, the method includes forming a patterned hard mask layer above a layer of insulating material, the patterned hard mask having a hard mask opening, forming an erodible spacer in the hard mask opening to thereby define a spacer opening and performing at least one etching process through the spacer opening on the layer of insulating material to define a trench therein for a conductive structure, wherein the erodible spacer is substantially eroded away during the at least one etching process.

Abstract: The present method of forming an electronic structure includes providing a tantalum base layer and depositing a layer of copper on the tantalum layer, the deposition being undertaken by physical vapor deposition with the temperature of the base layer at 50° C. or less, with the deposition taking place at a power level of 300 W or less.

Abstract: The present invention provides a metal polishing liquid capable of CMP at a high Cu polishing rate and solving the problems: (a) generation of scratches attributable to solid particles, (b) generation of deteriorations in flatness such as dishing and erosion, (c) complexity in a washing process for removing abrasive particles remaining on the surface of a substrate after polishing, and (d) higher costs attributable to the cost of a solid abrasive itself and to waste liquid treatment, as well as a method of polishing a film to be polished by using the same.

Abstract: A pattern-forming method includes forming a silicon-containing film on a substrate, the silicon-containing film having a mass ratio of silicon atoms to carbon atoms of 2 to 12. A shape transfer target layer is formed on the silicon-containing film. A fine pattern is transferred to the shape transfer target layer using a stamper that has a fine pattern to form a resist pattern. The silicon-containing film and the substrate are dry-etched using the resist pattern as a mask to form a pattern on the substrate in nanoimprint lithography. According to another aspect of the invention, a silicon-containing film includes silicon atoms and carbon atoms. A mass ratio of silicon atoms to carbon atoms is 2 to 12. The silicon-containing film is used for a pattern-forming method employed in nanoimprint lithography.

Abstract: Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF6/O2 plasma. Etch selectivity of over 800:1 (Si:SiGe) may be achieved at etch temperatures from ?80 degrees Celsius to ?140 degrees Celsius. High aspect ratio structures with high resolution may be patterned into Si substrates using SiGe as a hard mask layer for construction of microelectromechanical systems (MEMS) devices and semiconductor devices.

Abstract: The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) etching a metal-silicide layer and a POLY layer via a hard mask, wherein the metal-silicide layer is disposed on the POLY layer; (b) forming a POLY recess in the POLY layer; and (c) forming a liner film covering the metal-silicide layer.

Abstract: A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process.

Abstract: The present disclosure provides a method that includes forming a first photoresist layer on a substrate; forming a second photoresist layer over the first photoresist layer; and performing a lithography exposure process to the first photoresist layer and the second photoresist layer, thereby forming a first latent feature in the first photoresist layer and a second latent feature in the second photoresist layer.

Abstract: The method of producing a GaN-based microstructure includes a step of preparing a semiconductor structure provided with a trench formed in a main surface of the nitride semiconductor and a heat-treating mask covering a main surface of the nitride semiconductor excluding the trench, a first heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to form a crystallographic face of the nitride semiconductor on at least a part of a sidewall of the trench, a step of removing the heat-treating mask after the first heat-treatment step and a second heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to close an upper portion of the trench on the sidewall of which the crystallographic face is formed with a nitride semiconductor.

Abstract: A method and an apparatus for treating a silicon substrate for effectively removing a silicon oxide film formed on a surface of a silicon film and improving surface uniformity of the silicon film. The method comprises providing a substrate including a silicon film; providing a first fluid, which is capable of etching a silicon oxide film, to a surface of the substrate in a first time band; providing a second fluid containing water to the surface of the substrate in a second time band, which is different from the first time band; and providing a third fluid, which is capable of etching the silicon oxide film, has different ingredients as compared to the first fluid, and has high etching ratio with respect to the silicon oxide film, to a surface of the substrate in a third time band, which is different from the first time band and the second time band.

Abstract: A problem of a resist mask collapse due to a plasma process is solved. In a method of manufacturing a semiconductor device including steps of a plasma process to a sample having a mask made of an organic material, the plasma process includes a first step of a plasma process under a gas containing any of fluorine, oxygen, or nitrogen, or containing all of them, and a second step of the plasma process under a gas containing a rare gas without containing any of fluorine, oxygen, and nitrogen, and the first step and the second step are repeated.

Abstract: According to one embodiment, a manufacturing method of a semiconductor device includes a step of forming a dummy-fin semiconductor on a semiconductor substrate; a step of forming an insulating layer, into which a lower part of the dummy-fin semiconductor is buried, on the semiconductor substrate; a step of forming a fin semiconductor, which is bonded to a side face at an upper part of the dummy-fin semiconductor, on the insulating layer; and a step of removing the dummy-fin semiconductor on the insulating layer with the fin semiconductor being left on the insulating layer.

Abstract: A stamp having a nanoscale structure and a manufacturing method thereof are disclosed. The stamp includes a substrate, a buffer layer, and a nanoscale stamp layer. The method comprises forming a buffer layer on the substrate, and forming a stamp layer having a nanoscale structure on the buffer layer.

Abstract: In the present invention, a masking solution is supplied to an edge portion of a front surface of a substrate rotated around a vertical axis to form a masking film at the edge portion of the substrate, a hard mask solution is supplied to the front surface of the substrate to form a hard mask film on the front surface of the substrate, a hard mask film removing solution dissolving the hard mask film is supplied to the hard mask film formed at the edge portion of the substrate to remove the hard mask film formed at the edge portion of the substrate, and a masking film removing solution dissolving the masking film is supplied to the masking film to remove the masking film at the edge portion of the substrate.

Abstract: A method of manufacturing a semiconductor device includes: (a) supplying a first process gas from a first process gas supply unit into a process chamber via a flow rate control device to form a film on a substrate; (b) transmitting a signal representing an exhaust pressure detected by a pressure detector to a controller after the first process gas is supplied into the process chamber; (c) controlling a pressure adjustor and the flow rate control device once the signal is received by the controller such that the exhaust pressure reaches a predetermined pressure; (d) supplying a purge gas from a purge gas supply unit into the process chamber to purge an inside atmosphere after forming the first film; and (e) supplying a second process gas from a second process gas supply unit into the process chamber via the flow rate control device to form a second film.

Abstract: A method of manufacturing a thin film transistor (TFT), a TFT manufactured by the method, a method of manufacturing an organic light-emitting display apparatus that includes the TFT, a display including the TFT. By including a buffer layer below and an insulating layer above a silicon layer for the TFT, the silicon layer can be crystallized without being exposed to air, so that contamination can be prevented. Also, due to the overlying insulating layer, the silicon layer can be patterned without directly contacting photoresist. The result is a TFT with uniform and improved electrical characteristics, and an improved display apparatus.

Abstract: A process for coating a semiconductor wafer with a coating composition comprises curing the coating with a pulsed UV light, thereby preventing delamination during reflow operations. In a particular embodiment, the coating composition comprises both epoxy and acrylate resins. The epoxy resin can be cured thermally; the acrylate resin is cured by UV irradiation.

Abstract: A chemical vapor deposition method for forming an aluminum-silicon nitride layer upon a substrate uses an aluminum precursor, a silicon precursor and a nitrogen precursor under chemical vapor deposition conditions to deposit the aluminum-silicon nitride layer upon the substrate. The aluminum-silicon nitride layer has an index of refraction interposed between silicon nitride and aluminum nitride. The aluminum-silicon nitride layer also has a bandgap from about 4.5 to about 6 eV and a permittivity from about 6×10^-11 to about 8×10^-11 F/m. The aluminum-silicon nitride layer may be further thermally annealed to reduce a hydrogen content of the aluminum-silicon nitride layer.

Abstract: An article of manufacture for warming human extremities via graduated thermal insulation with a blanket comprised of concentrations of and transitions to and from concentrations of various types of woven thread fabric or non-woven fabric, having various properties of thermal insulation.

Abstract: The present invention relates to a glass plate for a substrate contains, as a glass matrix composition, in mol % on the oxide basis, SiO2: 67 to 72, Al2O3: 1 to 7, B2O3: 0 to 4, MgO: 11 to 15, CaO: 0 to 3, SrO: 0 to 3, BaO: 0 to 4, ZrO2: 0 to 4, Na2O: 8 to 15, and K2O: 0 to 7, with SiO2+Al2O3: 71 to 77, MgO+CaO+SrO+BaO: 11 to 17, Na2O+K2O: 8 to 17, and satisfying K2O/(Na2O+K2O)?0.13×(SiO2+Al2O3+0.5B2O3+0.3BaO)?9.4, in which the glass plate has a ?-OH value (mm?1) of 0.05 to 0.5, and a heat shrinkage ratio (C) of 16 ppm or less.

Abstract: A method of making ceramic membranes, and the ceramic membranes so formed, comprising combining a ceramic precursor with an organic or inorganic comonomer, forming the combination as a thin film on a substrate, photopolymerizing the thin film, and pyrolyzing the photopolymerized thin film.

Abstract: The object of the present invention is to provide a catalyst regeneration process which can improve catalyst selectivity. A first aspect of the invention is characterized in that a spent catalyst from a reactor is introduced into a first fluidized bed regenerator and contacted with an oxygen-containing gas stream and optional steam to carry out a coke combustion reaction, wherein the resultant mixture of the partially regenerated catalyst and flue gas is introduced into a second fluidized bed regenerator and contacted with steam and an optional oxygen-containing gas stream to carry out a further regeneration reaction, and then the regenerated catalyst is introduced into the reactor. A second aspect of the invention is characterized in that a spent catalyst from a reactor is introduced into a fluidized dense bed regenerator and contacted with an oxygen-containing gas stream and steam to carry out a coke combustion reaction, and then the regenerated catalyst is introduced into the reactor.

Abstract: An agglomerated zeolite adsorbent which comprises 95-99.5 mass % of X zeolite and 0.5-5.0 mass % of binder, wherein the exchangeable cationic sites of said X zeolite are occupied by Group IIA metal and/or K, the total pore volume of said adsorbent is no less than 0.26 mL/g as measured by mercury porosimetry, the volume of pores with pore diameters from 100 to 500 nm is at least 60% based on the total pore volume. During shaping, a pore-forming agent is added to this adsorbent, and then the adsorbent is alkali treated for in-situ crystallization, followed by ion exchange. Said adsorbent has high adsorption capacity, fast mass transfer rate and good mechanical strength. Said adsorbent is suitable for liquid phase adsorptive separation of para-xylene from C8 aromatic hydrocarbons and is also suitable for adsorptive separation of other alkyl aromatic hydrocarbons isomers.

Abstract: A method of making a catalyst containing nanosize zeolite particles supported on a support material is disclosed. A process for making styrene or ethylbenzene by reacting toluene with a C1 source over a catalyst containing nanosize zeolite particles supported on a support material is disclosed.