Abstract: A method for processing substrates includes providing a bonding layer between a substrate and a carrier to bond the substrate to the carrier, processing the substrate while the substrate is supported by the carrier, and removing the bonding layer to separate the substrate from the carrier. The bonding layer may include a thermosetting release layer and thermosetting glue layers, wherein at least one of the thermosetting glue layers is provided on each side of the thermosetting release layer.

Abstract: A method of forming a hybridized device including forming a first component provided with metal bumps, and a second component provided with connection elements, attaching the bumps to the connection elements. The manufacturing of the second component includes forming, on a surface of a substrate, resistive elements at the locations provided for the connection elements; depositing an electric insulator layer at least on the resistive elements; and forming the connection elements, each comprising a metal well having an opening capable of receiving the corresponding metal bump of the first microelectronic component and at least partially filled with a fusible element, particularly indium or an alloy of tin and gold, or with a conductive ink, particularly based on silver or copper. Further, the attachment of the balls to the connection elements comprises applying an electric current through the resistive elements to heat the bumps.

Abstract: An integrated circuit system comprises an interposer, a first integrated circuit, and at least one voltage regulator module. The first integrated circuit comprises first bond pads, and is electrically connected to the interposer at a first position of the interposer via the first bond pads. The first integrated circuit also comprises second bond pads. The first integrated circuit further comprises at least two circuit blocks. The at least two circuit blocks are configured to operate at different operating voltages. The at least one voltage regulator module is electrically connected to the first integrated circuit via the second bond pads, and the at least one voltage regulator module is configured to convert a received power supply voltage to the respective operating voltage of one of the at least two circuit blocks and supply the respective operating voltage via the second bond pads.

Abstract: A chip module comprises a carrier, having a first main surface and a second main surface opposite to the first main surface. A first recess structure is arranged in the carrier in the first main surface, and a chip is arranged in the first recess structure of the carrier. A patterned metallization layer is deposited on the second main surface of the carrier, the metallization layer having a first metallization structure and a second metallization structure, the first metallization structure being electrically isolated from the second metallization structure. The chip is electrically connected to the first metallization structure and the second metallization structure. The chip module comprises in particular an RFID chip and is suited to be connected to a textile substrate by way of laser reflow soldering.

Abstract: A method for designing a power distribution network of a circuit system includes the following steps: determining positions of a plurality of power source nodes; estimating a current distribution condition of the circuit system; and creating a first part of the power distribution network according to at least the positions of the power source nodes.

Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.

Abstract: Packaging methods and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes forming first contact pads on a carrier, forming a wiring structure over the first contact pads, and forming second contact pads over the wiring structure. A first packaged semiconductor device is coupled to a first set of the second contact pads, and a second packaged semiconductor device is coupled to a second set of the second contact pads. The carrier is removed. The second packaged semiconductor device comprises a different package type than the first packaged semiconductor device.

Abstract: There is provided a semiconductor device. The semiconductor device includes: a first board; a second board joined to the first board; a connection terminal provided between the first board and the second board and electrically connecting the first board and the second board; and an electronic component on at least one of the first board and the second board. The connection terminal serves as an antenna.

Abstract: In one embodiment, a device package is provided. The device package can include a substrate having first and second opposing surfaces, an opening being formed through the first and second surfaces of the substrate; a stiffener coupled to the first surface of the substrate, the stiffener having an extending portion that extends into the opening of the substrate; and an integrated circuit (IC) die coupled to the extending portion of the stiffener, the IC die being electrically coupled to the substrate.

Abstract: A semiconductor device connected by an anisotropic conductive film, the anisotropic conductive film including a binder resin; a first radical polymerization material having one or two (meth)acrylate reactive groups in a structure thereof and a second radical polymerization material having at least three (meth)acrylate reactive groups in a structure thereof; and conductive particles, the anisotropic conductive film having a moisture permeability of 170 g/m2/24 hr or less and a moisture absorbency of 2% or less.

Abstract: The present disclosure relates to a method and apparatus for improving back-end-of-the-line (BEOL) reliability. In some embodiments, the method forms an extreme low-k (ELK) dielectric layer having one or more metal layer structures over a semiconductor substrate. A first capping layer is formed over the ELK dielectric layer at a position between the one or more metal layer structures. A second capping layer is then deposited over the one or more metal layer structures at a position that is separated from the ELK dielectric layer by the first capping layer. The first capping layer has a high selectivity that limits interaction between the second capping layer and the ELK dielectric layer, reducing diffusion of the atoms from the second capping layer to the ELK dielectric layer and improving dielectric breakdown of the ELK dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes forming a barrier metal film on a surface of at least one of a first electrode of a wiring board and a second electrode of a semiconductor element, providing a connection terminal between the first and second electrodes, the connection terminal being made of solder containing tin, bismuth and zinc, and bonding the connection terminal to the barrier metal film by heating the connection terminal and maintaining the temperature of the connection terminal at a constant temperature not lower than a melting point of the solder for a certain period of time.

Abstract: An interconnection structure includes an underlying layer including a lower interconnection, and an interlayered dielectric layer including a contact hole and a trench therein. The contact hole exposes a portion of the lower interconnection, and the trench extends along a first direction to be connected to the contact hole. A contact plug extends through the contact hole in the interlayered dielectric layer, and an upper interconnection line extends in the trench of the interlayered dielectric layer and connects to the contact plug. The contact plug includes lower and upper sidewalls inclined at first and second angles, respectively, relative to the underlying layer, and the second angle is less than the first angle. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device includes a recess defined in a dielectric layer, the recess having an upper sidewall portion extending to an upper corner of the recess and a lower sidewall portion below the upper sidewall portion. An interconnect structure is positioned in the recess. The interconnect structure includes a continuous liner layer having upper and lower layer portions positioned laterally adjacent to the upper and lower sidewall portions, respectively. The upper layer portion includes an alloy of a first transition metal and a second transition metal and the lower layer portion includes the second transition metal but not the first transition metal. The interconnect structure also includes a fill material substantially filling the recess, wherein the second transition metal has a higher wettability for the fill material than the alloy.

Abstract: A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.

Abstract: Manufacturing method and circuit module, which comprises an insulator layer and, inside the insulator layer, at least one component, which comprises contact areas, the material of which contains a first metal. On the surface of the insulator layer are conductors, which comprise at least a first layer and a second layer, in such a way that at least the second layer contains a second metal. The circuit module comprises contact elements between the contact areas and the conductors for forming electrical contacts. The contact elements, for their part, comprise, on the surface of the material of the contact area, an intermediate layer, which contains a third metal, in such a way that the first, second, and third metals are different metals and the contact surface area (ACONT 1), between the intermediate layer and the contact area is less that the surface area (APAD) of the contact area.

Abstract: To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 ?m to 10 ?m from the edge of the concave to the bottom of the concave.

Abstract: According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.

Abstract: A semiconductor device includes a functional block unit, external terminals and, and an external resin sealing body. The functional block unit includes an internal resin sealing body having an edge and an opposite edge. The edge side of the internal resin sealing body covers a first end of an internal terminal, but does not cover a second end of the internal terminal. The edge side of the internal resin sealing body covers a first end of an internal terminal, but does not cover a second end of the internal terminal. The external resin sealing body covers the root portion and a portion of the middle portion of the external terminal, but does not cover the terminal portion of the external terminal. The functional block unit and the external terminals and are integrally connected together and sealed by the external resin sealing body.

Abstract: A droplet discharge head includes: a vibrating plate on which first and second terminals are formed; a reservoir forming substrate bonded to the vibrating plate and including a first inclined surface as a side surface on which a first wiring electrically connected to the first terminal is formed and that is inclined to a plate surface; and a wiring substrate bonded to the vibrating plate and including a second inclined surface as a side surface on which a second wiring electrically connected to the second terminal is formed and that is inclined to a plate surface along the first inclined surface.

Abstract: A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction

Abstract: A semiconductor device includes a semiconductor chip, the semiconductor chip including a substrate, a multilayer interconnect layer formed over the substrate, an outer peripheral cell column disposed along an edge of the substrate in a plan view, the outer peripheral cell column having at least one first I/O cell, and an inner peripheral cell column formed at an inner peripheral side of the outer peripheral cell column, the inner peripheral cell column having at least one second I/O cell.

Abstract: An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit block in the integrated circuit with a selected power supply signal.

Abstract: Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.

Abstract: Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads.

Abstract: A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.

Abstract: Various embodiments of mechanisms for forming through package vias (TPVs) with openings surrounding end-portions of the TPVs and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. The openings are formed by removing materials, such as by laser drill, surrounding the end-portions of the TPVs. The openings surrounding the end-portions of the TPVs of the die package enable solders of the bonding structures formed between another die package to remain in the openings without sliding and consequently increases yield and reliability of the bonding structures. Polymers may also be added to fill the openings surrounding the TPVs or even the space between the die packages to reduce cracking of the bonding structures under stress.

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract: BEOL memory cells are described that include one or more sidewall protection layers on the memory device (including, for example, an MTJ element) deposited prior to interconnect via etching to prevent the formation of electrical shorts between layers. One embodiment uses a single layer sidewall protection sleeve that is deposited after the memory device has been patterned. The layer material is vertically etched down to expose the upper surface of the top electrode while leaving a residual layer of protective material surrounding the rest of the memory device. The material for the protection layer is selected to resist the etchant used to remove the first dielectric material from the via in the subsequent interconnect process. A second embodiment uses dual-layer sidewall protection in which the first layer covers the memory element is preferably an oxygen-free dielectric and the second layer protects the first layer during via etching.

Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.

Abstract: The invention concerns a method comprising: forming a plurality of parallel lines (502, 504, 506) of a sacrificial material over a layer of conductive material (510) of an integrated circuit, said parallel lines being separated by trenches, at least one of said lines being interrupted along its length by an opening (516) dividing it into first and second line portions (504A, 504B) separated by a space (S); forming spacers (522, 524, 526, 528, 530) in said trenches on lateral sides of said line portions and filling at least a bottom part of said opening between the line portions; removing the sacrificial material by etching; and forming interconnection lines (302, 304A, 304B, 306A, 306B, 308, 310) of said conductive material based on a pattern defined by said spacers.

Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. The bottom package includes a die coupled to an interposer layer with an adhesive layer. One or more terminals are coupled to the interposer layer on the periphery of the die. The terminals and the die are at least partially encapsulated in an encapsulant. The terminals and the die are coupled to a redistribution layer (RDL). Terminals on the bottom of the RDL are used to couple the PoP package to a motherboard or a printed circuit board (PCB). One or more additional terminals couple the interposer layer to the top package. The additional terminals may be located anywhere along the surface of the interposer layer.

Abstract: A top package used in a PoP (package-on-package) package includes two memory die stacked with a redistribution layer (RDL) between the die. The first memory die is encapsulated in an encapsulant and coupled to a top surface of the RDL. A second memory die is coupled to a bottom surface of the RDL. The second memory die is coupled to the RDL with either a capillary underfill material or a non-conductive paste. The RDL includes routing between each of the memory die and one or more terminals coupled to the RDL on a periphery of the die.

Abstract: A semiconductor package offers improved product reliability by supplying a power voltage and a ground voltage to a semiconductor chip in a secured manner using a redistribution layer (RDL) structure. The semiconductor package includes a first semiconductor chip disposed on a substrate, a second semiconductor chip disposed on the first semiconductor chip, a plurality of redistribution lines disposed on the first semiconductor chip and electrically connecting the first semiconductor chip to the second semiconductor chip, and a redistribution wire disposed on the first semiconductor chip and electrically connecting one of the redistribution lines to another.

Abstract: A built-in electronic component substrate includes a first substrate, an electronic component including side surfaces and mounted on the first substrate, a first resin provided on the first substrate and covering the side surfaces of the electronic component, a second substrate provided above the electronic component and the first resin and layered on the first substrate, a substrate connection member provided between the first and the second substrates and electrically connecting the first and the second substrates, a second resin filling in between the electronic component and the second substrate and in between the first resin and the second substrate, and a third resin filling in between the first and the second substrates and encapsulating the substrate connection member, the electronic component, the first resin, and the second resin.

Abstract: Sub-micron precision alignment between two microelectronic components can be achieved by applying energy to incite an exothermic reaction in alternating thin film reactive layers between the two microelectronic components. Such a reaction rapidly distributes localized heat to melt a solder layer and form a joint without significant shifting of components.

Abstract: In some embodiments, a semiconductor device package assembly may include a substrate. The substrate may include a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the substrate. The second surface may include a die electrically coupled to the second surface. In some embodiments, the semiconductor device package may include an electrically insulating material covering at least a portion of the second surface and the die. The electrically insulating material may include a dielectric polymer. The dielectric polymer may function to inhibit deformation of the package during use. The dielectric polymer may include a coefficient of thermal expansion of between about 5 to about 15 ppm/° C. The dielectric polymer may include a modulus of between about 15 to about 25 Gpa.

Abstract: An encapsulation structure for an optoelectronic component may include: a barrier thin-film layer for protecting an optoelectronic component against chemical impurities; a cover layer applied above the barrier thin-film layer and serving for protecting the barrier thin-film layer against mechanical damage; and an intermediate layer applied on the barrier thin-film layer between barrier thin-film layer and cover layer and including a curable material designed such that when the non-cured intermediate layer is applied to the barrier thin-film layer, particle impurities at the surface of the barrier thin-film layer are enclosed by the intermediate layer and the applied intermediate layer has a substantially planar surface, and that after the intermediate layer has been cured, mechanical loads on the barrier thin-film layer as a result of particle impurities during the application of the cover layer are reduced by the intermediate layer.

Abstract: When opaque films are deposited on semi-conductor wafers, underlying alignment marks may be concealed. The re-exposure of such alignment marks is one source of resulting surface topography. In accordance with one implementation, alignment marks embedded in a wafer may be exposed by removing material from one or more layers and by replacing such material with a transparent material. In accordance with another implementation, the amount of material removed in an alignment mark recovery process may be mitigated by selectively ashing or etching above a stop layer.

Abstract: A fan assembly includes a nozzle having a first casing section, a second casing section, an air inlet, an air outlet, and an interior passage for conveying air from the air inlet to the air outlet. The nozzle defines a bore through which air from outside the fan assembly is drawn by air emitted from the nozzle. The nozzle is detachably mounted on a body including a motor and impeller unit for generating an air flow through the interior passage, and a humidifier for humidifying the air flow before it enters the interior passage. The first casing section defines, at least in part, the interior passage, and is detachable from the second casing section to allow the interior passage to be accessed by a user for cleaning.

Abstract: Humidifying apparatus includes a chamber, and a water tank for supplying water to the chamber. A baffle located within the chamber divides the chamber into an inlet section and an outlet section, and guides water received from the water tank along the inlet section to the outlet section. An air flow is conveyed over water stored in the outlet section of the chamber and is emitted from the apparatus. Water within both the inlet section and the outlet section of the chamber is irradiated with ultraviolet radiation. The water within the outlet section is atomized by a transducer to humidify the air flow.

Abstract: An illuminated surgical instrument is disclosed. One embodiment of the illuminated surgical instrument comprises a cannula and an injection-molded light-sleeve adjacent to and encircling at least a portion of the cannula. The surgical instrument can be a vitrectomy probe having a cutting port disposed at a distal end of the cannula. The light-sleeve can terminate near a distal end of the cannula, for example, near the cutting port of the vitrectomy probe. The light-sleeve is optically coupled to a light source. The light-sleeve can be injection-molded during manufacture using the cannula as an insert for the injection molding. The light-sleeve can be oriented for providing illumination in a direction along a longitudinal axis of the instrument.

Abstract: In one aspect, pharmaceutical compositions comprising dispersions of an acid-sensitive drug and a neutral dispersion polymer are disclosed. The acid-sensitive drug has improved chemical stability relative to dispersions of the drug and acidic polymers. In another aspect, pharmaceutical compositions of low-solubility drugs and amphiphilic, hydroxy-functional vinyl copolymers are disclosed.

Abstract: A polymer or polymer composite membrane having through-thickness micropores and a method of preparing the same are provided. More particularly, a polymer or polymer composite membrane having a pore structure such that micropores are aligned in a mesh structure in the thickness direction of the polymer or polymer composite membrane due to unidirectional freezing in the thickness direction of a solvent. The membrane has through-thickness micropores, and thus has improved permeability in the thickness direction and superior uniformity in size of the micropores and wall thickness between the micropores. For these reasons, the membrane can be used for a porous membrane substrate, microfiltration membrane, etc.

Abstract: Apparatus for performing an injection molding cycle, comprising: a manifold routing injection fluid to two or more gates, an actuator associated with each gate, each gate having a downstream sensor that senses a selected condition of the injection fluid material, a controller, the downstream sensors establishing a standard elapsed time, the controller including instructions that compares the standard elapsed time with a calculated amount of elapsed time associated with each of the gates and that adjust the velocity or position of each of the actuators.

Abstract: In a process for producing regenerated cellulose fibers, in which particles of a flame-retardant solid are incorporated into the fiber, the particles are placed into a mold, the dimension of which in a major axis of the particle is greater than in the two orthogonal minor axes of the particle, and the major axes of the particles in the fiber are aligned in a preferential direction parallel to the spinning direction thereof

Abstract: A mold release agent having an extended life and methods for making and using the same are provided. The extended life mold release agent may include a first material configured to be placed in direct physical contact with a surface of a mold cavity to seal the surface. The extended life mold release agent may also include a second material configured to coat the first material to protect the first material during a foam production process performed within the mold cavity. The second material includes a siloxane oil.

Abstract: The present invention relates to a porous manganese oxide-based lithium absorbent and a method for preparing the same. The method includes the steps of preparing a mixture by mixing a reactant for the synthesis of a lithium-manganese oxide precursor powder with an inorganic binder, molding the mixture, preparing a porous lithium-manganese oxide precursor molded body by heat-treating the molded mixture, and acid-treating the porous lithium-manganese oxide precursor molded body such that lithium ions of the porous lithium-manganese oxide precursor are exchanged with hydrogen ions, wherein pores are formed in the lithium-manganese oxide precursor molded body by gas generated in the heat treatment. The porous manganese oxide-based lithium adsorbent according to the present invention is easy to handle and has many more adsorption reaction sites compared to existing molded adsorbents, thus providing high lithium adsorption efficiency.

Abstract: A method and structure for flattening or straightening a curled flexible printed circuit, such as a flexible printed circuit that has been curled during a contact embossing process. The structure can include a cylindrical opening and a support shaft suspended within the cylindrical opening that prevents buckling of the flexible printed circuit during straightening. To flatten the curled flexible printed circuit, the curled end of the flexible printed circuit can be inserted into the cylindrical opening until the curled end is wrapped partially or completely around the support shaft.

Abstract: A coil for a transformer includes first and second coil segments with each coil segment being defined by successive layers of wound conductor sheeting. The coil segments are electrically connected together and are adjacent, defining a space therebetween. A plurality of cooling duct pairs are disposed between certain of the layers in each of the first and second coil segments such that, for each cooling duct pair, an end of a cooling duct disposed in the first coil segment is adjacent to an end of a cooling duct disposed in the second coil segment, with the ends being disposed in the space. A connector connects the adjacent ends of each pair of cooling ducts.