Abstract: A STT-MRAM comprises apparatus, a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a bias voltage controlled perpendicular anisotropy of a recording layer through an interlayer interaction to achieve a lower spin-transfer switching current. The anisotropy modification layer is under an electric field along a perpendicular direction with a proper voltage between a digital line and a bit line from a control circuitry, accordingly, the energy switch barrier is reduced in the spin-transfer recording while maintaining a high thermal stability and a good retention.

Abstract: A ferroelectric memory cell (1) and a memory device (100) comprising one or more such cells (1). The ferroelectric memory cell comprises a stack (4) of layers arranged on a flexible substrate (3). Said stack comprises an electrically active part (4a) and a protective layer (11) for protecting the electrically active part against scratches and abrasion. Said electrically active part comprises a bottom electrode layer (5) and a top electrode layer (9) and at least one ferroelectric memory material layer (7) between said electrodes. The stack further comprises a buffer layer (13) arranged between the top electrode layer (9) and the protective layer (11). The buffer layer (13) is adapted for at least partially absorbing a lateral dimensional change (?L) occurring in the protective layer (11) and thus preventing said dimensional change (?L) from being transferred to the electrically active part (4a), thereby reducing the risk of short circuit to occur between the electrodes.

Abstract: There is provided an image sensor module, including: an image sensor having a small thickness of 175 ?m or less and having a first coefficient of thermal expansion; a substrate having the image sensor mounted thereon and having a second coefficient of thermal expansion higher than the first coefficient of thermal expansion; and an adhesive layer disposed between the image sensor and the substrate and including an adhesive having a third coefficient of thermal expansion of 130 ppm/° C. or more at a glass transition temperature Tg or more.

Abstract: Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon. Other embodiments are disclosed and claimed.

Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

Abstract: A semiconductor device includes: a photoelectric conversion section made of semiconductor; a color filter made of an inorganic material to which a metal ion is added; and a getter film formed between the photoelectric conversion section and the color filter and configured to trap the metal ion.

Abstract: A variable optical filter is disclosed including a bandpass filter and a blocking filter. The bandpass filter includes a stack of alternating first and second layers, and the blocking filter includes a stack of alternating third and fourth layers. The first, second and fourth materials each comprise different materials, so that a refractive index of the first material is smaller than a refractive index of the second material, which is smaller than a refractive index of the fourth material; while an absorption coefficient of the second material is smaller than an absorption coefficient of the fourth material. The materials can be selected to ensure high index contrast in the blocking filter and low optical losses in the bandpass filter. The first to fourth layers can be deposited directly on a photodetector array.

Abstract: The present invention relates to a solid-state imaging device having good focusing properties, a method for manufacturing such a solid-state imaging device, and an electronic apparatus. The solid-state imaging device has a semiconductor substrate 11 and a photoelectric conversion part formed in the semiconductor substrate 11. In the solid-state imaging device, a laminate including an organic material layer and an inorganic material layer is formed on the semiconductor substrate with at least one stress relaxation layer 22 interposed between the organic and inorganic material layers. This technology is applicable to, for example, solid-state imaging devices having pixels and microlenses placed thereon.

Abstract: In a pixel unit of a solid-state imaging device, a semiconductor substrate is provided with a plurality of photodiodes, a first insulating film includes a recess in a portion above each of the photodiodes, a second insulating film embeds the recess, a plurality of color filters is formed on the second insulating film, the color filters each corresponding to one of the photodiodes, a partition is provided between adjacent ones of the color filters, the partition being a part of a third insulating film, and in an area outside of the pixel unit, (i) a conductive film at least partially covered by the third insulating film is formed on the second insulating film, and (ii) the third insulating film formed on the conductive film and on the second insulating film near the conductive film has a film thickness smaller than a film thickness of the partition.

Abstract: A curable liquid formulation comprising: (i) one or more near-infrared absorbing polymethine dyes; (ii) one or more crosslinkable polymers; and (iii) one or more casting solvents. The invention is also directed to solid near-infrared absorbing films composed of crosslinked forms of the curable liquid formulation. The invention is also directed to a microelectronic substrate containing a coating of the solid near-infrared absorbing film as well as a method for patterning a photoresist layer coated on a microelectronic substrate in the case where the near-infrared absorbing film is between the microelectronic substrate and a photoresist film.

Abstract: A silicon photomultiplier detector cell may include a photodiode region and a readout circuit region formed on a same substrate. The photodiode region may include a first semiconductor layer exposed on a surface of the silicon photomultiplier detector cell and doped with first type impurities; a second semiconductor layer doped with second type impurities; and/or a first epitaxial layer between the first semiconductor layer and the second semiconductor layer. The first epitaxial layer may contact the first semiconductor layer and the second semiconductor layer. The first epitaxial layer may be doped with the first type impurities at a concentration lower than a concentration of the first type impurities of the first semiconductor layer.

Abstract: A sensing device has a semiconductor substrate with an opening and a membrane spanning the opening. A heater is arranged on the membrane. To reduce the thermal conductivity of the membrane, a recess is etched into the membrane from below.

Abstract: A power diode is disclosed wherein it is possible to lower on-voltage by expanding a conducting region at an on time. By applying negative voltage to a plate electrode when turning on a power diode, an inversion layer is formed in a front surface layer of an n drift region sandwiched between a p guard ring region and a p anode region, and the p guard ring region and p anode region are connected by the inversion layer, thereby causing one portion or all of the p guard ring region to function as an active region together with the anode region, and expanding an energization region, thus lowering on-voltage.

Abstract: A SOI RF device and a method for forming the same are provided. A trench exposed a part of the high resistivity silicon base is formed in the SOI substrate; a non-doped polysilicon layer is disposed on the high resistivity silicon base which is exposed by the trench; and at least a part of the non-doped polysilicon layer is covered by an above metal layer. With effects of the metal layer which is applied with a RF signal or a superposed signal, and fixed charges in the BOX layer, an inversion layer may be formed at a surface of the non-doped polysilicon layer. Since carriers may easily recombine at the grain boundaries of polysilicon, eddy current generated on a surface of the high resistivity silicon base is reduced, loss of the RF signal is reduced, and linearity of the RF signal device is improved.

Abstract: A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

Abstract: An electronic fuse structure having an Mx level including an Mx dielectric, a fuse line, an Mx cap dielectric above at least a portion of the Mx dielectric, and a modified portion of the Mx cap dielectric directly above at least a portion of the fuse line, where the modified portion of the Mx cap dielectric is chemically different from the remainder of the Mx cap dielectric, an Mx+1 level including an Mx+1 dielectric, a first Mx+1 metal, an Mx+1 cap dielectric above of the Mx+1 dielectric and the first Mx+1 metal, where the Mx+1 level is above the Mx level, and a first via electrically connecting the fuse line to the first Mx+1 metal.

Abstract: An electronic fuse structure including etching a dual damascene feature in a dielectric layer, the dual damascene feature including a first via opening, a second via opening, and a trench opening, forming a seed layer within the dual damascene feature, the seed layer including a conductive material, and heating the dielectric layer and the seed layer causing the seed layer to reflow and fill the first via opening, the second via opening, and partially filling the trench opening to form a fuse line, a first via, and a second via. The structure further including forming an insulating layer on top of the fuse line, and forming a fill material on top of the insulating layer and substantially filling the trench opening.

Abstract: Provided is a semiconductor device which prevents deterioration of the long-term reliability caused by entry of moisture owing to a fuse opening in a multilayer wiring process. In order to prevent entry of moisture through the fuse opening, interlayer insulating films which are oxide films are etched so as to leave a part of a plasma TEOS oxide film layer. After that, a passivation nitride film is deposited and patterned, and then, the passivation nitride film is partly removed, thereby obtaining a structure in which side walls and a side bottom surface of the interlayer insulating films in the fuse opening are covered with the passivation nitride film. This enables inhibition of entry of moisture through an interface among the stacked interlayer insulating films and through an SOG layer, and deterioration of the IC characteristics owing to moisture can be prevented.

Abstract: One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage VPP greater than or equal to a dielectric breakdown voltage VBD of the antifuse is applied to the first conductor plate and the second conductor plate. The first conductor plate has a total edge length that is greater than two times the sum of its maximum width and maximum length dimensions. The first conductor plate's top surface area may also be less than the product of its maximum length and maximum width.

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate is disclosed. A first conductive line and a second conductive line are disposed in the first insulating layer, and each of the first and second conductive lines has a first end and a second end, wherein the second ends of the first and second conductive lines are coupled to each other. A first winding portion and a second winding portion are disposed in the second insulating layer, and each of the first and second winding portions includes a third conductive line and a fourth conductive line arranged from the inside to the outside. Each of the third and fourth conductive lines has a first end and a second end, wherein the first and second conductive lines overlap at least a portion of the third conductive lines.

Abstract: An inductor device includes an insulation layer, an inductor, fixed electrodes, and a movable electrode. The inductor is formed on the insulation layer. The fixed electrodes are provided in positions which do not overlap with the inductor in a planar view. The movable electrode overlaps with the inductor and the fixed electrodes in the planar view, and is separated from the inductor and the fixed electrodes. Further, the movable electrode includes first openings.

Abstract: A semiconductor device includes a semiconductor substrate, and a multilayer wiring layer provided over the semiconductor substrate. The multilayer wiring layer includes an inductor wiring formed in one wiring layer, a plurality of first dummy metals formed in the same layer as the inductor and provided inside the inductor, a plurality of second dummy metals formed in a same layer as the inductor and provided outside the inductor, a plurality of third dummy metals formed in a layer lower than the one wiring layer including the inductor, and provided inside the inductor in a plan view, a plurality of fourth dummy metals formed in a same layer as the plurality of third dummy metals and provided outside the inductor in the plan view, and a plurality of fifth dummy metals formed in the same layer as the plurality of third dummy metals and provided to overlap with the inductor.

Abstract: A semiconductor device including: first and second semiconductor chips mounted on a base substrate; a third semiconductor chip, which is mounted on the base substrate, and outputs control signals controlling operations of the first and second semiconductor chips; a first transmission transformer, which is mounted on the base substrate, and has a reception-side terminal connected to the third semiconductor chip and a transmission-side terminal connected to the first semiconductor chip; and a second transmission transformer, which is mounted on the base substrate, and has a reception-side terminal connected to the third semiconductor chip and a transmission-side terminal connected to the second semiconductor chip, wherein the control signals are transmitted from the third semiconductor chip to the first semiconductor chip and the second semiconductor chip individually through the first transmission transformer and the second transmission transformer.

Abstract: A semiconductor ceramic having a compounding molar ratio m between a Sr site and a Ti site that satisfies 1.000?m?1.020, has a donor element present as a solid solution in crystal grains, has an acceptor element present in a grain boundary layer in the range of 0.5 mol or less with respect to 100 mol of the Ti element, contains a Zr element in the range of 0.15 mol or more and 3.0 mol or less with respect to 100 mol of the Ti element, and has the crystal grains of 1.5 ?m or less in average grain size.

Abstract: Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The titanium nitride material may be oxidized to a titanium dioxide material. A second conductive material may be formed over a surface of the titanium dioxide material. A semiconductor device may include at least one capacitor, wherein a major longitudinal portion of the at least one capacitor is not surrounded by a solid material. The capacitor may include a first electrode; a ruthenium oxide material laterally adjacent the first electrode; a rutile titanium dioxide material laterally adjacent the ruthenium oxide material; and a second electrode laterally adjacent the rutile titanium dioxide material.

Abstract: Provided is a method of manufacturing a capacitor of a display apparatus, the display apparatus being formed on a substrate and including a thin film transistor, which includes an active layer, a gate electrode, and source and drain electrodes, a display device connected to the thin film transistor, and the capacitor, the method including: forming an electrode layer on the substrate; forming a passivation layer on the electrode layer; patterning the passivation layer to form a first pattern including first branch patterns parallel to each other, and a second pattern including second branch patterns parallel to each other and interposed between the first branch patterns; and forming first and second electrodes by etching the electrode layer using the first and second patterns as masks.

Abstract: A method and structures are provided for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications. A deep oxygen implant is provided in a selected region of substrate. A first deep trench and second deep trench are formed above the deep oxygen implant. The first deep trench is a generally large rectangular box deep trench of minimum width and the second deep trench is a second small area deep trench centered within the first rectangular box deep trench. Ion implantation at relatively high ion pressure and annealing is utilized to form highly doped N+ regions or P+ regions both inside and outside the outside the first deep trench and around the outside the second deep trench region. These regions provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions.

Abstract: According to an embodiment, a method for manufacturing a semiconductor device is provided. The method includes providing a mask layer which is used as an implantation mask when forming a doping region and which is used as an etching mask when forming an opening and a contact element formed in the opening. The contact element is in contact with the doping region.

Abstract: A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.

Abstract: A method includes applying a reinforcing wafer to a semiconductor wafer, thereby forming a composite wafer. Further the method includes dividing the composite wafer, thereby generating a plurality of composite chips each including a semiconductor chip and a reinforcing chip.

Abstract: According to example embodiments, a method of forming micropatterns includes forming dummy patterns having first widths on a dummy region of a substrate, and forming cell patterns having second widths on an active line region of the substrate. The active line region may be adjacent to the dummy region and the second widths may be less than the first widths. The method may further include forming damascene metallization by forming a seed layer on the active line region and the dummy region, forming a conductive material layer on a whole surface of the substrate, and planarizing the conductive material layer to form metal lines.

Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Abstract: A method comprises dispensing a first solvent on a semiconductor substrate; dispensing a first layer of a high-viscosity polymer on the first solvent; dispensing a second solvent on the first layer of high-viscosity polymer; and spinning the semiconductor substrate after dispensing the second solvent, so as to spread the high-viscosity polymer to a periphery of the semiconductor substrate.

Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.

Abstract: Apparatus and methods for an electronic package incorporating shielding against emissions of electromagnetic interference (EMI). According to an integrated circuit structure, a substrate is on a printed circuit board. An integrated circuit chip is on the substrate. The integrated circuit chip is electrically connected to the substrate. An electromagnetic interference (EMI) shielding unit is on the integrated circuit chip and the substrate. The EMI shielding unit comprises a lid covering the integrated circuit chip and portions of the substrate outside the integrated circuit chip. A fill material can be deposited within a cavity formed between the lid and the substrate. The fill material comprises an EMI absorbing material. A periphery of the lid comprises a side skirt, the side skirt circumscribing the integrated circuit chip and the substrate. EMI absorbing material is on the printed circuit board, and a portion of the side skirt is embedded in the EMI absorbing material.

Abstract: Provided is a method of manufacturing a semiconductor device which includes a semiconductor chip, an insulating board mounted with the semiconductor chip and having a wiring pattern, and a leadframe connected to the wiring pattern, the semiconductor chip, the wiring pattern and the leadframe being partially sealed with a sealing resin, wherein: an epoxy resin composition formed by adding 0.3 to 0.7 mass % of epoxysilane as a silane coupling agent to an epoxy resin is used as the sealing resin; and a copper member made of copper or a copper alloy and having an oxide film formed in the surface with a film thickness in a color indicated by an L* value in the range of 48 to 51, an a* value in the range of 40 to 49 and a b* value in the range of 24 to 40 is used as the leadframe and the wiring pattern.

Abstract: Various embodiments provide a chip arrangement. The chip arrangement may include a first chip including a first contact and a second contact; a second chip; a leadframe including a first leadframe portion and a second leadframe portion electrically insulated from the first leadframe portion; and a plurality of pins coupled to the leadframe. At least one first pin is coupled to the first leadframe portion and at least one second pin is coupled to the second leadframe portion. The first contact of the first chip is electrically coupled to the first leadframe portion and the second contact of the first chip is coupled to the second leadframe portion. A contact of the second chip is electrically coupled to the second leadframe portion.

Abstract: A semiconductor device (100) with a leadframe having first (310) and second (311) leads with central and peripheral ends, the central ends in a first horizontal plane (150). The first leads have peripheral ends (310b) in a second horizontal plane spaced (160) from the first plane and the second leads having peripheral ends in a third horizontal plane (170). A semiconductor chip (101) is connected to the central lead ends. A package (120) encapsulates the chip and the central ends of the first and second leads, leaving the peripheral ends of the first and second leads un-encapsulated, wherein the packaged device has lead ends as terminals on the second and third horizontal plane.

Abstract: A packaged electronic device includes a package substrate, an electronic component die mounted to the package substrate, and an encapsulant bonded to a portion of the package substrate at a catechol group adhesion promoted interface that includes benzene rings bonded with the package substrate and the encapsulant.

Abstract: An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

Abstract: A semiconductor package having a metal frame includes a frame-shaped conductive member which has an opening portion, mounted on a substrate, and a semiconductor element disposed within the opening. A ring-shaped wiring pattern is provided on a portion of the substrate outwards from the opening portion of the conductive member. The electrostatic coupling capacity of the ring-shaped wiring pattern and the conductive member is not less than the electrostatic coupling capacity of a semiconductor metal wiring layer and the conductive member. The ring-shaped wiring pattern and the ground wiring of the semiconductor metal wiring layer are electrically connected.

Abstract: A semiconductor package of an embodiment includes: a semiconductor chip having a signal input terminal and a signal output terminal; and a cap unit that is formed on the semiconductor chip. The cap unit includes a concave portion forming a hollow structure between the semiconductor chip and the cap unit, a first through electrode electrically connected to the signal input terminal, and a second through electrode electrically connected to the signal output terminal. Of the inner side surfaces of the concave portion, a first inner side surface and a second inner side surface facing each other are not parallel to each other.

Abstract: A semiconductor device includes an insulating substrate joined with a semiconductor chip, a case covering a surface of the insulating substrate where the semiconductor chip is joined, and a control terminal in which one end portion is electrically connected to the semiconductor chip, and another end portion passes through the case and is exposed to outside of the case. A portion of the control terminal exposed to the outside of the case includes a cut-out section where a part of the exposed portion is cut out, and a blocking section formed by bending a portion surrounded by the cut-out section and remaining on the control terminal. The blocking section contacts the case from the outside of the case and blocks a movement of the control terminal.

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad.

Abstract: The present invention discloses a chip package and a manufacturing method thereof. The chip package includes: a semiconductor chip having an upper surface and a lower surface opposite to each other; a metal heat conductive layer formed on the lower surface, for conducting or absorbing heat generated by the semiconductor chip; and a bond pad formed on the upper surface, for electrically connecting to a circuit in the semiconductor chip.

Abstract: A friction stir welding structure is comprised of a first and a second member integrated into one piece by friction stir welding, and in which a thin section is formed along the friction stir weld section on at least one of either of the first and the second member.

Abstract: An integrated structure includes a support supporting at least one chip and a heat dissipating housing, attached to the chip. The housing is thermally conductive and has a thermal expansion compatible with the chip. The housing may further including closed cavities filled with a phase change material.

Abstract: A semiconductor module includes a control board, and a shield plate arranged opposing the control board. A metal first heat dissipating portion is provided on a surface of the control board. A metal second heat dissipating portion is provided on a first surface of the shield plate, opposing the surface of the control board. A dielectric body is arranged between the first heat dissipating portion and the second heat dissipating portion.

Abstract: Provided is a conductive paste, an electrode for a semiconductor device manufactured by using the conductive paste, a semiconductor device and a method for manufacturing the semiconductor device. The conductive paste includes conductive powder made of a plurality of conductive particles and silver powder made of a plurality of silver particles. The conductive particles includes a base material made of ceramics and a conductive layer configured to cover at least a part of an outer surface of the base material. The ratio of the mass of the conductive layer relative to the total mass of the conductive particles is 10% or more by mass, and the ratio of the mass of the conductive powder relative to the total mass of the conductive powder and the silver powder is 25% or less by mass.

Abstract: Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.