Abstract: A semiconductor device includes: a first buffer layer formed on a substrate; a second buffer layer formed on a portion of the first buffer layer; a third buffer layer formed on the first buffer layer and the second buffer layer; a first semiconductor layer formed on the third buffer layer; a second semiconductor layer formed on the first semiconductor layer; and a gate electrode, a source electrode, and a drain electrode that are formed on the second semiconductor layer, wherein the second buffer layer is composed of a material with higher resistivity than the first semiconductor layer; and the second buffer layer is formed in a region immediately below and between the gate electrode and the drain electrode.

Abstract: A transistor and a method of manufacturing the same are disclosed. The transistor includes a first epitaxial layer, a channel layer, a gate structure and an impurity region. The first epitaxial layer on a substrate includes a silicon-germanium-tin (SixGe1-x-ySny) single crystal having a lattice constant greater than a lattice constant of a germanium (Ge) single crystal. The channel layer is disposed adjacent to the first epitaxial layer. The channel layer includes the germanium single crystal. The gate structure is disposed on the channel layer. The impurity region is disposed at an upper portion of the channel layer adjacent to the gate structure.

Abstract: Semiconductor trilayer structures that are doped and strained are provided. Also provided are mechanically flexible transistors, including radiofrequency transistors, incorporating the trilayer structures and methods for fabricating the trilayer structures and transistors. The trilayer structures comprise a first layer of single-crystalline semiconductor material, a second layer of single-crystalline semiconductor material and a third layer of single-crystalline semiconductor material. In the structures, the second layer is in contact with and sandwiched between the first and third layers and the first layer is selectively doped to provide one or more doped regions in the layer.

Abstract: A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At least one of the S/D features includes a first semiconductor material, a second semiconductor material over the first semiconductor material, and a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions.

Abstract: A III-V semiconductor device on a silicon substrate is constructed with a silicon (Si) substrate onto which gallium arsenide (GaAs) indium phosphide (InP) and aluminum indium arsenide (AlInAs) to form a structure of AlInAs over InP over GaAs over Si. The GaAs is applied in at least one layer over the Si, followed by at least one layer of InP and at least one layer of AlInAs. A portion of the structure is doped and a cap or passivation layer is applied.

Abstract: A method for manufacturing a semiconductor device includes forming a buffer layer made of a nitride semiconductor, forming a channel layer made of a nitride semiconductor over the buffer layer, forming a barrier layer made of a nitride semiconductor over the channel layer, forming a cap layer made of a nitride semiconductor over the barrier layer, forming a gate insulating film so as to in contact with the cap layer; and forming a gate electrode over the gate insulating film, wherein compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer by controlling compositions of the cap layer, the barrier layer, the channel layer, and the buffer layer.

Abstract: Disclosed is a semiconductor device including transistors B on an output side of a current mirror, arranged uniformly in a surrounding area of a transistor A on an input side of the current mirror. The transistors B are arranged at equal distances, adjacently to the transistor A, on both sides of the transistor A.

Abstract: In one implementation, a chemical detection device is described. The device includes a chemically-sensitive field effect transistor including a floating gate conductor coupled to a gate dielectric and having an upper surface, and a sensing material on the upper surface. The device also includes a fill material defining a reaction region extending above the sensing material, the reaction region overlying and substantially aligned with the floating gate conductor.

Abstract: A chemical sensor is described with at least one layer of metal oxide arranged between two electrodes with the length of the layer of metal oxide between the electrodes being less than 50 microns, wherein at least one interface layer is formed between the surface of at least one of the electrodes and the layer of metal oxide and wherein the interface layer lowers the contact resistance between the electrodes and the layer of metal oxide by facilitating transport of charge carriers across layer boundaries.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a gate structure separating source and drain (S/D) features. The semiconductor device further includes a first dielectric layer formed over the substrate, the first dielectric layer including a first interconnect structure in electrical contact with the S/D features. The semiconductor device further includes an intermediate layer formed over the first dielectric layer, the intermediate layer having a top surface that is substantially coplanar with a top surface of the first interconnect structure. The semiconductor device further includes a second dielectric layer formed over the intermediate layer, the second dielectric layer including a second interconnect structure in electrical contact with the first interconnect structure and a third interconnect structure in electrical contact with the gate structure.

Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.

Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.

Abstract: A multiple time programmable nonvolatile memory device having a single polysilicon memory cell includes a select transistor and a bitcell transistor. The bitcell transistor has asymmetrically configured source, drain, and channel regions including asymmetrically configured source-body and drain-body junctions. Compared with the drain-body junction, the impurity concentration gradient of the source-body junction is more gradual, which may significantly improve program disturb immunity. The bitcell transistor gate may be connected to an electrode of a coupling capacitor, but may be otherwise floating or Ohmically isolated. The floating gate of the bitcell is protected by a dielectric layer for potentially improved data retention.

Abstract: An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide is formed by depositing a first oxide over a channel region of the anti-fuse memory cell, removing the first oxide in a thin oxide area of the channel region, and then thermally growing a second oxide in the thin oxide area. The remaining first oxide defines a thick oxide area of the channel region. The second oxide growth occurs under the remaining first oxide, but at a rate less than thermal oxide growth in the thin oxide area. This results in a combined thickness of the first oxide and the second oxide in the thick oxide area being greater than second oxide in the thin oxide area.

Abstract: A memory device is provided having an improved gate coupling ratio, substantial suppression of p-type dopant segregation, and reduction in inter-poly dielectric current leakage. The memory device may be substantially free of any void spaces in a second conductive layer. Methods of manufacturing such a memory device are also provided.

Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines and in a groove in the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.

Abstract: A fabricating method for fabricating a non-volatile memory structure including the following steps is provided. A first conductive type doped layer is formed in a substrate. A plurality of stacked structures is formed on the substrate, and each of the stacked structures includes a charge storage structure. A first dielectric layer is formed on the substrate between the adjacent stacked structures. A second conductive type doped region is formed in the substrate between the adjacent charge storage structures. The second conductive type doped region has an overlap region with each of the charge storage structures. In addition, the second conductive type doped region divides the first conductive type doped layer into a plurality of first conductive type doped regions that are separated from each other. A conductive layer is formed on the first dielectric layer.

Abstract: An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A farther benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

Abstract: A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell for use in a CMOS IC, where the CEONOS NVM cell requires two or three additional masks, but is otherwise substantially formed using the same standard CMOS flow processes used to form NMOS transistors. The cell is similar to an NMOS cell but includes an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data. The cells utilize special source/drain engineering to include pocket implants and lightly-doped drain extensions, which facilitate program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share a drain diffusion and three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).

Abstract: Non-volatile memory (NVM) cells having carbon impurities are disclosed along with related manufacturing methods. The carbon impurities can be introduced using a variety of techniques, including through epitaxial growth of silicon-carbon (SiC) layers and/or carbon implants. Further, the carbon impurities can be introduced into one or more structures within NVM cells, including source regions, drain regions, gate regions, and/or charge storage layers. For discrete charge storage layers that utilize nanocrystal structures, carbon impurities can be introduced into the nanocrystal charge storage layers. The disclosed embodiments are useful for a variety of NVM cell types including split-gate NVM cells, floating gate NVM cells, discrete charge storage NVM cells, and/or other desired NVM cells. Advantageously, the carbon impurities introduce tensile stress into the cell structures, and this tensile stress helps maintain NVM system performance and data retention even as device geometries are reduced.

Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

Abstract: A thin film transistor based on carbon nanotubes includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The semiconductor layer is electrically connected with the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The work-functions of the source electrode and of the drain electrode are different from that of the semiconductor layer, enabling the creation of both p-type and n-type field-effect transistors.

Abstract: A semiconductor device includes a pillar-shaped semiconductor having an impurity concentration of 1017 cm?3 or less, a first insulator that surrounds the pillar-shaped semiconductor, a first metal that surrounds a portion of the first insulator at a first end of the pillar-shaped semiconductor, a second metal that surrounds a portion of the first insulator at the second end of the pillar-shaped semiconductor, a third metal that surrounds a portion of the first insulator in a region sandwiched between the first metal and the second metal, a second insulator formed between the first and third metals, a third insulator formed between the second and third metals, a fourth metal that connects the first metal and the one end, and a fifth metal that connects the second metal and the other end. The third metal has a work function of about 4.2 eV to about 5.0 eV.

Abstract: A semiconductor device includes a first conductivity-type drain layer, a first conductivity-type drift layer formed on the drain layer, a second conductivity-type base layer formed on the drift layer, a first conductivity-type source layer which is selectively formed on a surface of the base layer, a trench region formed through a surface of the source layer such that the trench region reaches the drift layer from the surface of the source layer, a gate electrode formed adjacent to the base layer and inside the trench region, and surrounded by a first insulation film, a field plate electrode formed in the trench region below the gate electrode and surrounded by a second insulation film having a higher dielectric constant than the first insulation film, a drain electrode which is electrically connected to the drain layer, and a source electrode electrically connected to the source layer.

Abstract: A first lower insulating film (LIL1) is formed on the bottom surface and a lower portion of the side surface of a first concave portion (gate trench) and is thicker than a gate insulating film (GIF). An upper end of LIL1 is connected to a lower end of the GIF. A second lower insulating film is formed on the bottom surface and a lower portion of the side surface of a second concave portion (termination trench). An upper insulating film (UIF) is formed at an upper portion of the side surface of the second concave portion and a lower end is connected to an upper end of LIL2. The depth of the second concave portion is ?90% and ?110% of the depth of the first concave portion. The thickness of LIL2 is ?95% and ?105% of the thickness of LIL1. The UIF is thicker than the GIF.

Abstract: A semiconductor device includes: a semiconductor substrate formed with an element region; a first conductive type first region formed in the element region and located on a surface side of the semiconductor substrate; a second conductive type second region located in a deeper position than the first region in the element region and contacting the first region; a first conductive type third region located in a deeper position than the second region in the element region, contacting the second region, and separated from the first region by the second region; and a gate disposed in a trench extending from the surface to reach the third region, and contacting a range of the second region via the insulation film.

Abstract: The n-channel double diffusion MOS transistor includes a p-type semiconductor substrate, a p-type epitaxial layer, and an n-type buried layer provided in a boundary between the p-type semiconductor substrate and the p-type epitaxial layer. In a p-type body layer provided in a surface portion of the p-type epitaxial layer, an n-type source layer is provided to define a double diffusion structure together with the p-type body layer. An n-type drift layer is provided in a surface portion of the p-type epitaxial layer in spaced relation from the p-type body layer. An n-type drain layer is provided in a surface portion of the p-type epitaxial layer in contact with the n-type drift layer. A p-type buried layer having a lower impurity concentration than the n-type buried layer is buried in the p-type epitaxial layer between the n-type drift layer and the n-type buried layer in contact with an upper surface of the n-type buried layer.

Abstract: A method of manufacturing a diode is provided. An N-type well region is formed in a first upper portion of an N-type epitaxial layer. A P-type drift region is formed in a second upper portion of the N-type epitaxial layer. An N-type doping region is formed in the N-type well region. A P-type doping region is formed in the P-type drift region. An isolation structure is formed in the P-type drift region. The isolation structure is disposed between the P-type doping region and the N-type well region. A first electrode is formed on a portion of the N-type epitaxial layer. The portion of the N-type epitaxial layer is disposed between the N-type well region and the P-type drift region. The first electrode overlaps a portion of the isolation structure. A connection structure is formed to electrically couple the N-type doping region and the first electrode.

Abstract: A method provides an intermediate semiconductor device structure and includes providing a water having first dummy gate plugs and second dummy gate plugs embedded in a first layer having a non planar wafer surface topography due at least to a presence of the fist dummy gate plugs; depositing at least one second layer over the first layer, the at least one second layer comprising a hard mask material; and removing at least a portion of the second layer to form a substantially planar wafer surface topography over the first dummy gate plugs and the second dummy gate plugs prior to gate conductor deposition.

Abstract: An intermediate wafer includes a substrate having a surface and a first dummy gate plug disposed upon a structure, e.g., a FIN, supported by the substrate surface; a second dummy gate plug disposed upon the substrate surface; and a first layer in which the first dummy gate plug and the second dummy gate plug are embedded. The first layer exhibits a non-planar surface topography characterized by a depression due at least to a presence of the first dummy gate plug. The structure further includes a second layer that fills the depression to the surface of the first layer, and a third layer that overlies the first layer and the second layer. The third layer is formed of a hard mask material and has a substantially planar surface topography over the first and second dummy gate plugs and over the depression that is filled with the material of the second layer.

Abstract: Embodiments of the invention provide an array substrate and a fabrication method thereof, and a liquid crystal display device. The array substrate comprises: a gate line, a data line, and a pixel unit formed by the gate line and the data line intersecting with each other. A first thin-film transistor and a pixel electrode are formed in the pixel unit, and the pixel electrode has slits. The pixel unit further comprises a second thin-film transistor, a first common electrode and a second common electrode, and the second thin-film transistor is configured to turn on and transmit a signal of the first common electrode to the second common electrode when a data line signal is at a high level.

Abstract: A double-diffused metal oxide semiconductor (DMOS) structure is configured as an open drain output driver having electrostatic discharge (ESD) protection and a reverse voltage blocking diode inherent in the structure and without requiring metal connections for the ESD and reverse voltage blocking diode protections.

Abstract: A semiconductor device includes an n-type drift layer formed on a main surface of a semiconductor substrate, a plurality of p-type well regions formed selectively in an upper layer portion of the drift layer, an n-type source region formed in a surface of the p-type well region, and a p-type contact region which is shallower than the source region formed in the surface of the p-type well region adjacent to the source region. Moreover, the semiconductor device includes an n-type additional region formed in contact with a bottom surface of the p-type well region in a position corresponding to below the contact region and deeper than the p-type well region.

Abstract: Methods for forming FIN-shaped field effect transistors (FINFETs) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (FIN) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the FIN, thereby defining a drain-side FIN region of the FIN between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the FIN in the drain-side FIN region.

Abstract: A method for fabricating a finFET device having an insulating layer that insulates the fin from a substrate is described. The insulating layer can prevent leakage current that would otherwise flow through bulk semiconductor material in the substrate. The structure may be fabricated starting with a bulk semiconductor substrate, without the need for a semiconductor-on-insulator substrate. Fin structures may be formed by epitaxial growth, which can improve the uniformity of fin heights in the devices.

Abstract: In one aspect, a method for silicidation includes the steps of: (a) providing a wafer having at least one first active area and at least one second active area defined therein; (b) masking the first active area with a first hardmask; (c) doping the second active area; (d) forming a silicide in the second active area, wherein the first hardmask serves to mask the first active area during both the doping step (c) and the forming step (d); (e) removing the first hardmask; (f) masking the second active area with a second hardmask; (g) doping the first active area; (h) forming a silicide in the first active area, wherein the second hardmask serves to mask the second active area during both the doping step (g) and the forming step (h); and (i) removing the second hardmask.

Abstract: Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and drain regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different.

Abstract: An integrated circuit includes a layer of a semiconductor device including a standard cell configuration having a fixed gate electrode pitch between gate electrode lines and a resistor formed of metal between the fixed gate electrode pitch of the standard cell configuration. In one embodiment, the integrated circuit can be charged device model (CDM) electrostatic discharge (ESD) protection circuit for a cross domain standard cell having the resistor formed of metal. A method of manufacturing integrated circuits includes forming a plurality of gate electrode lines separated by a gate electrode pitch to form a core standard cell device, applying at least a first layer of metal within the gate electrode pitch to form a portion of a resistor, and applying at least a second layer of metal to couple to the first layer of metal to form another portion of the resistor.

Abstract: A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes respective gate contacts and a conductive interconnect structure.

Abstract: A first implant is performed into a substrate to form a well in which a plurality of transistors will be formed. Each transistor of a first subset of the plurality of transistors to be formed has a width that satisfies a predetermined width constraint and each transistor of a second subset has a width that does not satisfy the constraint. A second implant is performed at locations in the well in which transistors of the first subset will be formed and not at locations in the well in which transistors of the second subset will be formed. The transistors are formed, wherein a channel region of each transistor of the first subset is formed in a portion of the substrate which received the second implant and a channel region of each transistor of the second subset is formed in a portion of the substrate which did not receive the second implant.

Abstract: A semiconductor device and a method of forming the semiconductor device includes: forming gate electrodes on a semiconductor substrate and forming spacers on both side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes. Each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes.

Abstract: Methods for fabricating crack resistant Microelectromechanical (MEMS) devices are provided, as are MEMS devices produced pursuant to such methods. In one embodiment, the method includes forming a sacrificial body over a substrate, producing a multi-layer membrane structure on the substrate, and removing at least a portion of the sacrificial body to form an inner cavity within the multi-layer membrane structure. The multi-layer membrane structure is produced by first forming a base membrane layer over and around the sacrificial body such that the base membrane layer has a non-planar upper surface. A predetermined thickness of the base membrane layer is then removed to impart the base membrane layer with a planar upper surface. A cap membrane layer is formed over the planar upper surface of the base membrane layer. The cap membrane layer is composed of a material having a substantially parallel grain orientation.

Abstract: An integrated MEMS sensor package is disclosed. The package comprises a sensor chip with a top surface and a bottom surface. The top surface comprises an opening. The bottom surface is attached to a substrate with electrical inter-connects. A lid is coupled to the top surface with an adhesive material. The lid may have an opening to expose the sensor chip to ambient environment.

Abstract: MEMS devices with a rigid backplate and a method of making a MEMS device with a rigid backplate are disclosed. In one embodiment, a device includes a substrate and a backplate supported by the substrate. The backplate includes elongated protrusions.

Abstract: An in-process magnetic layer having an in-process area dimension is formed with a chemically damaged region at a periphery. At least a portion of the chemically damaged region is transformed to a chemically modified peripheral portion that is non-ferromagnetic. Optionally, the transforming is by oxidation, nitridation or fluorination, or combinations of the same.

Abstract: The blocking temperature of the AFM layer in a TMR sensor has been raised by inserting a magnetic seed layer between the AFM layer and the bottom shield. This gives the device improved thermal stability, including improved SNR and BER.

Abstract: A vertical Hall Effect element includes a low voltage P-well region disposed at a position between pickups of a vertical Hall Effect element to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.

Abstract: The invention provides a tunneling magnetoresistance (TMR) read sensor with an integrated auxiliary shield comprising buffer, parallel-coupling, shielding and decoupling layers for high-resolution magnetic recording. The buffer layer, preferably formed of an amorphous ferromagnetic Co—X (where X is Hf, Y, Zr, etc.) film, creates microstructural discontinuity between a lower ferromagnetic shield and the TMR read sensor. The parallel-coupling layer, preferably formed of a polycrystalline nonmagnetic Ru film, causes parallel coupling between the buffer and shielding layers. The shielding layer, preferably formed of a polycrystalline ferromagnetic Ni—Fe film exactly identical to that used as the lower ferromagnetic shield, shields magnetic fluxes stemming from a recording medium into the lower edge of the TMR read sensor.