Abstract: An organic light-emitting device including a compound represented by Formula 1 below: wherein description of Formula 1 above is specified in the detailed description.

Abstract: A solid-state image pickup unit including a pixel section having a plurality of unit pixels two-dimensionally arranged in a matrix formation, wherein a unit pixel includes a conductive region of a first conductivity type having a surface adjacent to a multilayer wiring layer, a charge accumulation region of a second conductivity type formed within the first conductive region, wherein the charge accumulation region is separated from the surface of the conductive region adjacent to the multilayer wiring layer by a separation section, and a contact disposed in the conductive region, the contact electrically connecting the charge accumulation region and an external wire of the multilayer wiring layer.

Abstract: A thin-film transistor (TFT) substrate includes a flexible substrate. A first barrier layer is formed on the flexible substrate. The first barrier layer includes a first silicon oxide layer and a first silicon nitride layer. A second barrier layer is formed on the first barrier layer. The second barrier layer includes a second silicon oxide layer and a second silicon nitride layer. A TFT layer is formed on the second barrier layer. The second silicon oxide layer is disposed adjacent to the TFT layer.

Abstract: An amine-based compound and an organic light-emitting diode including the same are provided.

Abstract: This invention relates to a method for making soluble precursors to imides, polyimides, and polymers containing imide groups, and a method of making thin films of the same by solution casting and then removing the solubilizing group to produce thermally stable and insoluble materials.

Abstract: An organic light-emitting diode includes a substrate, a first electrode, a second electrode facing the first electrode, and an organic layer between the first electrode and the second electrode. The organic layer includes an emission layer, and the emission layer includes a first compound represented by Formula 1 and a second compound represented by Formula 100.

Abstract: A self-light emitting device and an electrical appliance including the same are provided, in which extracting efficiency of light from a light emitting element, especially in an EL element, can be improved. A light scattering body formed by etching a transparent film is provided on an insulator so that the extracting efficiency of light can be improved, and the self-light emitting device with high efficiency of light emission can be provided.

Abstract: A self-light emitting display unit capable of improving manufacturing yield is provided. Sizes of color pixel circuits corresponding to pixels for R, G, and B are respectively set unevenly within a pixel circuit according to a magnitude ratio of drive currents which allow color self-light emitting elements in the pixel to emit with a same light emission luminance. Thereby, the pattern densities of color pixel circuits respectively corresponding to the pixels for R, G, and B become even to each other, and the pattern defect rate as the whole pixel circuit is decreased.

Abstract: A vertical electro-optical component and a method for forming the same are provided. The vertical electro-optical component includes a substrate, a first electrode layer formed on the substrate, a patterned insulating layer formed on the first electrode layer, a metal layer formed on the patterned insulating layer, a semiconductor layer formed on the first electrode layer, and a second electrode layer formed on the semiconductor layer, wherein the semiconductor layer encapsulates the patterned insulating layer and the metal layer. The vertical electro-optical component thus has a low operational voltage of a vertical transistor and a high reaction speed of a photo diode, and may be used to form light-emitting transistors.

Abstract: The present disclosure provides a nitrogen-containing heterocyclic compound and an organic electronic device comprising the same. The organic electronic device according to the present disclosure shows excellent characteristics in terms of efficiency, driving voltage and lifespan.

Abstract: Provided is an organic electroluminescent device (organic EL device) which has improved luminous efficiency and a simple configuration, while ensuring sufficient driving stability. This organic electroluminescent device includes a light-emitting layer between an anode and a cathode that are laminated on a substrate. The light-emitting layer contains a phosphorescent light-emitting dopant, and a carbazole compound represented by the following formula (1) as a host material. In the formula (1), E represents oxygen or sulfur, and R1 to R6 each represent hydrogen, an alkyl group, a cycloalkyl group, or an aromatic group represented by the formula (2). In the formula (2), X represents CR9 or nitrogen.

Abstract: Provided are an organic electroluminescence element, an illumination device, and a display device having lower driving voltage and excellent luminous efficiency. An organic electroluminescence element has a supporting substrate; and a cathode, a light emitting layer and an adjacent layer provided on the supporting substrate, wherein the adjacent layer is arranged adjacent to the outer side of the cathode (i.e., the side opposite to the light emitting layer), wherein the cathode is a transparent layer containing a metal and having a film thickness of 2 nm or more but less than 10 nm; and wherein the adjacent layer has a refractive index of between 1.6 and 1.95, a film thickness of between 15 nm and 180 nm, and contains no light scattering particle.

Abstract: An OLED device includes: a transparent substrate; a light-emitting stack including an anode layer, a cathode layer, and a functional layer, the anode layer including anode units, each of which has first and second anode elements that extend in a column direction and that are aligned with and spaced apart from each other along a row direction transverse to the column direction; an anode-connecting metallic layer stacked on the light-emitting stack; a cathode-connecting metallic layer stacked on the light-emitting stack; and bridging lines disposed in the light-emitting stack and extending in the row direction such that the first and second anode elements are electrically connected to each other through a respective one of the bridging lines.

Abstract: Arrangements of pixel components that allow for full-color devices, while using emissive devices that use blue color altering layers in conjunction with blue emissive regions, that emit at not more than two colors, and/or that use limited number of color altering layers, are provided. Devices disclosed herein also may be achieved using simplified fabrication techniques compared to conventional side-by-side arrangements, because fewer masking steps may be required.

Abstract: A display includes: a light-emitting element formed by laminating a first electrode layer, an organic layer including a light-emitting layer and a second electrode layer in order on a base; and an auxiliary wiring layer being arranged so as to surround the organic layer and being electrically connected to the second electrode layer, in which the auxiliary wiring layer includes a two-layer configuration including a first conductive layer and a second conductive layer, the first conductive layer has lower contact resistance to the second electrode layer than that of the second conductive layer, the two-layer configuration in the auxiliary wiring layer is formed so that an end surface of the second conductive layer is recessed inward from an end surface of the first conductive layer, thereby a part of a top surface of the first conductive layer is in contact with the second electrode layer.

Abstract: An organic electroluminescent lighting device includes an organic electroluminescent element which has a first electrode, a light-emitting layer, and a second electrode, which is formed on a surface of a base substrate and which is sealed with an opposed substrate. The organic electroluminescent lighting device further includes an auxiliary electrode that includes a transparent conductive layer made of optically-transparent electrode material, a conductive resin layer made of electric conductive resin, and a metal film layer made of metal having higher electric conductivity than that of the material of the transparent conductive layer, which are stacked in this order on the surface of the base substrate. The auxiliary electrode is formed on the surface of the base substrate so as to be across an opening edge of the opposed substrate. The auxiliary electrode is formed with a block structure configured to block moisture permeation through the conductive resin layer from outside.

Abstract: The present invention provides an organic EL panel and a manufacturing method of the organic EL layer which can slow the reduction in the light emission lifetime of an organic layer and allow a short-circuit defect to be repaired. Organic EL elements include: an organic EL element including a short-circuit portion, and an altered portion formed to be highly resistive by irradiating a cathode with a laser beam; and an organic EL element which does not include the short-circuit portion. In the organic EL element, an organic EL layer emits light when a voltage higher than or equal to a first voltage is applied. In the organic EL element, the organic EL layer emits light when a voltage higher than equal to a second voltage that is higher than the first voltage is applied.

Abstract: Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is configured with a bitcell having a memory element and a selector element serially connected between an intersection of a wordline and bitline. The selector element can be implemented, for instance, with any number of crystalline materials that exhibit an S-shaped current-voltage (IV) curve, or that otherwise enables a snapback in the selector voltage after the threshold criteria is exceeded. The snapback of the selector is effectively exploited to accommodate the ON-state voltage of the selector under a given maximum supply voltage, wherein without the snapback, the ON-state voltage would exceed that maximum supply voltage. In some example embodiments, the maximum supply voltage is less than 1 volt (e.g., 0.9 volts or less).

Abstract: A semiconductor device includes: a first semiconductor layer of a nitride semiconductor formed on a substrate; a second semiconductor layer of a nitride semiconductor formed on the first semiconductor layer; and a gate electrode, a source electrode, a drain electrode, and a hole extraction electrode, each of which is formed on the second semiconductor layer, wherein between the source electrode and the hole extraction electrode or in a region right under the source electrode, the first semiconductor layer and the second semiconductor layer form a vertical interface approximately perpendicular to a surface of the substrate, and a surface of the first semiconductor layer configured to form the vertical interface is an N-polar surface.

Abstract: Disclosed is a thin film transistor including a light-shielding layer made of the same material as a semiconductor layer on a substrate, and a method for fabricating the same. The thin film transistor includes a substrate, a light-shielding layer and a buffer layer formed on the substrate in this order, a semiconductor layer formed on the buffer layer, the semiconductor layer formed of the same material as the light-shielding layer, a gate insulating film and a gate electrode formed on the semiconductor layer in this order, an interlayer insulating film formed on the substrate such that it covers the gate electrode, the interlayer insulating film comprising a source contact hole and a drain contact hole exposing source and drain areas of the semiconductor layer, respectively, and a source electrode and a drain electrode electrically connected to the semiconductor layer through the source contact hole and the drain contact hole.

Abstract: The invention provides an array substrate, a fabrication method thereof and a display device. The array substrate comprises a base substrate; a gate layer which is disposed on the base substrate and comprises a gate; a gate insulating layer disposed on the gate layer; a source layer which is disposed on the gate insulating layer and comprises a source; a metal oxide semiconductor layer which is disposed on the source layer and the gate insulating layer and comprises an active layer, wherein the source is in direct contact with the active layer; and a pixel electrode layer in direct contact with the active layer. A position where the gate is formed in the gate layer corresponds to a position between the source and a contacting portion of the pixel electrode layer with the active layer.

Abstract: A method for processing an oxide semiconductor containing indium, gallium, and zinc is provided. In the method, the oxide semiconductor layer comprises a plurality of excess oxygen, a first oxygen vacancy that is close to first indium and captures first hydrogen, and a second oxygen vacancy that is close to second indium and captures second hydrogen, the first hydrogen captured by the first oxygen vacancy is bonded to one of a plurality of excess oxygen to so that a hydroxyl is formed; the hydroxyl is bonded to the second hydrogen captured by the second oxygen vacancy to release as water; and then, the first oxygen vacancy captures one of excess oxygen and the second oxygen vacancy captures one of excess oxygen.

Abstract: A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled.

Abstract: When an oxide semiconductor film is microfabricated to have an island shape, with the use of a hard mask, unevenness of an end portion of the oxide semiconductor film can be suppressed. Specifically, a hard mask is formed over the oxide semiconductor film, a resist is formed over the hard mask, light exposure is performed to form a resist mask, the hard mask is processed using the resist mask as a mask, the oxide semiconductor film is processed using the processed hard mask as a mask, the resist mask and the processed hard mask are removed, a source electrode and a drain electrode are formed in contact with the processed oxide semiconductor film, a gate insulating film is formed over the source electrode and the drain electrode, and a gate electrode is formed over the gate insulating film, the gate electrode overlapping with the oxide semiconductor film.

Abstract: To provide an oxide semiconductor film including a low-resistance region, which can be applied to a transistor. To provide a transistor including the oxide semiconductor film, which can perform at high speed. To provide a high-performance semiconductor device including the transistor including the oxide semiconductor film, which can perform at high speed, with high yield. A film having a reducing property is formed over the oxide semiconductor film. Next, part of oxygen atoms are transferred from the oxide semiconductor film to the film having a reducing property. Next, an impurity is added to the oxide semiconductor film through the film having a reducing property and then, the film having a reducing property is removed, so that a low-resistance region is formed in the oxide semiconductor film.

Abstract: One object is to have stable electrical characteristics and high reliability and to manufacture a semiconductor device including a semi-conductive oxide film. Film formation is performed by a sputtering method using a target in which gallium oxide is added to a material that is easy to volatilize compared to gallium when the material is heated at 400° C. to 700° C. like zinc, and a formed film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film and the oxide is crystallized. Further, a semi-conductive oxide film is deposited thereover, whereby a semi-conductive oxide having a crystal which succeeds a crystal structure of the oxide that is crystallized by heat treatment is formed.

Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.

Abstract: An object is to reduce the manufacturing cost of a semiconductor device. An object is to improve the aperture ratio of a semiconductor device. An object is to make a display portion of a semiconductor device display a higher-definition image. An object is to provide a semiconductor device which can be operated at high speed. The semiconductor device includes a driver circuit portion and a display portion over one substrate. The driver circuit portion includes: a driver circuit TFT in which source and drain electrodes are formed using a metal and a channel layer is formed using an oxide semiconductor; and a driver circuit wiring formed using a metal. The display portion includes: a pixel TFT in which source and drain electrodes are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor; and a display wiring formed using an oxide conductor.

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

Abstract: An integrated test circuit, including a plurality of test structure elements, wherein each test structure element includes at least a supply line and a test line; a plurality of select transistors, wherein each select transistor is assigned to one corresponding test structure element, and wherein each select transistor includes a first controlled region, a second controlled region, and a control region, wherein the second controlled region of each select transistor is respectively connected to the supply line of the corresponding test structure element, so that each select transistor is unambiguously assigned to the corresponding test structure element; and a plurality of contact pads, connected to respective first controlled regions and control regions of the plurality of select transistors, such that each test structure element of the plurality of test structure elements can be individually addressed by the plurality of contact pads.

Abstract: An integrated circuit including a semiconductor device has a power component including a plurality of trenches in a cell array, the plurality of trenches running in a first direction, and a sensor component integrated into the cell array of the power component and including a sensor cell having an area which is smaller than an area of the cell array of the power component. The integrated circuit further includes isolation trenches disposed between the sensor component and the power component, an insulating material being disposed in the isolation trenches. The isolation trenches run in a second direction that is different from the first direction.

Abstract: The invention discloses a method of fabricating a GOI silicon wafer, a GOI silicon wafer, and a method of GOI detection on the fabricated GOI silicon wafer, where the method of fabricating a GOI silicon wafer includes: in a process of fabricating a trench-type VDMOS, after a trench is formed and a gate oxide layer is grown, a poly-silicon layer is grown; and after the poly-silicon layer is grown, a mask of a metal layer is aligned with a silicon substrate with the poly-silicon layer grown, where the mask of the metal layer is a mask used in formation of the metal layer in the process of fabricating the VDMOS; and at least one pattern for GOI detection is formed on the silicon substrate with the poly-silicon layer grown, through the aligned mask of the metal layer in a photo-lithography to form a GOI silicon wafer.

Abstract: A semiconductor apparatus includes a TSV formed to be electrically connected with another chip and a TSV test unit configured to check a capacitance component of the TSV to generate a TSV abnormality signal.

Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

Abstract: A semiconductor device is disclosed allowing detection of a connection state of a Through Silicon Via (TSV) at a wafer level. The semiconductor device includes a first line formed over a Through Silicon Via (TSV), a second line formed over the first line, and a first power line and a second power line formed over the same layer as the second line. Therefore, the semiconductor device can screen not only a chip-to-chip connection state after packaging completion, but also a connection state between the TSV and the chip at a wafer level, so that unnecessary costs and time encountered in packaging of a defective chip are reduced.

Abstract: A display device includes a signal line disposed on a substrate. A signal input line is disposed on the substrate and connected to a driver. A first insulating layer is disposed on the signal line. A second insulating layer is disposed on the signal input line and the first insulating layer. First contact holes penetrate the first insulating layer and the second insulating layer and expose a portion of the signal line. Second contact holes penetrate the second insulating layer and expose a portion of the signal input line. A connecting member connects the signal line and the signal input line through the first and the second contact holes and is disposed on the second insulating layer. The first and the second contact holes are alternately arranged in the second insulating layer.

Abstract: A thin-film transistor device includes a gate electrode formed above a substrate, a gate insulating film formed on the gate electrode, a crystalline silicon thin film that is formed above the gate insulating film and has a channel region, an amorphous silicon thin film formed on the crystalline silicon thin film, and a source electrode and a drain electrode that are formed above the channel region, and the crystalline silicon thin film has a half-width of a Raman band corresponding to a phonon mode specific to the crystalline silicon thin film of 5.0 or more and less than 6.0 cm?1, and an average crystal grain size of about 50 nm or more and 300 nm or less.

Abstract: Embodiments of the present invention provide a method of manufacturing a pixel unit, in which only a single patterning process and a single doping process are performed on a polysilicon layer so as to form heavily doped regions of a thin film transistor and a lower electrode of a storage capacitor respectively, thereby reducing numbers of photolithography and masking processes required to manufacture a LTPS-TFT, shortening time periods for development and mass production, and reducing complexity of processes as well as monitoring difficulty, and decreasing the production cost. The present invention further provides a pixel unit manufactured according to the method, an array substrate and a display device including the same.

Abstract: An array substrate, which is formed with a gate electrode (2), a source electrode (5), a drain electrode (6), a gate insulating layer (3), an active layer (4) and a passivation layer (9) in a thin film transistor region, and with the gate insulating layer (3), a pixel electrode (7), the passivation layer (9) and a common electrode (8) in a pixel electrode pattern region, and a color resin layer (11) is formed between the passivation layer (9) and the common electrode (8). Since the color resin layer (11) for planarization is formed on the passivation layer (9), the horizontal driving manner may be suitably applied in order to reduce light leakage, to improve contrast ratio and aperture ratio of a panel and to lower production costs.

Abstract: A display unit includes: a display layer including a pixel electrode; a semiconductor layer provided in a layer below the display layer, the semiconductor layer including a wiring layer that includes a material removable by an etchant by which the pixel electrode is also removable; and a terminal section configured to electrically connect the semiconductor layer to an external circuit, the terminal section including a first electrically-conductive layer made of a material same as a material of the wiring layer.

Abstract: A thin film transistor (TFT) array panel and a manufacturing method thereof are disclosed. A contact hole may be formed to expose a pad disposed on a substrate of the TFT array panel. A first layer of a connecting member is formed with the same layer as a first field generating electrode and is disposed in the contact hole. A second passivation layer is disposed in the TFT array panel, but is removed at a region where the contact hole is formed and portions of the second passivation layer that cover the first layer of the connecting member. A second layer of the connecting member is formed on the first layer of the connecting member.

Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.

Abstract: A display device comprises a first pixel circuit and a second pixel circuit adjacent to the first pixel circuit along a first direction. The first pixel circuit includes a first transistor and a first electro-optic element, and the second pixel circuit includes a second transistor and a second electro-optic element. A power supply line extends along the first direction. A connection wiring is connected between the first transistor and the second transistor, and is connected to the power supply line via a contact portion having at least two contact holes.

Abstract: The present disclosure relates to a gallium-nitride (GaN) transistor device having a composite gallium nitride layer with alternating layers of GaN and aluminum nitride (AlN). In some embodiments, the GaN transistor device has a first GaN layer disposed above a semiconductor substrate. An AlN inter-layer is disposed on the first GaN layer. A second GaN layer is disposed on the AlN inter-layer. The AlN inter-layer allows for the thickness of the GaN layer to be increased over continuous GaN layers, mitigating bowing and cracking of the GaN substrate, while improving the breakdown voltage of the disclosed GaN device.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material.

Abstract: The present disclosure relates to a channel layer of bi-layer of gallium nitride (GaN) within a HEMT. A first breakdown voltage layer of GaN is disposed beneath an active layer of the HEMT. A second breakdown voltage layer of GaN is disposed beneath the first breakdown voltage layer, wherein the first resistivity value is less than the second resistivity value. An increased resistivity of the second breakdown voltage layer results from an increased concentration of carbon dopants which increases the breakdown voltage in the second breakdown voltage layer, but can degrade the crystal structure. To alleviate this degradation, a crystal adaptation layer is disposed beneath the second breakdown voltage layer and configured to lattice-match to the second breakdown voltage layer of GaN. As a result, the HEMT achieves a high breakdown voltage without any associated degradation to the first breakdown voltage layer, wherein a channel of the HEMT resides.

Abstract: A semiconductor light emitting element includes: an n-type semiconductor layer; a light emitting layer alternately laminating plural barrier layers and plural well layers; and a p-type semiconductor layer, wherein the light emitting layer includes three or more well layers and four or more barrier layers, each well layer being sandwiched by the barrier layers, one barrier layer contacting the n-type semiconductor layer, and another barrier layer contacting the p-type semiconductor layer, the well layers include plural n-side well layers from the n-type semiconductor layer side and one p-side well layer on the p-type semiconductor layer side, and a V-shaped concave portion including inclined surfaces is generated in the light emitting layer, and in at least one of the n-side well layers, a concentration of atoms of In on the inclined surface is not more than 50% of a concentration of atoms of In in the n-side well layer.

Abstract: A high electron mobility transistor having a channel layer, electron supply layer, source electrode, and drain electrode is included so as to have a cap layer formed on the electron supply layer between the source and drain electrodes and having an inclined side surface, an insulating film having an opening portion on the upper surface of the cap layer and covering the side surface thereof, and a gate electrode is formed in the opening portion and extending, via the insulating film, over the side surface of the cap layer on the drain electrode side. The gate electrode having an overhang on the drain electrode side can reduce the peak electric field.

Abstract: The invention provides an optoelectronic device adapted to emit ultraviolet light, including an aluminum nitride single crystalline substrate, wherein the dislocation density of the substrate is less than about 105 cm?2 and the Full Width Half Maximum (FWHM) of the double axis rocking curve for the (002) and (102) crystallographic planes is less than about 200 arcsec; and an ultraviolet light-emitting diode structure overlying the aluminum nitride single crystalline substrate, the diode structure including a first electrode electrically connected to an n-type semiconductor layer and a second electrode electrically connected to a p-type semiconductor layer. In certain embodiments, the optoelectronic devices of the invention exhibit a reverse leakage current less than about 10?5 A/cm2 at ?10V and/or an L80 of at least about 5000 hours at an injection current density of 28 A/cm2.

Abstract: A semiconductor device which reduces a source resistance and a manufacturing method for the same are provided. The semiconductor device has a nitride based compound semiconductor layer arranged on a substrate, an active region which has an aluminum gallium nitride layer arranged on the nitride based compound semiconductor layer, and a gate electrode, source electrode and drain electrode arranged on the active region. The semiconductor device has gate terminal electrodes, source terminal electrodes and drain terminal electrode connected to the gate electrode, source electrode and drain electrode respectively. The semiconductor device has end face electrodes which are arranged on a side face of the substrate by a side where the source terminal electrode is arranged, and which are connected to the source terminal electrode. The semiconductor device has a projection arranged on the end face electrode which prevents solder used in die bonding from reaching the source terminal electrodes.