Abstract: A transistor or the like having high field-effect mobility is provided. A transistor or the like having stable electrical characteristics is provided. A semiconductor device including a first oxide semiconductor layer, a second oxide semiconductor layer, a gate insulating film, and a gate electrode which partly overlap with one another is provided. The second oxide semiconductor layer is positioned between the first oxide semiconductor layer and the gate insulating film. The gate insulating film is positioned between the second oxide semiconductor layer and the gate electrode. The first oxide semiconductor layer has fewer oxygen vacancies than those of the second oxide semiconductor layer.

Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.

Abstract: A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.

Abstract: The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer.

Abstract: Semiconductor test devices and methods for fabricating the same may be provided. The semiconductor test device may include a first thermal test flip chip cell including a first heater and a first sensor, and a test substrate formed under the first thermal test flip chip cell. The first thermal test flip chip cell may include a plurality of first bumps arranged on a bottom surface of the first thermal test flip chip cell and be configured to be electrically connected to the first heater and the first sensor. The test substrate may include a first ball array arranged on a bottom surface of the test substrate in a first direction and be configured to be electrically connected to the plurality of first bumps, which are electrically connected to the first heater and the first sensor.

Abstract: A GeSi avalanche photodiode (APD includes an anti-reflection structure, a Ge absorption region, and a resonance cavity enhanced (RCE) reflector. The anti-reflection structure includes one or more dielectric layers and a top contact layer which is heavily doped with dopants of a first polarity. The RCE reflector includes: an intrinsic or lightly doped Si multiplication layer, a Si contact layer which is heavily doped with dopants of a second polarity opposite the first polarity, a Si cavity length compensation layer, a buried oxide (BOX) layer, and a Si substrate.

Abstract: An object is to realize a hermetically sealed package which ensures long-term airtightness inside the package by sealing using a substrate, or a sealing structure for reducing destruction caused by pressure from the outside. A frame of a semiconductor material is provided over a first substrate, which is bonded to a second substrate having a semiconductor element so that the semiconductor element is located inside the frame between the first substrate and the second substrate. The frame may be formed using, as frame members, two L-shaped semiconductor members in combination or four or more stick semiconductor members in combination.

Abstract: Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices.

Abstract: According to one embodiment, a display device includes a semiconductor including a first channel region, a second channel region, a source region, a drain region, a first region located between the source region and the first channel region, a second region formed between the first channel region and the second channel region, and a third region located between the drain region and the second channel region, wherein the second region has a length of 5 ?m or more, which is greater than a length of each of the first region and the third region.

Abstract: A preferred method of optimizing a Ga-nitride device material structure for a frequency multiplication device comprises: determining the amplitude and frequency of the input signal being multiplied in frequency; providing a Ga-nitride region on a substrate; determining the Al percentage composition and impurity doping in an AlGaN region positioned on the Ga-nitride region based upon the power level and waveform of the input signal and the desired frequency range in order to optimize power input/output efficiency; and selecting an orientation of N-face polar GaN or Ga-face polar GaN material relative to the AlGaN/GaN interface so as to orient the face of the GaN so as to optimize charge at the AlGaN/GaN interface. A preferred embodiment comprises an anti-serial Schottky varactor comprising: two Schottky diodes in anti-serial connection; each comprising at least one GaN layer designed based upon doping and thickness to improve the conversion efficiency.

Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.

Abstract: A rare earth oxide gate dielectric on III-N material grown on a silicon substrate includes a single crystal stress compensating template positioned on a silicon substrate. The stress compensating template is substantially crystal lattice matched to the surface of the silicon substrate. A GaN structure is positioned on the surface of the stress compensating template and substantially crystal lattice matched thereto. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched thereto. A single crystal rare earth oxide dielectric layer is grown on the active layer of III-N material.

Abstract: Embodiments of a semi-insulating Group III nitride and methods of fabrication thereof are disclosed. In one embodiment, a semi-insulating Group III nitride layer includes a first doped portion that is doped with a first dopant and a second doped portion that is doped with a second dopant that is different than the first dopant. The first doped portion extends to a first thickness of the semi-insulating Group III nitride layer. The second doped portion extends from approximately the first thickness of the semi-insulating Group III nitride layer to a second thickness of the semi-insulating Group III nitride layer. In one embodiment, the first dopant is Iron (Fe), and the second dopant is Carbon (C). In another embodiment, the semi-insulating Group III nitride layer is a semi-insulating Gallium Nitride (GaN) layer, the first dopant is Fe, and the second dopant is C.

Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

Abstract: Disclosed is a method of manufacturing a light emitting device. More particularly, disclosed are a growth substrate, a nitride semiconductor device and a method of manufacturing a light emitting device. The method includes preparing a growth substrate including a metal substrate, forming a semiconductor structure including a nitride-based semiconductor on the growth substrate, providing a support structure on the semiconductor structure, and separating the growth substrate from the semiconductor structure.

Abstract: A semiconductor device includes a buffer layer, a channel layer and a barrier layer formed over a substrate, a trench penetrating through the barrier layer to reach the middle of the channel layer, and a gate electrode disposed inside the trench via a gate insulating film. The channel layer contains n-type impurities, and a region of the channel layer positioned on a buffer layer side has an n-type impurity concentration larger than a region of the channel layer positioned on a barrier layer side, and the buffer layer is made of nitride semiconductor having a band gap wider than that of the channel layer. The channel layer is made of GaN and the buffer layer is made of AlGaN. The channel layer has a channel lower layer containing n-type impurities at an intermediate concentration and a main channel layer formed thereon and containing n-type impurities at a low concentration.

Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher.

Abstract: A method of producing a light-emitting semiconductor device of a group III nitride compound includes forming a buffer layer on a sapphire substrate, forming a Si-doped N+-layer with supplying silane, the N+-layer satisfying formula (Alx3Ga1-x3)y3In1-y3N, wherein 0?x3?1, 0?y3?1 and 0?x3+y3?1, forming an emission layer of a group III nitride compound semiconductor satisfying formula Alx1Gay1In1-x1-y1N, where 0?x1?1, 0?y1?1, and 0?x1+y1?1, on the N+-layer, and forming a P-layer of a P-type conduction on the emission layer, the P-layer including aluminum gallium nitride satisfying formula Alx2Ga1-x2N, wherein 0?x2?1.

Abstract: A photocoupler includes: a light emitting element; a first photodiode array; a second photodiode array; a third photo diode array; an enhancement-mode MOSFET; a first depletion-mode MOSFET; and a second depletion mode MOSFET. The light emitting element converts the input electrical signal into the optical signal. A drain current of the enhancement-mode MOSFET is supplied to the external load when the optical signal is ON. A drain current of the first depletion-mode MOSFET is supplied to the external load when the optical signal is OFF and a voltage passing through the second depletion-mode MOSFET switched to the ON state is supplied to the gate of the first depletion-mode MOSFET. And the drain current of the first depletion-mode MOSFET is larger than a drain current of the first depletion-mode MOSFET when a gate voltage of the first depletion-mode MOSFET is zero.

Abstract: The invention provides a package structure of optical transceiver component, comprising: a metal base; a plurality of pins, at least one optical emitting diode and/or at least one optical receiving diode; wherein the pins are provided and passed through the metal base and insulated with the metal base by using an insulating material; the optical emitting diode and the optical receiving diode are each mounted on the metal base through a sub-mount, respectively. The optical emitting diode/optical receiving diode is connected to the pins neighboring therewith by a wire directly or through the sub-mount, when set the top surface of the pins be a reference level, at least one of the top surfaces of the optical emitting diode, the optical receiving diode, and sub-mount is flush with the reference level.

Abstract: Light emitter packages and related methods having improved performance are disclosed. In one aspect, a light emitter package can include at least one light emitter chip disposed over a substrate or submount. In some aspects, the package can include a reflective polymeric material or polymeric reflector (sometimes referred to as a “solder mask” or “solder mask material”), a reflective material, and a conductive material disposed adjacent each other within a portion of the light emitter package. In some aspects, the reflective material can include a metallic material or metallic reflector applied to side walls of traces and/or within portions of a gap between traces prior to application of the reflective polymeric material within the gap.

Abstract: A display device includes a substrate and a flexible circuit having one of its ends bonded to the substrate. The substrate comprises a pixel array. A driver integrated circuit (IC) is mounted on the flexible circuit. The flexible circuit is bonded to the substrate without protruding beyond an edge of the substrate. One end of the flexible circuit faces toward an inside of the substrate when the flexible circuit is flatly placed on or over the substrate, and the other end of the flexible circuit is bonded to the edge of the substrate.

Abstract: The light emitting device including: a flexible substrate having a negative lead electrode and a positive lead electrode formed on an upper surface thereof; a light emitting element having a negative electrode and a positive electrode formed on an upper surface thereof; an insulating film formed on a side surface of the light emitting element; a wiring formed in contact with the insulating film for connecting between the negative electrode and the negative lead electrode, or between the positive electrode and the positive lead electrode.

Abstract: A light emitting device including a light emitting structure comprising a plurality of light emitting regions comprising a first semiconductor layer, an active layer and a second semiconductor layer, a first electrode unit disposed on the first semiconductor layer in one of the light emitting regions, a second electrode unit disposed on the second semiconductor layer in another of the light emitting regions, and at least one connection electrode to sequentially connect the light emitting regions in series, wherein the light emitting regions connected in series are divided into 1st to ith light emitting region groups and areas of light emitting regions that belong to different groups are different (where 1<i?j, each of i and j is a natural number, and j is a last light emitting region group).

Abstract: A light emitting apparatus comprises an electrically insulating base member; a pair of electrically conductive pattern portions formed on an upper surface of the base member; at least one light emitting device that is electrically connected to the pair of electrically conductive pattern portions; and a resin portion that surrounds at least a side surface of the at least one light emitting device and partially covers the pair of electrically conductive pattern portions. Each of the pair of electrically conductive pattern portions extends toward a periphery of the base member from resin-covered parts of the electrically conductive pattern portions. At least the resin-covered parts of each of the electrically conductive pattern portions has at least one elongated through hole extending in a direction in which the electrically conductive pattern portions extend from the resin-covered parts, wherein the resin portion contacts the base member via the through holes.

Abstract: Various examples of a lighting device, backlight module and illumination module are described. A lighting device includes a carrier component, an LED chip, a thermistor, and a plurality of metal wires. The carrier component includes a plurality of electrodes. The LED chip and the thermistor are disposed on the carrier component and electrically coupled to each other. The plurality of metal wires form a circuit with the plurality of electrodes, the LED chip, and the thermistor. The thermistor has dimensions in chip-level scale when viewed from the top of the lighting device. A backlight module includes the aforementioned lighting device. An illumination module includes the aforementioned lighting device and a driver which is electrically coupled to the lighting device.

Abstract: Disclosed is a light emitting device array. The light emitting device array comprises a light emitting device and a body comprises first and second lead frames electrically connected to the light emitting device and a substrate on which the light emitting device package is disposed, the substrate comprises a base layer and a metal layer disposed on the base layer and electrically connected to the light emitting device package, wherein the metal layer comprises first and second electrode patterns electrically connected to the first and second lead frames and a heat dissipation pattern insulated from at least one of the first or(and) second electrode patterns, absorbing heat generated from at least one of the base layer or(and) the light emitting device package and then dissipating the heat.

Abstract: A plurality of conductive pads are disposed on a substrate. A plurality of semiconductor dies are each disposed on a respective one of the conductive pads. A mold device is positioned over the substrate. The mold device contains a plurality of recesses that are each configured to accommodate a respective one of the semiconductor dies underneath.

Abstract: This invention provides a germanium electroluminescence device and a fabricating method of the same for using germanium of an indirect bandgap semiconductor without modifying a bandgap as a light-emitting layer which emits a 1550 nm-wavelength light and enabling to use not only as infrared LEDs itself but also as light sources for optical communication systems.

Abstract: Light emitter components and methods having improved performance and related methods are disclosed. In one embodiment, a light emitter component can include a submount and at least one light emitting diode (LED) chip disposed over the submount. The submount can contact at least two different sides of the at least one LED chip. In one aspect, a submount can include surface portions adapted to receive portions one or more LED chips. In one aspect, one or more LED chips can be embedded within the submount.

Abstract: A light emitting diode (LED) backlight module includes a transparent conductive substrate that has an electrode-bearing surface and a plurality of transparent conductive electrodes disposed on the electrode-bearing surface, an LED chip that is welded on the transparent conductive electrodes by flip-chip packaging techniques, and a reflecting member that is spaced apart from and that corresponds in position to the LED chip so as to reflect light generated from the LED chip to the transparent conductive substrate.

Abstract: The device according to the invention comprises a nanostructured LED with a first group of nanowires protruding from a first area of a substrate and a contacting means in a second area of the substrate. Each nanowire of the first group of nanowires comprises a p-i-n-junction and a top portion of each nanowire or at least one selection of nanowires is covered with a light reflecting contact layer. The contacting means of the second area is in electrical contact with the bottom of the nanowires, the light-reflecting contact layer being in electrical contact with the contacting means of the second area via the p-i-n-junction. Thus when a voltage is applied between the contacting means of the second area and the light-reflecting contact layer, light is generated within the nanowire. On top of the light-reflecting contact layer, a first group of contact pads for flip-chip bonding can be provided, distributed and separated to equalize the voltage across the layer to reduce the average serial resistance.

Abstract: The present application relates to a light emitting device package. The light emitting device package includes a package substrate in which a via hole is formed. An electrode layer extends to both surfaces of the package substrate after passing through the via hole. A light emitting device is arranged on the package substrate and is connected to the electrode layer. A fluorescence film includes a first part that fills at least a part of an internal space of the via hole and a second part that covers at least a part of the light emitting device.

Abstract: A color filter substrate includes a second base material, a stopper film provided on the second base material, an insulating film including color filter grooves provided on the stopper film, and color filters provided so as to embed the color filter grooves.

Abstract: An optical communication module includes an optical semiconductor element. The element includes an optical functional region having a light receiving function or a light emitting function, a first transmission layer transmissive to light emitted from the optical functional region or light received by the optical functional region, and a wiring layer stacked on the first transmission layer and constituting a conduction path to the optical functional region. The communication module also includes a second transmission layer transmissive to the light and disposed to cover the optical semiconductor element, and a first resin member stacked on the second transmission layer. The communication module is formed with a fixing hole for fixing an optical fiber. The fixing hole includes a bottom face provided by the second transmission layer, and an opening formed in an outer surface of the first resin member.

Abstract: Disclosed is a light emitting device including: a light emitting element including an LED chip and a phosphor layer provided at the light emitting side of the LED chip; and a substrate on which the light emitting element is bonded by an adhesive material. The adhesive material is an anisotropic conductive material.

Abstract: A light emitting device includes a base that has an element mounting surface, a light emitting element that is mounted on the element mounting surface and that has maximum light intensity in a directly upward direction, and a coating member that contains a fluorescent body that is excited by light from the light emitting element, and that is constituted by a single layer that coats an upper part of the light emitting element. The fluorescent body exists at a position other than directly above the light emitting element.

Abstract: Certain example embodiments relate to improved lighting systems and/or methods of making the same. In certain example embodiments, a lighting system includes a glass substrate with one or more apertures. An LED or other light source is disposed at one end of the aperture such that light from the LED directed through the aperture of the glass substrate exits the opposite end of the aperture. Inner surfaces of the aperture have a mirroring material such as silver to reflect the emitted light from the LED. In certain example embodiments, a remote phosphor article or layer is disposed opposite the LED at the other end of the aperture. In certain example embodiment, a lens is disposed in the aperture, between the remote phosphor article and the LED.

Abstract: A package structure of semiconductor light emitting element is provided. The package structure of semiconductor light emitting element includes a substrate, a light emitting element and a transparent conductive board. A first electrode and a second electrode are disposed on the substrate. The light emitting element is disposed on the substrate and between the first electrode and the second electrode. A first bonding pad and a second bonding pad are disposed on the light emitting element. The transparent conductive board has a first surface and a second surface opposite to the first surface. The second surface of the transparent conductive board is located over the light emitting element for electrically connecting the first electrode and the first bonding pad and electrically connecting the second electrode and the second bonding pad.

Abstract: Formation of an interlayer is realized for a light-emitting device, the interlayer having properties of anticorrosion and adhesion to a silicone layer, thus preventing incidence of cracking during a baking process. The light-emitting device comprises a light-emitting element covered with the silicone layer, and the interlayer is provided between the light-emitting element and the silicone layer. The interlayer is formed of a mixture of a tri-functional polysiloxane and a tetra-functional polysiloxane.

Abstract: A semiconductor lighting device may include at least one semiconductor light source and a lens, wherein the lens has a light entrance surface at the underside, said light entrance surface facing the at least one semiconductor light source, and a light exit surface at the top side, the light entrance surface has a light deflection structure in the form of a TIR structure, at which entering light can be deflected in the direction of the light exit surface by means of total internal reflection, and the lens is fitted to the semiconductor lighting device in a detachable fashion.

Abstract: This invention discloses a substrate for a light-emitting device and light-emitting device using the same, and the substrate comprises a sapphire substrate. The sapphire substrate comprises a surface having a plurality of cones, heights of the cones are ranged from 1.4-1.9 ?m, diameters of the cones are ranged from 2.4-2.9 ?m, base angles between the bottom of each of the cones and the level surface of the sapphire substrate are ranged from 40°-80°, the plurality of cones are uniformly distributed over the sapphire substrate and do not contact each other, a distance between the apexes of each two neighboring cones is ranged from 2.5-3.5 ?m, a distance between the bottoms of each two neighboring cones is ranged from 0.1-0.6 ?m. Further, the substrate of the light-emitting device further comprises an interlayer covering the sapphire substrate to increase the epitaxy speed and enhance the throughput subsequently.

Abstract: This invention discloses a substrate for a light-emitting device and light-emitting device using the same, and the substrate comprises a sapphire substrate. The sapphire substrate comprises a surface having a plurality of cones, heights of the cones are ranged from 1.6-2.1 ?m, diameters of the cones are ranged from 3.4-3.9 ?m, base angles between the bottom of each of the cones and the level surface of the sapphire substrate are ranged from 40°-80°, the plurality of cones are uniformly distributed over the sapphire substrate and do not contact each other, a distance between apexes of each two neighboring cones is ranged from 3.5-4.5 ?m, a distance between the bottoms of each two neighboring cones is ranged from 0.1-0.6 ?m. Further, the substrate of the light-emitting device further comprises an interlayer covering the sapphire substrate to increase the epitaxy speed and enhance the throughput subsequently.

Abstract: This invention discloses a substrate for a light-emitting device and light-emitting device using the same, and the substrate comprises a sapphire substrate. The sapphire substrate comprises a surface having a plurality of cones, heights of the cones are ranged from 0.6-1.6 ?m, diameters of the cones are ranged from 0.6-1.6 ?m, base angles between the bottom of each of the cones and the level surface of the sapphire substrate are ranged from 40°-80°, the plurality of cones are uniformly distributed over the sapphire substrate and do not contact each other, a distance between the apexes of each two neighboring cones is ranged from 1.7-2.3 ?m, a distance between the bottoms of each two neighboring cones is ranged from 0.4-1.4 ?m. Further, the substrate of the light-emitting device further comprises an interlayer covering the sapphire substrate to increase the epitaxy speed and enhance the throughput subsequently.

Abstract: The light emitting device includes: a substrate; a first conductive-type semiconductor layer laminated on the substrate; a light emitting layer laminated on the first conductive-type semiconductor layer; a second conductive-type semiconductor layer laminated on the light emitting layer; a first ITO layer, a second ITO layer, a first metal layer and a second metal layer. The first ITO layer is laminated at a side of the first conductive-type semiconductor layer opposite to the substrate. The second ITO layer is laminated at a side of the second conductive-type semiconductor layer opposite to the substrate. The first metal layer is laminated on the first ITO layer. The second metal layer is laminated on the second ITO layer.

Abstract: The light emitting element including: a semiconductor laminate including a first layer, an active layer and a second layer; a first electrode including protrusions that penetrate the second layer and the active layer, the first electrode connected to the first layer via the protrusions; a second electrode connected to the second layer on an lower face of the second layer; and an insulation film between the protrusions and the semiconductor laminate, wherein the protrusions each include a protrusion body covered with the insulation film and a protrusion tip, an upper face and a side face of the protrusion tip being exposed from the insulation film, the first layer includes recesses arranged on an upper face of the first layer so as to sandwich first areas located above the respective the protrusions, and a distance between the recesses sandwiching the first area is larger than a width of the protrusion tip.

Abstract: An LED device and method of manufacture including separately coupling a thin flexible interposer and an LED die to a heat sink structure and then electrically coupling the interposer and the LED die together with a wirebond. A specifically shaped perimeter of an aperture within the interposer negates the need for a cavity or alignment markings within the heat sink structure by limiting the orientation in which the die fits within the aperture. Alternatively, an LED device and method of manufacture include coupling a rigid circuit board to an LED die such that electrical contacts of the die are electrically coupled with electrical input/output terminals of the circuit board. This die/board unit is then able to be coupled to a heat sink structure to form a portion of the device.

Abstract: Bi-directional silicon controlled rectifier device structures and design structures, as well as fabrication methods for bi-directional silicon controlled rectifier device structures. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. An anode of a first silicon controlled rectifier is formed in the first well. A cathode of a second silicon controlled rectifier is formed in the first well. The anode of the first silicon controlled rectifier has the first conductivity type. The cathode of the second silicon controlled rectifier has a second conductivity type opposite to the first conductivity type.

Abstract: There is provided a power semiconductor device, including a first conductive type drift layer; a second conductive type body layer formed on the drift layer, a second conductive type collector layer formed below the drift layer; a first gate formed by penetrating through the body layer and a portion of the drift layer, a first conductive type emitter layer formed in the body layer and formed to be spaced apart from the first gate, a second gate covering upper portions of the body layer and the emitter layer and formed as a flat type gate on the first gate, and a segregation stop layer formed between contact surfaces of the first and second gates with the body layer, the emitter layer, and the drift layer.

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.