Abstract: An embodiment of a fractal fixed capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure. The capacitor body has a first plate with a fractal shape separated by a horizontal distance from a second plate with a fractal shape. The first plate and the second plate are within the same plane. Such a fractal fixed capacitor further comprises a substrate above which the capacitor body is positioned.

Abstract: In one general aspect, an apparatus includes a first capacitor defined by a dielectric disposed between a bump metal and a region of a first conductivity type, and a second capacitor in series with the first capacitor and defined by a PN junction including the region of the first conductivity type and a region of a second conductivity type. The region of the first conductivity type can be configured to be coupled to a first node having a first voltage, and the region of the second conductivity type can be configured to be coupled to a second node having a second voltage different than the first voltage.

Abstract: Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (Tcc) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (Vcc2) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.

Abstract: An integrated circuit contains three thin film resistors over a dielectric layer. The first resistor body includes only a bottom thin film layer and the first resistor heads include the bottom thin film layer, a middle thin film layer and a top thin film layer. The second resistor body and heads include all three thin film layers. The third resistor body does not include the middle thin film layer. The three resistors are formed using two etch masks.

Abstract: A guard structure for a semiconductor structure is provided. The guard structure includes a first guard ring, a second guard ring and a third guard ring. The first guard ring has a first conductivity type. The second guard ring has a second conductivity type, and surrounds the first guard ring. The third guard ring has the first conductivity type, and surrounds the second guard ring, wherein the first, the second and the third guard rings are grounded. A method of forming a guard layout pattern for a semiconductor layout pattern is also provided.

Abstract: A semiconductor device includes an emitter region, a collector region and a base region. The emitter region is implanted in a semiconductor substrate. The collector region is implanted in the semiconductor substrate. The base region is disposed between the emitter region and collector region. The base region includes no more than one LDD region and no more than one halo region. The base region contacts directly with at least one of the emitter region and the collector region.

Abstract: Provided is a substrate for epitaxial growth, which enables the improvement in quality of a Ga-containing oxide layer that is formed on a ?-Ga2O3 single-crystal substrate. A substrate (1) for epitaxial growth comprises ?-Ga2O3 single crystals, wherein face (010) of the single crystals or a face that is inclined at an angle equal to or smaller than 37.5° with respect to the face (010) is the major face. A crystal laminate structure (2) comprises: the substrate (1) for epitaxial growth; and epitaxial crystals (20) which are formed on the major face (10) of the substrate (1) for epitaxial growth and each of which comprises a Ga-containing oxide.

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

Abstract: A semiconductor device and a method for forming a device are presented. A wafer substrate having first and second regions is provided. The second region includes an inner region of the substrate while the first region includes an outer peripheral region from an edge of the substrate towards the inner region. A protection unit is provided above the substrate. The protection unit includes a region having a total width WT defined by outer and inner rings of the protection unit. The substrate is etched to form at least a trench in the second region of the substrate. The WT of the protection unit is sufficiently wide to protect the first region of the wafer substrate such that the first region is devoid of trench.

Abstract: To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.

Abstract: A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between said first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including an lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of said first semiconductor chip area relative to said outer side wall of the lower metal layer.

Abstract: A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. The chips are disposed vertically adjacent to each other. The bottom surface of a second chip faces the bottom surface of a first chip. The pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps. The 3D-IC structure further includes a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps. The thermal via structure has an upper portion and a lower portion.

Abstract: A first bonding material layer is formed on a first substrate and a second bonding material layer is formed on a second substrate. The first and second bonding material layers include a metal. Ions are implanted into the first and second bonding material layers to induce structural damages in the in the first and second bonding material layers. The first and second substrates are bonded by forming a physical contact between the first and second bonding material layers. The structural damages in the first and second bonding material layers enhance diffusion of materials across the interface between the first and second bonding material layers to form a bonded material layer in which metal grains are present across the bonding interface, thereby providing a high adhesion strength across the first and second substrates.

Abstract: A method for making a mechanically flexible silicon substrate is disclosed. In one embodiment, the method includes providing a silicon substrate. The method further includes forming a first etch stop layer in the silicon substrate and forming a second etch stop layer in the silicon substrate. The method also includes forming one or more trenches over the first etch stop layer and the second etch stop layer. The method further includes removing the silicon substrate between the first etch stop layer and the second etch stop layer.

Abstract: In a semiconductor device having an insulating layer structure and method of manufacturing the same, a substrate including a first region and a second region may be provided. A first pattern structure may be formed on the first region of the substrate. A second pattern structure may be formed on the second region of the substrate, and have a height that is greater than the height of the first pattern structure. An insulating layer structure is formed on the first and second pattern structures and includes a protrusion near an area at which the first and second regions meet each other. An upper surface of the insulating interlayer structure is higher than a top surface of the second pattern structure. The protrusion may have at least one side surface having a staircase shape. A planarized insulating interlayer may be formed without substantial damage to the infrastructure by using the insulating layer structure in accordance with example embodiments.

Abstract: A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si4+ or Ge4+ oxidation state of the surface of the Si or Ge substrate, respectively, resulting from the presence of the oxygen monolayer represents less than 50%, preferably less than 40% and more preferably less than 30% of the sum of Si1+, Si2+, Si3+ and Si4+ oxidation states or the sum of Ge1+, Ge2+, Ge3+ and Ge4+ oxidation states, respectively, as measured by XPS.

Abstract: Provided herein are multi-layer stacks for use in extreme ultraviolet lithography tailored to achieve optimum etch contrast to shrink features and smooth the edges of features while enabling use of an optical leveling sensor with little or reduced error. The multi-layer stacks may include an atomically smooth layer with an average local roughness of less than a monolayer, and one or more underlayers, which may be between a target layer to be patterned and a photoresist. Also provided are methods of depositing multi-layer stacks for use in extreme ultraviolet lithography.

Abstract: An embedded chip package structure including a core layer, a chip, a first circuit layer and a second circuit layer is provided. The core layer includes a first surface, a second surface opposite to each other and a chip container passing through the first surface and the second surface. The chip is disposed in the chip container. The chip includes an active surface and a protrusion and a top surface of the protrusion is a part of the active surface. The first circuit layer is disposed on the first surface and electrically connected to the core layer and the chip. The first circuit layer has a through hole. The protrusion of the chip is situated within the through hole, and the top surface of the protrusion is exposed to receive an external signal. The second circuit layer is disposed on the second surface and electrically connected to the core layer.

Abstract: The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially encapsulates the die on the substrate. The seed layer is disposed on the package body and the first metal layer is disposed on the seed layer. The second metal layer is disposed on the first metal layer and the lateral surface of the substrate. The first metal layer and the second metal layer form an outer metal cap that provides thermal dissipation and electromagnetic interference (EMI) shielding.

Abstract: A semiconductor package comprises a substrate, a grounding layer, a encapsulant, a shielding layer, and a conductive element. The substrate includes a chip. The encapsulant encapsulates the grounding layer and the chip, wherein the encapsulant has an upper surface. The shielding layer is formed on the upper surface of the encapsulant. The conductive element surrounds a waveguide cavity and extends to the grounding layer. The grounding layer, the shielding layer and the conductive element together form a waveguide antenna.

Abstract: An electronic device includes a first transistor device with first contact elements, a second transistor device with second contact elements, and an electrical connection member with a first main face and a second main face opposite to the first main face. The first transistor device is disposed on the first main face of the electrical connection member and the second transistor device is disposed on the second main face of the electrical connection member. One of the first contact elements is electrically connected with one of the second contact elements by a part of the electrical connection member.

Abstract: A semiconductor device includes a lead frame, a semiconductor chip soldered to the lead frame, and a metal bar. The metal bar is arranged inside a solder layer so as to extend along one side of the semiconductor chip. When viewed in a stacking direction of the lead frame and the semiconductor chip, the metal bar is arranged so that a part of the metal bar overlaps the semiconductor chip, and the rest of the metal bar does not overlap the semiconductor chip. Then, in a section of the metal bar in a plane perpendicular to a longitudinal direction of the metal bar, an outline of the metal bar on a side of a center of the semiconductor chip is curved so as to project on the side of the center of the semiconductor chip.

Abstract: An object is to provide a semiconductor device having a plate electrode adapted to a plurality of chips, capable of being produced at low cost, and having high heat cycle property. A semiconductor device according to the present invention includes a plurality of semiconductor chips formed on a substrate, and a plate electrode connecting electrodes of the plurality of semiconductor chips. The plate electrode has half-cut portions formed by half-pressing and the raised sides of the half-cut portions are bonded with the electrodes of the semiconductor chips.

Abstract: A method and structure for encoding information on an integrated circuit chip. The method includes selecting a set of chip pads of the integrated circuit chip for encoding the information; encoding the information during a wirebonding process, the wirebonding process comprising forming ball bonds on chip pads of the integrated circuit chip and wedge bonds on leadframe fingers adjacent to one or more edges of the integrated circuit chip, the ball bonds and the wedge bonds connected by respective and integral wires; and wherein the information is encoded by varying one or more wirebonding parameters on each chip pad of the set of chip pads, the wirebonding parameters selected from the group consisting of the location of a ball bond, the diameter of a ball bond, both the location and diameter of a ball bond, the location of a wedge bond and combinations thereof.

Abstract: A resin package includes: a die pad having a main surface on which a semiconductor substrate and a matching circuit substrate is mounted; at least one lead terminal electrically connected to the semiconductor substrate and the matching circuit substrate; a thin plate fixed to at least one of the main surface of the die pad and a main surface of the at least one lead terminal; and molding resin which covers the semiconductor substrate, the matching circuit substrate, and the thin plate.

Abstract: Various aspects of the disclosure are directed to integrated circuit (IC) die leadframe packages. In accordance with one or more embodiments, a stainless steel leadframe apparatus has a polymer-based layer that adheres to both stainless steel and IC die encapsulation, with the stainless steel conducting signals/data between respective surfaces for communicating with the packaged IC die. In some embodiments, the apparatus includes the IC die adhered to the polymer-based layer via an adhesive, wire bonds coupled to the stainless steel leadframe for passing the signals/data, and an encapsulation epoxy that encapsulates the IC die and wire bonds.

Abstract: In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (MOSFET) die are on the first and the second die flags, respectively. A power control integrated circuit (IC) is stacked on top of at least one of the first or the second MOSFET die. A mold compound is encapsulating the power control IC, the first and second MOSFET die, and the first and second die flags.

Abstract: A method of wire bonding a die to a lead frame comprising mounting the die on a die attachment pad portion of a leadframe and supporting the leadframe on a support plate having a vacuum hole therein filled with porous material.

Abstract: In various embodiments a chip arrangement is provided, wherein the chip arrangement may include a chip and at least one foil attached to at least one side of the chip.

Abstract: A packaging substrate is disclosed, which includes: an encapsulant having opposite first and second surfaces; a plurality of conductive elements embedded in the encapsulant, wherein each of the conductive elements has a first conductive pad exposed from the first surface of the encapsulant and a second conductive pad exposed from the second surface of the encapsulant; and a protection layer formed on the second surface of the encapsulant and the second conductive pads so as to protect the second surface of the encapsulant from being scratched.

Abstract: A packaged semiconductor device has opposing first and second main surfaces and a sidewall connecting the first and second main surfaces. A semiconductor die is embedded in the package and has a first main surface facing the first main surface of the package and an opposing second main surface facing the second main surface of the package. Conductive leads are electrically coupled to the semiconductor die, each of which is partially embedded within the package and extends outside of the package from the package sidewall. At least one tie bar is partially embedded within the package and has an exposed segment extending outside of the package from the sidewall. A portion of the exposed segment is in contact with the first main surface of the package. The tie bar forms a heat sink to dissipate heat generated by the semiconductor die.

Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.

Abstract: A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink.

Abstract: A microelectronic package of the present description may include a microelectronic interposer having a first surface with an active surface of the at least one microelectronic device electrically attached to the microelectronic interposer first surface. A thermal interface material may be disposed on a back surface of the at least one microelectronic device. A heat spreader, having a first surface and an opposing second surface, may be in thermal contact by its first surface with the thermal interface material. A mold material may be disposed to encapsulate the microelectronic device, the thermal interface material, and the heat spreader, wherein the mold material abuts at least a portion of the microelectronic interposer first surface.

Abstract: Provided herein are electronic devices assembled with thermally insulating layers.

Abstract: Provided herein are electronic devices assembled with thermally insulating layers.

Abstract: An integrated heat spreader comprising a heat spreader frame that has a plurality of openings formed therethrough and a plurality of thermally conductive structures secured within the heat spreader frame openings. The thermally conductive structures can be formed to have various thicknesses which compensate for varying heights between at least two microelectronic devices in a multi-chip package. The thermally conductive structures can be secured in the heat spreader frame by sizing the openings and the thermally conductive structures such that the thermally conductive structures can be secured within the openings without requiring welding or adhesives.

Abstract: A molded semiconductor package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, and one or more heat conductors in the molding compound that are thermally coupled to the substrate. Advantageously, the heat conductors are mounted in the molding compound near one or more of the corners of the die. The package may also include a lid. The heat conductors produce a more uniform distribution of heat in the substrate. The package is assembled by mounting the die on the substrate, mounting the heat conductors on the substrate and applying the molding compound to the substrate, the die, and the heat conductors mounted on the substrate. For packages that use a lid, the lid is then secured to the package and coupled to the heat conductors.

Abstract: In a method for forming a sintered silver coating film, for use as a heat spreader, on a semiconductor substrate or a semiconductor package, a coating film of an ink or paste containing silver nanoparticles is formed on one surface of the semiconductor substrate or the substrate package. Further, the coating film is sintered by heating the coating film under an atmosphere of a humidity of 30% to 50% RH (30° C.) by a ventilation oven.

Abstract: A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate.

Abstract: A cooling device for a semiconductor module supplying a coolant from outside into a water jacket and cooling a semiconductor element, includes a heat sink thermally connected to the semiconductor element; a first flow channel extending from a coolant introducing port and including a guide section having an inclined surface for guiding the coolant toward one side surface of the heat sink; a second flow channel disposed parallel to the first flow channel and extending toward a coolant discharge port; a flow velocity adjusting plate disposed in the second flow channel and formed parallel to the other side surface of the heat sink at a distance therefrom; and a third flow channel formed to communicate the first flow channel and the second flow channel. The heat sink is disposed in the third flow channel.

Abstract: The present invention is an improvement in a molded semiconductor package and the method for its manufacture. The package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, a lid on the molding compound, and a heat pipe extending between the semiconductor die and the lid. Preferably, the heat pipe is formed so that it encircles the die. The package is assembled by mounting the die on the substrate, applying the molding compound to the substrate while a channel is formed in the molding compound adjacent the semiconductor die, inserting a heat pipe material in the channel, and mounting the lid on the molding compound and the heat pipe material.

Abstract: An electronic component unit includes a semiconductor package mounted on a front surface of a substrate, a heat sink including a pushing plate installed on the semiconductor package, a reinforcing plate disposed on a back surface of the substrate, and a plurality of fasteners that connect corner portions of the pushing plate and the reinforcing plate to each other, wherein the semiconductor package is pressed and fixed on the substrate by fastening the plurality of fasteners, and the reinforcing plate includes a base plate portion including a connection portion to which each of the plurality of fasteners is connected, and a pressing plate portion which is disposed at a planar central side of the base plate portion, and separably laminated on the base plate portion to press the back surface of the substrate.

Abstract: A semiconductor device includes a semiconductor chip, multiple terminals arranged in a first direction, a resin portion sealing the semiconductor chip and the terminals. The terminals are projected from a side surface of the resin portion in a second direction, and include at least one subject terminal having a first portion and a second portion. In the subject terminal, a first longitudinal end of the first portion is positioned inside of the resin portion and a second longitudinal end of the first portion is positioned outside of the resin portion, and the second portion is arranged adjacent to the first portion. Further, a length of the first portion is greater than a length of the second portion in the third direction, and a length of the first portion is smaller than a length of the second portion in the first direction.

Abstract: A packaging substrate and a fabrication method thereof are disclosed. The packaging substrate includes: a substrate body having a plurality of first and second conductive pads formed on a surface thereof; a first insulating layer formed on the surface of the substrate body and having a plurality of first and second openings for respectively exposing the first and second conductive pads; a conductive layer formed on the first and second conductive pads and the first insulating layer around peripheries of the first and second conductive pads; a plurality of first and second conductive bumps formed on the conductive layer on the first and second conductive pads, respectively; a solder layer formed on the second conductive bumps; and a plurality of conductive posts formed on the first conductive bumps and having a width different from that of the first conductive bumps. The invention improves the fabrication efficiency.

Abstract: A semiconductor unit includes a chip having left and right columns of contacts at its front surface. Interconnect pads are provided overlying the front surface of the chip and connected to at least some of the contacts as, for example, by traces or by arrangements including wire bonds. The interconnect pads alone, or the interconnect pads and some of the contacts, provide an array of external connection elements. This array includes some reversal pairs of external connection elements in which the external connection element connected to or incorporating the right contact is disposed to the left of the external connection element incorporating or connected to the left contact. Such a unit may be used in a multi-chip. The reversed connections simplify routing, particularly where corresponding contacts of two chips are to be connected to common terminals on the package substrate.

Abstract: A semiconductor apparatus includes a first wiring substrate, a second wiring substrate positioned above the first wiring substrate, multiple connection terminals provided between the first wiring substrate and the second wiring substrate and configured to electrically connect the first wiring substrate and the second wiring substrate, an electronic component provided on at least one of the first wiring substrate and the second wiring substrate. The multiple connection terminals include a signal terminal and ground terminals provided on both sides of the signal terminal. The signal terminal and the ground terminals have side surfaces that face each other. The signal terminal and the ground terminals are adjacently arranged, so that intervals between the side surfaces of the signal terminal and the ground terminals are constant from a plan view.

Abstract: Provided is a semiconductor chip that is flip-chip mounted where an inner chip pad array and an outer chip pad array, which are arranged on an inner side and an outer side of IO cells in a staggered manner, are arranged to be spaced away from each other by a predetermined gap or greater. The predetermined gap represents a gap where one via can be arranged between an inner substrate pad array and an outer substrate pad array on a substrate which faces and is connected to the inner chip pad array and the outer chip pad array. In addition, the predetermined gap represents a gap where a plated wire is interconnected and then a resist opening for etch-back can be formed. Even in a case where a space for forming an interconnection is not present between outer substrate pad arrays, interconnection characteristics of the substrate are improved.

Abstract: The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area.

Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.