Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Abstract: A voltage equal to the threshold value of a TFT (106) is held in capacitor unit (109). When a video signal is inputted from a source signal line, the voltage held in the capacitor unit is added thereto and a resultant signal is applied to a gate electrode of the TFT (106). Even when a threshold value is varied for each pixel, each threshold value is held in the capacitor unit (109) for each pixel. Thus, the influence of a variation in threshold value can be eliminated. Further, holding of the threshold value is conducted by only the capacitor unit (109) and a charge does not move at writing of a video signal so that a voltage between both electrodes is not changed. Thus, it is not influenced by a variation in capacitance value.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a phosphor layer, and a transparent film. The semiconductor layer has a first face, a second face opposite to the first face, and a light emitting layer. The p-side electrode is provided on the second face in an area including the light emitting layer. The n-side electrode is provided on the second face in an area not including the light emitting layer. The phosphor layer is provided on the first face. The phosphor layer includes a transparent resin and phosphor dispersed in the transparent resin. The transparent film is provided on the phosphor layer and has an adhesiveness lower than an adhesiveness of the transparent resin.

Abstract: In a gallium nitride based compound semiconductor light-emitting element including an active layer, the active layer includes a well layer 104 and a barrier layer 103, each of which is a semiconductor layer of which the growing plane is an m plane. The well layer 104 has a lower surface and an upper surface and has an In composition distribution in which the composition of In changes according to a distance from the lower surface in a thickness direction of the well layer 104. The In composition of the well layer 104 becomes a local minimum at a level that is defined by a certain distance from the lower surface and that portion of the well layer 104 where the In composition becomes the local minimum runs parallel to the lower surface.

Abstract: III-N material grown on a buffer on a silicon substrate includes a single crystal electrically insulating buffer positioned on a silicon substrate. The single crystal buffer includes rare earth aluminum nitride substantially crystal lattice matched to the surface of the silicon substrate, i.e. a lattice co-incidence between REAlN and Si better than a 5:4 ratio. A layer of single crystal III-N material is positioned on the surface of the buffer and substantially crystal lattice matched to the surface of the buffer.

Abstract: A method for fabricating LED devices. The method includes providing a gallium and nitrogen containing substrate member (e.g., GaN) comprising a backside surface and a front side surface. The method includes subjecting the backside surface to a polishing process, causing a backside surface to be characterized by a surface roughness, subjecting the backside surface to an anisotropic etching process exposing various crystal planes to form a plurality of pyramid-like structures distributed spatially in a non-periodic manner on the backside surface, treating the backside surface comprising the plurality of pyramid-like structures, to a plasma species, and subjecting the backside surface to a surface treatment. The method further includes forming a contact material comprising an aluminum bearing species or a titanium bearing species overlying the surface-treated backside to form a plurality of LED devices with the contact material.

Abstract: Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section 230, connected to the first electrode, containing carbon (C) such that a surface density distribution has a peak at a first interface with the first electrode.

Abstract: A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency.

Abstract: According to the invention, a semiconductor device composite structure is provided which comprises an initial substrate with discrete, integrated devices and a heat removal structure. The heat removal structure comprises: a bond layer which is attached to the initial substrate or the devices, a heat removal structure which is attached on the bond layer and which consists of a material with a specific thermal conductivity which is at least double the level of the average specific heat conductivity of the initial substrate or the devices, and one or more metallic thermal bridges which thermally connect the devices with the heat removal structure via the bond layer. The thermal bridges are designed as vertical through connections (vias) through the bond and heat removal structure. The invention furthermore relates to an associated production method.

Abstract: Integrated optical waveguides and methods for the production thereof which have a patterned upper cladding with a defined opening to allow at least one side or at least one end of a light transmissive element to be air clad. The at least one side or at least one end is, for preference, a lens structure unitary with the waveguide or a bend. Also provided is a method of fabricating an optical waveguide with a patterned cladding.

Abstract: Disclosed is a light emitting device package. The light emitting device package includes a package body having a first cavity and a second cavity; a plurality of reflective frames comprising a first reflective frame and a second reflective frame on the first cavity and the second cavity, respectively, and each of the first reflective frame and the second reflective frame comprises a bottom frame and at least two side wall frames extending from the bottom frame; and a light emitting device on the first reflective frame, wherein the first reflective frame and the second reflective frame are electrically separated from each other.

Abstract: A lighting module may include a lighting band with a band-shaped flexible substrate, wherein at least one semiconductor light source is applied to a top side of the substrate, wherein the lighting module is faced with a protective layer such that at least one emission area of the at least one semiconductor light source is exposed thereby.

Abstract: A method of producing an optoelectronic component including providing an epitaxially grown layer sequence on a growth substrate, which comprises a suitable layer for light emission; applying a metal layer to the epitaxially grown layer sequence; applying a molding support to the metal layer, the molding support including a support material with a first coefficient of thermal expansion and a fiber mesh with a second coefficient of thermal expansion functionally bonded to the support material; and detaching the growth substrate.

Abstract: This photodiode array module includes a first semiconductor substrate 2 having a first photodiode array that is sensitive to light of a first wavelength band, a second semiconductor substrate 2? having a second photodiode array that is sensitive to light of a second wavelength band, and a third semiconductor substrate 3 which is formed with a plurality of amplifiers AMP and on which the first and second semiconductor substrates 2, 2? are placed side by side without overlapping, and which connects each photodiode to the amplifier AMP via a bump. In adjacent end portions of the first semiconductor substrate 2 and the second semiconductor substrate 2?, stepped portions are formed, which thus allows performing measurement with low noise even when respective pixels are aligned successively over both substrates.

Abstract: A display panel includes a first substrate on which an electrode line and a switching element are disposed, a second substrate positioned opposite the first substrate, a seal provided between the first substrate and the second substrate, a pad electrode that vertically overlaps the seal and is electrically connected to the electrode line, and a side electrode which is connected to one end of the pad electrode and includes a portion positioned on an exterior facing side of the seal.

Abstract: Disclosed is a light-emitting element comprising a plurality of light-emitting units which are separated from one another by a charge generation layer. The light-emitting units each have a light-emitting layer which is featured by a stack of two layers. Each of the two layers includes a host material and a phosphorescent material where the phosphorescent material in one of the two layers is blue emissive while the phosphorescent material in the other of the two layers exhibits a maximum emission peak in a range from 500 nm to 700 nm. The phosphorescent material exhibiting a maximum emission peak in a range from 500 nm to 700 nm may be different from light-emitting unit to light-emitting unit. An additive may be included in at least one of the two layers so that an exciplex is formed with the host material.

Abstract: The present invention relates to an electro-optical device provided with an electrode (10). The electrode comprising an electrically conductive structure extending in a plane. The structure comprises a grid of elongated elements (12) with length L and a width dimension D in said plane. The electrically conductive structure further comprises one or more contactfields (14) having an inscribed circle with a radius of at least 2D and a circumscribed circle with a radius of at most three times L. The area occupied by the contactfields (14) is at most 20% of the area occupied by the grid of elongated elements (12).

Abstract: A lighting device comprising a light emitter chip, a reflective cup and a lumiphor positioned between the chip and the cup. Also, a lighting device comprising a light emitter chip, a wire bonded to a first surface of the chip and a lumiphor which faces a second surface of the chip. Also, a lighting device comprising a light emitter chip, and a lumiphor, a first surface of the chip facing a first region of the lumiphor, a second surface of the chip facing a second region of the lumiphor. Also, a lighting device comprising a light emitter chip and first and second lumiphors, a first surface of the chip facing the second lumiphor, a second surface of the chip facing the first lumiphor. Also, methods of making lighting devices.

Abstract: A light emitting diode (LED) device comprises a first lead frame, a second lead frame, a LED die and at least one bump. The LED die is fixed on and electrically connected to the first lead frame. The second lead frame separated from the first lead frame with a distance is connected to the LED die. The bump disposed on at least one of the first lead frame and the second lead frame to identify a gripping space for allowing an electronic element inserted or gripped therein.

Abstract: An arrangement having at least one optoelectronic semiconductor component includes a carrier element suitable for carrying the at least one optoelectronic semiconductor component. The arrangement comprises a housing body formed from a light-absorbing plastic. The housing body is arranged at the carrier element The housing body comprises an elevated region and a recessed region. An oblique flank is formed between the elevated and recessed regions. The recessed region reaches as far as the optoelectronic semiconductor component in order to reduce reflections.

Abstract: A semiconductor device has a substrate with a first and second recess formed in a surface of the substrate using a wet etch process. The second recess can have a size different from a size of the first recess. A plurality of conductive vias are formed in a surface of the first and second recesses using a dry etch process. A first conductive layer is formed over the surface of the substrate, over curved side walls of the first and second recesses, and electrically connected to the plurality of conductive vias. A first and second semiconductor die are mounted into the first and second recesses respectively. The second semiconductor die can have a size different from a size of the first semiconductor die. The first and second semiconductor die are electrically connected to the first conductive layer. An interconnect structure is electrically connected to the plurality of conductive vias.

Abstract: A light emitting component, and more particularly to a white light emitting component with high light emitting efficiency are provided. The white light emitting component with high light emitting efficiency has properties of high driving voltage, high color render index and concentrated optical density. The light emitting component includes a plurality of different light emitting diode chip groups for emitting a number of lights in different wavelength ranges and a wavelength conversion fluorescent material. A manufacturing method by stacking miniature light emitting diode chip groups to form the white light emitting component is also provided.

Abstract: A method of transferring a uniform phosphor layer on an article and a light-emitting structure having a uniform phosphor layer. The method includes disposing a surface of the article in a proximity of a carrier having the uniform phosphor layer on a surface thereon, and causing the uniform phosphor layer to be secured to the surface of the article. Therefore, the uniform phosphor layer is secured to the articles according to a contour of the article.

Abstract: In a light emission module (40), a light wavelength conversion ceramic (52) is formed in a sheet shape which converts the wavelength of the light emitted from a semiconductor light emission element (48) when emitting the light. The light wavelength conversion ceramic (52) has a tapered plane (52a) which is inclined to approach the semiconductor light emission element (48) toward the brim portion. The light wavelength conversion ceramic (52) is transparent and is arranged so that the light emission wavelength band after the conversion has an all ray permeability of 40% or above.

Abstract: A light-emitting device includes a first semiconductor layer; an active layer formed on the first semiconductor layer; a second semiconductor layer formed on the active layer; and a first pad formed on the second semiconductor layer, wherein the second semiconductor layer comprises a first region right under the first pad and a plurality of voids formed in the first region, wherein the region outside the first region in the second semiconductor layer is devoid of voids, and an area of the first region is smaller than that of the first pad in top view and the area of the first pad is smaller than that of the second semiconductor layer in top view, and the light emitted from the active layer is extracted from a top surface of the second semiconductor layer opposite the first semiconductor layer.

Abstract: Provided are a semiconductor light emitting device and a method of fabricating the same. The semiconductor light emitting device includes: a light emitting structure comprising a first conductive type semiconductor layer, an active layer under the first conductive type semiconductor layer, and a second conductive type semiconductor layer under the active layer; a reflective electrode layer under the light emitting structure, and an outer protection layer at an outer circumference of the reflective electrode layer.

Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first electrode, a second electrode, a third electrode, and a fourth electrode. The stacked structural body includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected to the first semiconductor layer. The second electrode forms an ohmic contact with the second semiconductor layer. The second electrode is translucent to light emitted from the light emitting layer. The third electrode penetrates through the second electrode and is electrically connected to the second electrode to form Shottky contact with the second semiconductor layer. The third electrode is disposed between the fourth electrode and the second semiconductor layer.

Abstract: A light source capable of solving a problem in which the etendue is increased when random polarization is converted into a specific polarization is provided. A relief structure that functions as surface plasmon excitation means for exciting a surface plasmon by a specific polarization component in a polarization direction perpendicular to a first direction in an interface between metal layer 15 and first cover layer 14 in light from emission layer 13 incident on the interface is formed at the interface. The relief structure is periodic in a second direction. Projections 21A of the relief structure are extended along the first direction.

Abstract: An improved approach is described to implement an LED-based large area display which uses an array of single color solid state lighting elements (e.g. LEDs). In some embodiments, the panel comprises an array of blue LEDs, where each pixel of the array comprises three blue LEDs. An overlay is placed over the array of blue LEDs, where the overlay comprises a printed array of phosphor portions. Each pixel on the PCB comprised of three blue LEDs is matched to a corresponding portion of the overlay having the printed phosphor portions. The printed phosphor portions of the overlay includes a number of regions of blue light excitable phosphor materials that are configured to convert, by a process of photoluminescence, blue excitation light generated by the light sources into green or red and colored light. Regions of the overlay associated with generating blue light comprise an aperture/window that allows blue light to pass through the overlay.

Abstract: Light emitting devices for light emitting diodes (LEDs) are disclosed. In one embodiment a light emitting device can include a submount and a light emission area disposed over the submount. The light emission area can include one or more light emitting diodes (LEDs), a fillet at least partially disposed about the one or more the LEDs, and filling material. The filling material can be disposed over a portion of the one or more LEDs and a portion of the fillet.

Abstract: Disclosed is a light emitting device including a conductive substrate, a first electrode layer disposed on the conductive substrate, a light emitting structure disposed on the first electrode layer, the light emitting structure including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and a second electrode layer electrically connected to the second semiconductor layer, wherein the first electrode layer includes a transparent electrode layer disposed between the conductive substrate and the first semiconductor layer, and an ohmic layer comprising a plurality of metal contact portions vertically passing through the transparent electrode layer, wherein each metal contact portion includes AuBe.

Abstract: The inventive concept provides organic light emitting diodes and methods of manufacturing an organic light emitting diode. The organic light emitting diode includes a substrate, a first electrode layer and a second electrode layer formed on the substrate, an organic light emitting layer disposed between the first electrode layer and the second electrode layer and generating light, and a scattering layer between the first electrode layer and the substrate or between the first electrode layer and the organic light emitting layer. The scattering layer scatters the light.

Abstract: An object of the invention is to provide a method for manufacturing semiconductor devices that are flexible in which elements fabricated using a comparatively low-temperature (less than 500° C.) process are separated from a substrate. After a molybdenum film is formed over a glass substrate, a molybdenum oxide film is formed over the molybdenum film, a nonmetal inorganic film and an organic compound film are stacked over the molybdenum oxide film, and elements fabricated by a comparatively low-temperature (less than 500° C.) process are formed using existing manufacturing equipment for large glass substrates, the elements are separated from the glass substrate.

Abstract: A light emitting diode package includes a first lead frame comprising a first hole cup, a second lead frame comprising a second hole cup and disposed to face the first lead frame with a gap disposed between the first lead frame and the second lead frame, a first light emitting diode chip disposed on the first hole cup, and a second light emitting diode chip disposed on the second hole cup, the first lead frame comprising a first enlarged region formed between the gap and the first hole cup, and the second lead frame comprising a second enlarged region formed between the gap and the second hole cup.

Abstract: A LED module includes a substrate, a LED chip supported on the substrate, a metal wiring installed on the substrate, the metal wiring including a mounting portion on which the LED chip is mounted, an encapsulating resin configured to cover the LED chip and the metal wiring, and a clad member configured to cover the metal wiring to expose the mounting portion, the encapsulating resin arranged to cover the clad member.

Abstract: An organic light emitting diode display includes a flexible substrate, an organic light emitting diode disposed over the flexible substrate, and an encapsulation film disposed over the flexible substrate to encapsulate the organic light emitting diode, with the organic light emitting diode interposed between the encapsulation film and the flexible substrate. A thermal conduction layer contacts the flexible substrate, wherein the thermal conduction layer faces the organic light emitting diode and the flexible substrate is interposed between the thermal conduction layer and the organic light emitting diode. A first film is disposed over the encapsulation film, and a second film is disposed over the thermal conduction layer.

Abstract: A strain release layer adjoining the active layer in a blue LED is bounded on the bottom by a first relatively-highly silicon-doped region and is also bounded on the top by a second relatively-highly silicon-doped region. The second relatively-highly silicon-doped region is a sublayer of the active layer of the LED. The first relatively-highly silicon-doped region is a sublayer of the N-type layer of the LED. The first relatively-highly silicon-doped region is also separated from the remainder of the N-type layer by an intervening sublayer that is only lightly doped with silicon. The silicon doping profile promotes current spreading and high output power (lumens/watt). The LED has a low reverse leakage current and a high ESD breakdown voltage. The strain release layer has a concentration of indium that is between 5×1019 atoms/cm3 and 5×1020 atoms/cm3, and the first and second relatively-highly silicon-doped regions have silicon concentrations that exceed 1×1018 atoms/cm3.

Abstract: A vertical power component including: a silicon substrate of a first conductivity type; on the side of a lower surface of the substrate supporting a single electrode, a lower layer of the second conductivity type; and on the side of an upper surface of the substrate supporting a conduction electrode and a gate electrode, an upper region of the second conductivity type, wherein the component periphery includes, on the lower surface side, a porous silicon insulating ring penetrating into the substrate down to a depth greater than that of the lower layer.

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Abstract: The present invention relates to a technique of semiconductor devices, and provides a semiconductor device, which uses two controllable current sources to control the electron current and the hole current of the voltage-sustaining region of a thyristor under conduction state, making the sum of the two currents from anode to cathode close to a saturated value under high voltage, thus avoiding the current crowding effect in local region and increasing the reliability of the device. Besides, it further provides a method of implementing the two current sources in the device and a method to improve the switching speed.

Abstract: An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate. The first electrostatic discharge protection device includes a buried layer formed over the substrate, the buried layer having a first conductivity type and defining an opening located over a region of the substrate, a first transistor formed over the opening of the buried layer, the first transistor having an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp, and a second transistor formed over the buried layer, the second transistor having an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp.

Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm?3 and 1×1020 cm?3, and/or the oxygen concentration within 5×1018 cm?3 and 1×1020 cm?3. The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.

Abstract: A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.

Abstract: We have observed anomalous behavior of II-VI semiconductor devices grown on certain semiconductor substrates, and have determined that the anomalous behavior is likely the result of indium atoms from the substrate migrating into the II-V layers during growth. The indium can thus become an unintended dopant in one or more of the II-VI layers grown on the substrate, particularly layers that are close to the growth substrate, and can detrimentally impact device performance. We describe a variety of semiconductor constructions and techniques effective to deplete the migrating indium within a short distance in the growth layers, or to substantially prevent indium from migrating out of the substrate, or to otherwise substantially isolate functional II-VI layers from the migrating indium, so as to maintain good device performance.

Abstract: A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins.

Abstract: Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).

Abstract: A heterojunction bipolar transistor includes a base mesa, an emitter assembly formed over the base mesa, and a base contact. The emitter assembly includes multiple circular sectors. Each circular sector is spaced apart from one another such that a sector gap is formed between radial sides of adjacent circular sectors. The base contact, which is formed over the base mesa, has a central portion and multiple radial members. Each radial member extends outward from the central portion of the base contact along a corresponding sector gap. As such, each of the circular sectors of the emitter assembly is separated by a radial member of the base contact. The number of circular sectors may vary from one embodiment to another. For example, the emitter assembly may have three, four, six, or more circular sectors.

Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Abstract: An apparatus comprises: a sensing element formed on a buried oxide layer of a substrate and providing communication between a source region and a drain region; a gate dielectric layer on the sensing element, the gate dielectric layer defining a sensing surface on the sensing element; a passive surface surrounding the sensing surface; and a compound bound to the sensing surface and not bound to the passive surface, the compound having a ligand specifically configured to preferentially bind a target molecule to be sensed. An electrolyte solution in contact with the sensing surface and the passive surface forms a top gate of the apparatus.

Abstract: A semiconductor device includes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface. A shielding member is disposed between the gate pad and the drain electrode, the shielding member being electrically connected to the source electrode.