Abstract: A semiconductor device includes a plurality of channels. Each of the channels includes a plurality of banks sequentially activated at intervals of a predetermined time in response to a refresh command; a comparator, when the refresh command is input to a corresponding channel, configured to detect whether the refresh command is applied to a contiguous channel; a delay decision unit configured to output a control signal to determine a bank active delay time in response to an output signal of the comparator; and a delay circuit configured to control an active delay time of the plurality of banks in response to an output signal of the delay decision unit.

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract: A semiconductor device may include a write control block configured to generate a plurality of write enable signals for controlling a write operation, and a write delay block configured to apply delay times to a plurality of write data which are transmitted through a write global input/output line. The semiconductor device may also include a plurality of banks configured to operate in response to the plurality of write enable signals and receive the plurality of write data, wherein the plurality of write data have different delay times according to physical positions of the plurality of banks.

Abstract: Methods and apparatuses are disclosed including an apparatus that includes a controller circuit configured to access a first subarray of a memory and to access a second subarray of the memory subsequent to accessing the first subarray but contemporaneous with precharging a portion of the first subarray by a precharge circuit associated with the first subarray.

Abstract: A memory circuit includes at least one bit cell that receives a word line, complementary bit lines and an array supply voltage and a word line suppression circuit. The word line suppression circuit includes two PFETs with their drains connected to the word line and their sources connected to the array supply voltage and an NFET with its source connected to ground and its drain connected to the word line. The NFET is inactivated before the PFETs are activated. One of the PFETs is activated before the other PFET is activated so as to control the slew rate of the word line and improve the static noise margin of the at least one bit cell.

Abstract: In at least one embodiment, a sense amplifier circuit includes a bit line, a sense amplifier output, a keeper circuit, and a noise threshold control circuit. The keeper circuit is coupled to the bit line and includes an NMOS transistor coupled between a power node and the bit line. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and configured to maintain a voltage level of the bit line. The noise threshold control circuit is connected to the sense amplifier output and the bit line. The noise threshold control circuit comprises an inverter.

Abstract: A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.

Abstract: Memory cells with read assist schemes and methods of use are provided. The memory includes a plurality of rows and columns, each of which include a memory cell having a pull-down device. The memory further includes at least one boost circuit connected to each of the memory cells and which provides a negative boost signal to the pull-down devices during read access.

Abstract: A semiconductor memory device includes a pipe channel layer formed on a semiconductor substrate, a first channel layer, a second channel layer and a third channel layer, connected with the pipe channel layer, first conductive layers stacked while surrounding the first channel layer, second conductive layers stacked while surrounding the second channel layer, and third conductive layers stacked while surrounding the third channel layer, wherein the first to third conductive layers are separately controlled.

Abstract: Disclosed herein is a resistive switching device having an amorphous layer comprised of an insulating silicon-containing material and a conducting material. The amorphous layer may be disposed between two or more electrodes and be capable of switching between at least two resistance states. Circuits and memory devices including resistive switching devices are also disclosed, and a composition of matter involving an insulating silicon-containing material and a conducting material comprising between 5 and 40 percent by molar percentage of the composition is disclosed herein as well. Also disclosed herein are methods for switching the resistance of an amorphous material.

Abstract: A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode.

Abstract: A method for read measurement of resistive memory cells having s?2 programmable cell-states includes applying to each cell at least one initial voltage and making a measurement indicative of cell current due to the initial voltage; determining a read voltage for the cell in dependence on the measurement; applying the read voltage to the cell; making a read measurement indicative of cell current due to the read voltage; and outputting a cell-state metric dependent on the read measurement; wherein the read voltages for cells are determined in such a manner that the cell-state metric exhibits a desired property.

Abstract: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.

Abstract: A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.

Abstract: A semiconductor device includes a memory cell array including a plurality of first and second memory cells each comprising a variable resistance element that establishes an electrical resistance that changes in response to an application of a write voltage after a forming voltage has been applied, the first memory cell to which the forming voltage is applied, and the second memory cell to which the forming voltage is not applied, and the second memory cell being configured to store one of first and second logic values constituting first information, the first and second logic values being different from each other.

Abstract: According to one embodiment, a plurality of first wirings is disposed in first and second directions crossing each other and extends in a third direction perpendicular to the first and second directions. Second wirings extend in the second direction and are provided at a predetermined interval in the third direction of the first wirings. The first wiring includes a metal plug layer and a barrier metal film. A standard electrode potential of a metal that forms the barrier metal film is higher than a standard electrode potential of a metal that forms the variable resistive layer.

Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.

Abstract: A nonvolatile memory cell string includes two or more cell devices formed in series on a wall type semiconductor protruded from a semiconductor substrate with a predetermined length along one direction to form the cell string. One end of the cell string is electrically connected to outside through a string selection transistor formed on one end of the wall type semiconductor. The other end of the cell string is floated and not electrically connected to outside.

Abstract: A non-volatile memory device, including: a substrate; a plurality of string stacks disposed over the substrate, each string stack including a long axis and a short axis in a plane parallel to the substrate, the long axis extending along a y-direction and the short axis extending along an x-direction, each string stack including a plurality of strings being stacked in a direction vertical to the substrate and having a first end and a second end at different locations in the y-direction, the plurality of string stacks including a first and a second set of string stacks, at least some of the string stacks of the first set of string stacks being offset along the x-direction from at least some of the string stacks of the second set of string stacks.

Abstract: When applying a programming voltage at one end of a word line of a non-volatile memory circuit, if the word line has a large RC constant the far end of the word line will not rise as fast as the driven end, which can adversely affect device performance. To more quickly raise the voltage on the selected word line, a voltage kick is applied to non-selected word lines, such as dummy word lines, by way of a non-selected sub-block of the selected block. The channel of NAND strings in the non-selected sub-block is used to transfer the kick to the far end of the selected word line of the selected sub-block.

Abstract: Provided is a flash memory integrated circuit with a compression codec. The flash memory integrated circuit may simultaneously include a memory block and a compression codec circuit. The compression codec circuit may compress input data. A controller circuit may store the compressed input data in at least one page that is included in the memory block. Through this, it is possible to enhance a usage efficiency of a flash memory.

Abstract: Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array including a plurality of strings, wherein each of the plurality of strings includes a first memory cell group, and a second memory cell group and peripheral circuits configured to generate a first precharge voltage applied to the first memory cell group and a second precharge voltage applied to the second memory cell group when a channel precharge operation is performed during a program operation, and generate a program voltage to apply the program voltage to the memory cell array when a program voltage application is performed.

Abstract: In a three-dimensional stacked non-volatile memory device, a short circuit in a select gate layer is detected and prevented. A short circuit may occur when charges which are accumulated in select gate lines due to plasma etching, discharge through a remaining portion of the select gate layer in a short circuit path when the select gate lines are driven. To detect a short circuit, during a testing phase, an increasing bias is applied is applied to the remaining portion while a current is measured. An increase in the current above a threshold indicates that the bias has exceed a breakdown voltage of a short circuit path. A value of the bias at this time is recorded as an optimal bias. During subsequent operations involving select gate transistors or memory cells, such as programming, erasing or reading, the optimal bias is applied when the select gate lines are driven to prevent a current flow through the short circuit.

Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

Abstract: The present disclosure is related to an adjusted read for a partially programmed block. A number of methods can include receiving a read request including a logical address, translating the logical address to a physical address and simultaneously determining whether a physical address associated with the read request is in a block that is partially programmed, and in response to the physical address being in the block that is partially programmed, adjusting a read signal level based on a proximity of the physical address to a last written page in the block.

Abstract: Methods for operating a non-volatile storage system in which cross-coupling effects are utilized to extend the effective threshold voltage window of a memory cell and to embed additional information within the extended threshold voltage window are described. In some cases, additional information may be embedded within a memory cell storing the highest programming state if the memory cell is in a high boosting environment by splitting the highest programming state into two substates and programming the memory cell to one of the two substates based on the additional information. A memory cell may be in a high boosting environment if its neighboring memory cells are in a high programmed state. Additional information may also be embedded within a memory cell storing the lowest programming state if the memory cell is in a low boosting environment. The additional information may include error correction information.

Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell, a voltage generator configured to output a first voltage and a second voltage, and a controller. The controller executes a write operation, which includes a first read operation, a program operation, and a verify operation. The controller executes the first read operation before the program operation and the verify operation. The controller executes the first read operation by applying the first voltage to a gate of the memory cell. The controller executes an erase verify operation by applying the second voltage to the gate of the memory cell. The first voltage is higher than the second voltage.

Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.

Abstract: A semiconductor device and a method of operating the same. The semiconductor device may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings extending substantially perpendicular to a semiconductor substrate, the plurality of cell strings sharing a plurality of bit lines, and a plurality of source lines respectively connected to the cell strings and word lines. Page buffers, connected to the bit lines, may store data. A selection switch portion may selectively transmit a voltage corresponding to data stored in the page buffers, and voltages supplied from an external source, to the bit lines and the source lines during the program operation, the read operation and the erase operation. A control circuit may control the page buffers and the selection switch portion.

Abstract: A semiconductor memory device includes at least one cell string to include a plurality of dummy memory cells and a plurality of memory cells connected in series between the plurality of dummy memory cells; and the peripheral circuit to control the at least one cell string so that a first type of data represented by a first number of bits is stored in at least one of the dummy memory cells and a second type of data represented by a second number of bits, the second number smaller than the first number, is stored in at least two of the plurality of memory cells.

Abstract: Reducing peak current and/or power consumption during verify of a non-volatile memory is disclosed. During a program verify, only memory cells in a first physical segment of the selected word line are verified during an initial program loop; memory cells in a different physical segment of the word line are locked out and not verified. The locked out memory cells may be slower to program. During a later program loop, memory cells in all physical segments are program verified. Locked out strings do not conduct a significant current during verify, thus reducing current/power consumption.

Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Abstract: A programmable resistive device cell using at least one MOS device as selector can be programmed or read by turning on a source junction diode of the MOS or a channel of the MOS. A programmable resistive device cell can include at least one programmable resistive element and at least one MOS device. The programmable resistive element can be coupled to a first supply voltage line. The MOS can have a source coupled to the programmable resistive element, a bulk coupled to a drain, a drain coupled to a second supply voltage line, and a gate coupled to a third supply voltage line. The programmable resistive element can be configured to be programmable or readable by applying voltages to the first, second, and/or third supply voltage lines to turn on the source junction of the MOS and/or to turn on the channel of the MOS.

Abstract: A system and method of writing data to a memory block includes receiving user data in a memory controller, the user data to be written to the memory block. The user data is first written to a buffer in the memory controller. A screening pattern is written to at least one screening column in the memory block and a first memory integrity test is performed. The first memory integrity test includes reading screening column data from the at least one screening column and comparing the screening column data read from the at least one screening column to the screening pattern. The user data is written to at least one user data column in the memory block when the screening column data read from the at least one screening column matches the screening pattern in the first memory integrity test.

Abstract: A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold programming values for the generic programmable address scrambler.

Abstract: Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include a static random access memory (SRAM) cell, read/write/decoder (R/W/decoder) circuitry to provide a nominal word line (WL) voltage and a nominal bit line (BL) voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed.

Abstract: A semiconductor device includes a compression block configured to compare and compress data of a plurality of core array blocks, by a unit of a group; a combination block configured to combine outputs of the compression block and output compression data; and a control block configured to latch the compression data and output latched data, and drive the latched data and the compression data and output resultant data to a first data line and a second data line.

Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.

Abstract: An instruction to read at least a portion of a superblock is received where the superblock is stored on at least a first solid state storage die. It is determined if adjusted threshold information, associated with the first solid state storage die and the superblock, is stored. If it is determined that adjusted threshold information is not stored, then an adjusted threshold is determined and a read is performed on the first solid state storage die using the determined adjusted threshold. If it is determined that adjusted threshold information is stored, then a read is performed on the first solid state storage die using the stored adjusted threshold information.

Abstract: A memory management method, a memory control circuit unit using the method, and a memory storage apparatus using the method are provided. The memory management method includes determining whether a use count of the rewritable non-volatile memory module is greater than a use count threshold; based on a result of the determination, sorting each physical erasing unit in a spare area in an ascending manner according to an erasing count of each physical erasing unit in the spare area or according to the number of maximum bit errors of the physical erasing units in the spare area, so as to form a plurality of sorted physical erasing units; and selecting the foremost physical erasing unit from the spare area to write data according to the sorted physical erasing units. By applying the memory management method, the lifespan of the rewritable non-volatile memory module may be effectively prolonged.

Abstract: Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

Abstract: Disclosed embodiments include nuclear fission reactor cores, nuclear fission reactors, methods of operating a nuclear fission reactor, and methods of managing excess reactivity in a nuclear fission reactor.

Abstract: A device for tensioning a preform made from interlaced fibers is applied to tension the preform used in a process for fabricating a part made from a ceramic matrix composite material. During this process, the preform is tensioned before and during its densification using the tensioning device (100), which comprises a main body (2), a first assembly element (3) and a second assembly element (4) and a control rod, rotation of the control rod causing translation of the second assembly element, separation of the first and second assembly elements from each other and tensioning of the preform along the longitudinal direction.

Abstract: The present invention relates to a method for detecting the drop of a cluster in a pressurized-water nuclear reactor, comprising the steps of: detecting a negative time derivative of the neutron flux, and comparing the absolute value of said time derivative to a first threshold value (S1); triggering a time delay (?T) if said absolute value is greater than said threshold value (S1); detecting a positive time derivative of said neutron flux, and comparing the absolute value of said time-derivative to a second threshold value (S2); and triggering the emergency shutdown of the reactor if the absolute value of said positive time derivative of said flux becomes greater than said second threshold value (S2) during said time delay (?T).

Abstract: To use 99mTc as a raw material for a radioactive medicine, a very small amount of 99mTc in the high concentration Mo(99Mo) solution is purified and recovered with high yield without contamination of 99Mo. 99mTc with high purity is recovered by forming a high concentration Mo(99Mo) solution which contains radionuclides 99Mo which is the parent nuclide of 99mTc used for the radioactive medicine and the raw material for its labeled compound, forming a high concentration Mo(99Mo) solution which contains radionuclides 99Mo and 99mTc by generating 99mTc to a radioactive-equilibrium state, getting 99mTc in the high concentration Mo(99Mo) solution adsorbed to activated carbon selectively by feeding the solution to an adsorption column which has activated carbon, and undergoing desorption and purification treatment of 99mTc with a desorbent from the activated carbon to which 99mTc is adsorbed.

Abstract: A charged-particle beam drawing method includes: storing a plurality of time interval patterns defining time intervals for performing a diagnosis of a drift amount of charged-particle beam; drawing a predetermined drawing pattern on a sample by irradiating the beam on the sample; receiving first event information including occurrence of event and type of event; acquiring region information specifying a region being drawn by the beam; selecting a specific time interval pattern from the plurality of time interval patterns based on the type of the event of the first event information and the region information; diagnosing the drift amount of the beam based on the specific time interval pattern, until second event information is received, the second event information includes occurrence of event and type of event; and drawing a predetermined drawing pattern on the sample while performing a drift correction of the charged-particle beam, based on the diagnosing.

Abstract: This invention relates to a copper thick film paste composition paste comprising copper powder, a Pb-free, Bi-free and Cd-free borosilicate glass frit, a component selected from the group consisting of ruthenium-based powder, copper oxide powder and mixtures thereof and an organic vehicle. The invention also provides methods of using the copper thick film paste composition to make a copper conductor on a substrate. Typical substrates are selected from the group consisting of aluminum nitride, aluminum oxide and silicon nitride.

Abstract: A preparing method of a reduced graphene oxide film, a reduced graphene oxide film prepared by the preparing method, a graphene electrode including the reduced graphene oxide film, an organic thin film transistor including the graphene electrode, and an antistatic film including the reduced graphene oxide film are provided. The method for preparing a reduced graphene oxide film comprises: coating a graphene oxide-dispersed solution on a substrate to form a graphene oxide thin film; and reducing the graphene oxide thin film using a chemical reduction method and a pressure-assisted thermal reduction method to form a reduced graphene oxide film.

Abstract: The invention provides a process for producing a transparent conducting film, which film comprises a doped zinc oxide wherein the dopant comprises Si, which process comprises: disposing a composition which is a liquid composition or a gel composition onto a substrate, wherein the composition comprises Zn and Si; and heating said substrate. The invention further provides transparent conducting films obtainable by the process of the invention, including transparent conducting films which comprise a doped zinc oxide wherein the dopant comprises Si, and wherein the film covers a surface area equal to or greater than 0.01 m2. The invention also provides a coated substrate, which substrate comprises a surface, which surface is coated with a transparent conducting film, wherein the film comprises a doped zinc oxide wherein the dopant comprises Si, and wherein the area of said surface which is coated with said film is equal to or greater than 0.01 m2.

Abstract: A main object of the present invention is to provide a practical slurry having a polar solvent as the dispersion medium for a sulfide solid electrolyte material. The present invention solves the above-mentioned problem by providing a slurry having: a sulfide solid electrolyte material, and a dispersion medium having at least one selected from the group consisting of tertiary amine; ether; thiol; ester having a functional group of a 3 or more carbon number bonded with a carbon atom of an ester bonding and a functional group of a 4 or more carbon number bonded with an oxygen atom of the ester bonding; and ester having a benzene ring bonded with a carbon atom of an ester bonding.