Abstract: A relay fault detection and correction system includes a signal detector structured to measure primary and secondary signals, and generates a fault output signal if the signals appear to be unterminated due to a relay not connecting the signals to the loads. A cycle circuit is structured to cause a relay controller to cycle a potentially under-performing relay between its states a number of times after the signal detector generates the fault output.

Abstract: An electrical switch is disclosed and includes a tensioning lever which, in the switched-on state of the switch, assumes a tensioning lever position tensioned by spring tension, and a locking device which can lock the tensioning lever into the tensioned tensioning lever position. In accordance with an embodiment of the invention, the locking device includes a rocker lever, which is attached rotatably to the tensioning lever around a rotary bearing, and a pawl, pivotable around a pivot point, which rests in the locked state on the rocker lever and in this way prevents the pivoting of the tensioning lever and—after an unlocking of the locking device—pivots away from the rocker lever and, in doing so, turns or can at least turn the rocker lever.

Abstract: An electrode for dielectric barrier discharge treatment of a substrate includes a tubular housing that is made of electrically insulating material and has a bottom wall facing the substrate, two side walls extending away from the substrate, and a top wall connecting the distal ends of the side walls. The electrode further includes an electrically conductive electrode member disposed inside the housing and having a plate that engages an internal surface of the bottom wall of the housing. The electrode has two wings formed in one piece with the plate and engaging internal surfaces of the side walls of the housing.

Abstract: One embodiment provides a tungsten wire containing 1 to 10% by mass of rhenium, the wire having a point indicating a 2% elongation within a quadrangle formed by joining points with straight lines, where the values of x and y are point (20, 75), point (20, 87), point (90, 75), and point (90, 58), in this order; wherein the wire diameter of the tungsten wire is represented by x ?m, and the elongation of the tungsten wire is 2% after electrically heating with an electrical current which is a ratio of y % to the fusion current (FC) at the wire diameter x ?m, and wherein a semi-logarithmic system of coordinates is expressed by a horizontal axis using a logarithmic scale of the wire diameter x and a vertical axis using a normal scale of ratio y to the fusion current.

Abstract: At the time of temporary firing for fixing a glass layer 3 to a glass member 4, the glass layer 3 is irradiated with laser light L2 through the glass member 4 from the glass member 4 side. This fully heats a part of the glass layer 3 on the glass member 4 side and thus can improve the adhesion of the glass layer 3 to the glass member 4. Further, even when irradiated with the laser light L2 at such a laser power as to melt both edge parts of the glass layer 3, the part of the glass layer 3 on the side opposite from the glass member 4 (i.e., the part of the glass layer 3 fused to the other glass member) is prevented from being crystallized by excess heat input, whereby the fusing state of the glass layer 3 with respect to the other glass member can be made uniform.

Abstract: A magnetron has an anode body (1) and including a ceramic sleeve (7). In higher power generators, stray radiation is emitted from this sleeve in addition to the main power launched from the antenna into the waveguide (2), and RF absorbing material is provided. Such absorbers, however, tend to be frequency-selective, and can overheat. According to the invention, a non-metallic jacket (13) containing a dielectric liquid such as water surrounds the sleeve. This provides absorption over a broad band of frequencies, and it is easy to make the jacket have a sufficiently high thermal capacity, for example, by arranging a flow of liquid through it.

Abstract: The present invention discloses a system and method for generating a beam of fast ions. The system comprising: a target substrate having a patterned surface, a pattern comprising nanoscale pattern features oriented substantially uniformly along a common axis; and; a beam unit adapted for receiving a high power coherent electromagnetic radiation beam and providing an electromagnetic radiation beam having a main pulse and a pre-pulse and focusing it onto said patterned surface of the target substrate to cause interaction between said radiation beam and said substrate enabling creation of fast ions.

Abstract: An ion implantation system provides ions to a workpiece positioned in a vacuum environment of a process chamber on a cooled chuck. A pre-chill station within the process chamber has a chilled workpiece support configured to cool the workpiece to a first temperature, and a post-heat station within the process chamber, has a heated workpiece support configured to heat the workpiece to a second temperature. The first temperature is lower than a process temperature, and the second temperature is greater than an external temperature. A workpiece transfer arm is further configured to concurrently transfer two or more workpieces between two or more of the chuck, a load lock chamber, the pre-chill station, and the post-heat station.

Abstract: A sample observation method uses a charged particle beam apparatus comprising a charged particle optical column irradiating a charged particle beam, a vacuum chamber, and a sample chamber being capable of storing a sample. The method includes maintaining a pressure of the sample chamber higher than that of the vacuum chamber by a thin film which permits the charged particle beam to be transmitted, determining a relation between a height of a lower surface of the thin film and a height of a lower end of a lens barrel of an optical microscope, measuring a distance between the sample and the lens barrel, and setting a distance between the sample and thin film based on the relation and the distance.

Abstract: There is provided a defect inspection apparatus including: an electron scanning unit configured to scan a surface of a sample with an electron beam; a plurality of detectors arranged around an optical axis of the electron beam and configured to detect electrons emitted from the surface of the sample by scanning the electron beam; a signal processing unit configured to generate image data of the surface of the sample based on detection signals from the detectors; an analysis unit configured to detect a defect due to irregularities of the surface of the sample based on the image data; and a control unit configured to control a scanning speed of the electron beam depending on the type of the sample.

Abstract: Measurements of line roughness are separated into groups depending upon pre-layers. Image data collected from similar pre-layer types are considered together in order to separate effects of line roughness from distortion of measurements caused by the pre-layers. The resulting line roughness measurements are used to estimate an aspect of line quality.

Abstract: An automatic setting method of an observation condition to facilitate analysis of an image and a sample observation method by automatic setting in an observation method of a structure of a sample by the electronic microscope and an electronic microscope having an automatic setting function are provided. The method includes a step of irradiating a fixed position in an observation region with an intermittent pulsed electron beam; a step of detecting a time change of an emission electron from the sample by the intermittent electron beam; and a step of setting the observation condition of the electronic microscope from the time change of the emission electron.

Abstract: A method and system for performing gas cluster ion beam (GCIB) etch processing of various materials is described. In particular, the GCIB etch processing includes using one or more molecular beams to optimize pressure at localized regions of the ion beam.

Abstract: An ion implantation apparatus includes a beam scanning unit and a beam parallelizing unit arranged downstream thereof. The beam scanning unit has a scan origin in a central part of the scanning unit on a central axis of an incident ion beam. The beam parallelizing unit has a focal point of a parallelizing lens at the scan origin. The ion implantation apparatus is configured such that a focal position of the incident beam into the scanning unit is located upstream of the scan origin along the central axis of the incident beam. The focal position of the incident beam into the scanning unit is adjusted to be at a position upstream of the scan origin along the central axis of the incident beam such that a divergence phenomenon caused by the space charge effect in an exiting ion beam from the parallelizing unit is compensated.

Abstract: A charged particle beam writing apparatus according to one aspect of the present invention includes an emission unit to emit a charged particle beam, an electron lens to converge the charged particle beam, a blanking deflector, arranged backward of the electron lens with respect to a direction of an optical axis, to deflect the charged particle beam in the case of performing a blanking control of switching between beam-on and beam-off, a blanking aperture member, arranged backward of the blanking deflector with respect to the direction of the optical axis, to block the charged particle beam having been deflected to be in a beam-off state, and a magnet coil, arranged in a center height position of the blanking deflector, to deflect the charged particle beam.

Abstract: A drawing apparatus includes: plural charged particle optical systems arrayed at a pitch in a first direction, each configured to irradiate a substrate with charged particle beams; a stage configured to hold the substrate and be moved relative to the charged particle optical systems in a second direction orthogonal to the first direction; and a controller configured to determine charged particle beams for the drawing with respect to each charged particle optical system so as to satisfy a relation given by SW=Pc/?=Ps/(? where Ps is an array pitch of shot regions in the first direction, SW is a width, in the first direction, of each drawing region by each charged particle optical system, Pc be an array pitch of drawing regions in the first direction, and ? and ? are natural numbers.

Abstract: Ion sources, systems and methods are disclosed.

Abstract: In the plasma processing apparatus 10, a processing space S is formed between a susceptor 12 and an upper electrode 13 facing the susceptor 12. The plasma processing apparatus 10 includes a magnetic field generating unit provided at a side of the upper electrode 13 opposite to the processing space S. The magnetic field generating unit includes a magnetic force line generating unit 27 having a pair of annular magnet rows 27a and 27b. The annular magnet rows 27a and 27b are provided at the side of the upper electrode 13 opposite to the processing space S and arranged concentrically when viewed from the top. In the magnetic force line generating unit 27, an angle ?1 formed by axial lines of magnets of the annular magnet rows 27a and 27b is set to be in a range of about 0°<?1?180°.

Abstract: An inhalable cold plasma mask device for generation of a breathable cold plasma for delivery to a patient. A biocompatible gas is received in a dielectric barrier discharge (DBD) device that is energized by an electrode that receives energy from a pulsed source. The DBD device can be grounded by a grounding structure. A grounding screen can be used prior to inhalation of the cold plasma. The inhalable cold plasma mask device includes the use of a single-layer or a two-layer approach to its construction. The inhalable cold plasma mask device can have one or two DBD devices. Such a device and associated method can be used to treat upper respiratory tract infections, as well as reducing inflammation, sinus and esophageal polyps in both size and frequency of occurrence.

Abstract: Methods for processing a substrate in a plasma processing chamber employing a plurality of RF power supplies. The method includes pulsing at a first pulsing frequency a first RF power supply to deliver a first RF signal between a high power state and a low power state. The method further includes switching the RF frequency of a second RF signal output by a second RF power supply between a first predefined RF frequency and a second RF frequency responsive to values of a measurable chamber parameter. The first RF frequency and the second RF frequencies and the thresholds for switching were learned in advance during a learning phase while the first RF signal pulses between the high power state and low power state at a second RF frequency lower than the first RF frequency and while the second RF power supply operates in different modes.

Abstract: According to one embodiment, a gas supply member is provided with a gas supply passage including a gas flow channel with a first diameter, and an exhaust port connected to one end portion of the gas flow channel and provided to a surface of a downstream side of the gas supply member. An yttria-containing film is formed on a surface constituting the exhaust port and the surface of the downstream side of the gas supply member. At least a part of the surface constituting the exhaust port is formed with a curved surface.

Abstract: It is possible to prevent processing gases from being mixed when alternately supplying the processing gases while alternately switching the processing gases and to suppressed a transient phenomenon more efficiently as compared to conventional cases. When supplying at least two kinds of processing gases (e.g., a C4F6 gas and a C4F8 gas) into a processing chamber while alternately switching the at least two kinds of processing gases during a plasma process on a wafer, the supply of each processing gas can be alternately turned on and off by alternately setting an instruction flow rate of a mass flow controller to be a predetermined flow rate and a zero flow rate while a downstream opening/closing valve provided at a downstream side of the mass flow controller is open.

Abstract: Systems and methods are used to analyze a sample using variable detection scan resolutions. A tandem mass spectrometer is instructed to perform at least two scans of a sample with different detection scan resolutions using a processor. The tandem mass spectrometer includes a mass analyzer that allows variable detection scan resolutions. The selection of the different detection scan resolutions can be based on one or more properties of sample compounds. The properties may include a sample compound molecular weight distribution that is calculated from a molecular weight distribution of expected compounds or is determined from a list of molecular weights for one or more known compounds. The tandem mass spectrometer can also be instructed to perform an analysis of the sample before instructing the tandem mass spectrometer to perform the at least two scans of the sample.

Abstract: A mass spectrometer system an ion source configured to produce ions and a non-metallic capillary configured to receive at least a portion of the ions from the ion source. The capillary includes an elongated body and multiple bores traversing the elongated body in a longitudinal direction. The bores transport the received ions through the capillary toward a mass analyzer of the mass spectrometer system for detection.

Abstract: A detection device including an ionization region, an ion gate comprising two electrodes, an ion modifier comprising two electrodes, a drift chamber and a collector. The ion gate and ion modifier are combined so the ion gate is one of the ion modifier electrodes.

Abstract: The present invention uses an AC voltage instead of DC voltage on an ion gate to filter/selectively pass ions. The ions that pass through the AC ion gate can be further separated in a spectrometric instrument. An ion mobility spectrometer using the AC ion gate can achieve better gating performance. For a time of flight ion mobility spectrometer with an AC ion gate, a narrow pulse of selected ions can be passed into a drift tube where they are separated based on their low field ion mobility. Moreover, when the AC voltage at the AC ion gate has a waveform as used for differential ion mobility spectrometry, the time of flight ion mobility spectrometer is converted into a two dimensional separation spectrometer, where ions are first separated based on their high field ion mobility and then further separated based on their low field ion mobility.

Abstract: An ion guide includes a plurality of curved electrodes and an ion deflecting device. The electrodes are arranged in parallel with each other and with a central curved axis, the curved central axis being co-extensive with an arc of a circular section having a radius of curvature, each electrode being radially spaced from the curved central axis, wherein the plurality of electrodes define a curved ion guide region arranged about the curved central axis and between opposing pairs of the electrodes. The ion deflecting device may include a device for applying a DC electric field to two or more of the electrodes in a radial direction. The ion deflecting device may include a pair of curved, parallel ion deflecting electrodes, which are in addition to curved electrodes utilized for applying an RF ion guiding field.

Abstract: A sample preparation and analysis system. The system includes a housing with a sample preparation station and a sample analysis station positioned within the housing. The sample analysis station is spaced away from the sample preparation station. A transport assembly is configured to move at least one sample within the housing and between the sample preparation station and the sample analysis station.

Abstract: Instead of sealing together the upper and lower panels of a display device with only a solid-filled sealing material, a vacuum region is provided in suction-force-applying communication with at least one of the panels and anchored to the other so as to pull the panels together due to pressure difference with and ambient atmosphere. The display device includes: a vacuum region defined by a pair of spaced apart, resilient and gas impermeable support barriers formed to integrally extend from at least one of the upper and lower panels of the display device and having the other end in vacuum region closing contact with the other display panel where the vacuum region is positioned in a peripheral area of the display device.

Abstract: The present invention is directed to devices and methods for generating light with plasma lamps. More particularly, the present invention provides plasma lamps driven by a radio-frequency source without the use of electrodes inside the bulb and related methods. In a specific embodiment, a coaxial type coupling module is used to drive an electrodeless bulb. Merely by way of example, such plasma lamps can be applied to applications such as stadiums, security, parking lots, military and defense, street lighting, large and small buildings, vehicle headlamps, aircraft landing, bridges, warehouses, UV water treatment, agriculture, architectural lighting, stage lighting, medical illumination, microscopes, projectors and displays, any combination of these, and the like.

Abstract: A safety net for a light bulb changer including a base. a circular aperture continuously disposed from a top surface of the base to a bottom surface of the base, a conical semi-rigid net having a bottom end attached to the top surface of the base, a circular support frame continuously disposed on a top edge of the net, a plurality of spaced apart support columns vertically disposed along an exterior surface of the net, a conical cover continuously disposed atop an outer edge of each of the plurality of support columns, a slot disposed through a side surface of the base, and a wingnut threadably engaged in the slot. A bottom end of a rod of a light bulb changer is slidably disposed through the aperture.

Abstract: A semiconductor device and a method for forming a device are presented. A wafer substrate having first and second regions is provided. The second region includes an inner region of the substrate while the first region includes an outer peripheral region from an edge of the substrate towards the inner region. A protection unit is provided above the substrate. The protection unit includes a region having a total width WT defined by outer and inner rings of the protection unit. The substrate is etched to form at least a trench in the second region of the substrate. The WT of the protection unit is sufficiently wide to protect the first region of the wafer substrate such that the first region is devoid of trench.

Abstract: According to various embodiments, a method for processing a wafer may include: forming at least one hollow chamber and a support structure within the wafer, the at least one hollow chamber defining a cap region of the carrier located above the at least one hollow chamber and a bottom region of the carrier located below the at least one hollow chamber and an edge region surrounding the cap region of the carrier, wherein a surface area of the cap region is greater than a surface area of the edge region, and wherein the cap region is connected to the bottom region by the support structure; removing the cap region in one piece from the bottom region and the edge region.

Abstract: A substrate can be appropriately oxidized, while oxidation of the substrate can be suppressed. The present invention includes a step of generating mixed plasma by causing a mixed gas of hydrogen (H2) gas and oxygen (O2) or oxygen-containing gas supplied to a processing chamber to form a plasma discharge, and processing the starting substrate by the mixed plasma; and a step of generating hydrogen plasma by causing hydrogen (H2) gas supplied to the processing chamber to form a plasma discharge, and processing the substrate by the hydrogen plasma.

Abstract: A method for making semiconductor devices may include forming a phosphosilicate glass (PSG) layer on a semiconductor wafer, with the PSG layer having a phosphine residual surface portion. The method may further include exposing the phosphine residual surface portion to a reactant plasma to integrate at least some of the phosphine residual surface portion into the PSG layer. The method may additionally include forming a mask layer on the PSG layer after the exposing.

Abstract: Disclosed herein are methods of depositing layers of material on multiple semiconductor substrates at multiple processing stations within one or more reaction chambers. The methods may include dosing a first substrate with film precursor at a first processing station and dosing a second substrate with film precursor at a second processing station with precursor flowing from a common source, wherein the timing of said dosing is staggered such that the first substrate is dosed during a first dosing phase during which the second substrate is not substantially dosed, and the second substrate is dosed during a second dosing phase during which the first substrate is not substantially dosed. Also disclosed herein are apparatuses having a plurality of processing stations contained within one or more reaction chambers and a controller with machine-readable instructions for staggering the dosing of first and second substrates at first and second processing stations.

Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.

Abstract: The temperature of a substrate is elevated rapidly while improving the temperature uniformity of the substrate. The substrate is loaded into a process chamber, the loaded substrate is supported on a first substrate support unit, a gas is supplied to the process chamber, the temperature of the substrate supported on the first substrate support unit is elevated in a state of increasing the pressure in the process chamber to higher than the pressure during loading of the substrate or in a state of increasing the pressure in the process chamber to higher than the pressure during processing for the surface of the substrate, the substrate supported on the first substrate support unit is transferred to the second substrate support unit and supported thereon after lapse of a predetermined time, and the surface of substrate is processed while heating the substrate supported on the second substrate support unit.

Abstract: Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane or a borane agent are provided. In some embodiments a film comprising titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that comprises titanium and at least one halide ligand, a second source chemical comprising metal and carbon, wherein the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, wherein the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. In some embodiments treatment forms a capping layer on the metal carbide film.

Abstract: A (000-1) C-plane of an n? type silicon carbide substrate having an off-angle ? in a <11-20> direction is defined as a principal plane, and a periphery of a portion of this principal surface layer defined as an alignment mark is selectively removed to leave the convex-shaped alignment mark. The alignment mark has a cross-like plane shape such that two rectangles having longitudinal dimensions tilted by 45 degrees relative to the <11-20> direction are orthogonal to each other. When a film thickness of a p? type epitaxial layer is Y; a width of the alignment mark parallel to the principal surface of the n? type silicon carbide substrate is X; and an off-angle of the n? type silicon carbide substrate is ?, an epitaxial layer is formed on an upper surface of the alignment mark such that Y?X·tan ? is satisfied.

Abstract: A method of growing III-N material on a silicon substrate includes the steps of epitaxially growing a single crystal rare earth oxide on a silicon substrate, epitaxially growing a single crystal rare earth nitride on the single crystal rare earth oxide, and epitaxially growing a layer of single crystal III-N material on the single crystal rare earth nitride.

Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

Abstract: Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.

Abstract: A metal chloride gas generator includes: a tube reactor including a receiving section for receiving a metal on an upstream side, and a growing section in which a growth substrate is placed on a downstream side; a gas inlet pipe arranged to extend from an upstream end with a gas inlet via the receiving section to the growing section, for introducing a gas from the upstream end to supply the gas to the receiving section, and supplying a metal chloride gas produced by a reaction between the gas and the metal in the receiving section to the growing section; and a heat shield plate placed in the reactor to thermally shield the upstream end from the growing section. The gas inlet pipe is bent between the upstream end and the heat shield plate.

Abstract: A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.

Abstract: A method of thin film formation includes: preparing a substrate; forming a thin film above the substrate; and crystallizing the thin film by irradiating the thin film with a light beam, in which the crystallizing includes steps of: crystallizing the thin film in a first region into a first crystalline thin film by irradiating the first region while scanning a first light beam relative to the substrate, the first region including at least one of: edge portions of the substrate; and a region through which a cutting line passes when the substrate is cut; and subsequently crystallizing the thin film in a second region into a second crystalline thin film by irradiating at least the second region while scanning a second light beam relative to the substrate, and the thin film has a higher absorption ratio of the second light beam than that of the first crystalline thin film.

Abstract: In some embodiments, a method of forming a three dimensional NAND structure atop a substrate may include providing to a process chamber a substrate having alternating nitride layers and oxide layers or alternating polycrystalline silicon layers and oxide layers formed atop the substrate and a photoresist layer formed atop the alternating layers; etching the photoresist layer to expose at least a portion of the alternating nitride layers and oxide layers or alternating polycrystalline silicon layers and oxide layers; providing a process gas comprising sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), and oxygen (O2) to the process chamber; providing an RF power of about 4 kW to about 6 kW to an RF coil to ignite the process gas to form a plasma; and etching through a desired number of the alternating layers to form a feature of a NAND structure.

Abstract: The use of surfactants A, the 1% by weight aqueous solutions of which exhibit a static surface tension <25 mN/m, the said surfactants A containing at least three short-chain perfluorinated groups Rf selected from the group consisting of trifluoromethyl, pentafluoroethyl, 1-heptafluoropropyl, 2-heptafluoropropyl, heptafluoroisopropyl, and pentafluorosulfanyl; for manufacturing integrated circuits comprising patterns having line-space dimensions below 50 nm and aspect ratios >3; and a photolithographic process making use of the surfactants A in immersion photoresist layers, photoresist layers exposed to actinic radiation, developer solutions for the exposed photoresist layers and/or in chemical rinse solutions for developed patterned photoresists comprising patterns having line-space dimensions below 50 nm and aspect ratios >3.

Abstract: A method for processing a substrate includes providing a set of patterned structures separated by a first gap on the substrate and directing first implanting ions to the substrate at a first ion energy, where the first implanting ions are effective to impact the substrate in regions defined by the first gap. The method also includes directing depositing ions to the substrate where the second ions are effective to deposit material on at least a portion of the set of patterned structures to form expanded patterned structures, where the expanded patterned structures are characterized by a second gap smaller than the first gap. The method further includes directing second implanting ions to the substrate at a second ion energy, where the second implanting ions effective to impact the substrate in regions defined by the second gap, the second ion energy comprising a higher ion energy than the first ion energy.

Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.