Abstract: In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.

Abstract: A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Abstract: Approaches for forming an oxide cap to protect a semiconductor device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming an oxide cap over a subset (e.g., SiP regions) of raised source drain (RSD) structures on the set of fins of the FinFET device to mitigate damage during subsequent processing. The oxide spacer is deposited before the removal of a nitride capping layer from the FinFET device (e.g., by a hot phosphorus wash). The oxide cap on top of the RSD structures will be preserved throughout the removal of the nitride capping layer to provide hardmask protection during this process.

Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

Abstract: Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

Abstract: A test structure includes an active region formed in a semiconducting substrate, a first line formed above and extending over an upper surface of the active region, and a first isolation region formed in the semiconducting substrate, wherein the active region surrounds the first isolation region. The test structure further includes a first extension formed above the active region and on and in contact with an upper surface of the first isolation region, wherein the first extension extends laterally over the upper surface of the active region from a first side of the first line. Additionally, the first line and the first extension are comprised of at least one of a high-k layer of insulating material and a metal layer.

Abstract: The present invention has a tray corresponding to a heat sink, a circuit part is accommodated in an accommodating part of the tray, and the circuit part is potting-sealed with a sealing resin such that external electrodes are exposed. The sealing resin covers and seals a top part of the tray.

Abstract: The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction.

Abstract: A glass composition for protecting a semiconductor junction is made of fine glass particles prepared from a material in a molten state obtained by melting a glass raw material which contains at least ZnO, SiO2, B2O3, Al2O3 and at least two oxides of alkaline earth metals selected from a group consisting of BaO, CaO and MgO and substantially contains none of Pb, As, Sb, Li, Na and K, the glass composition for protecting a semiconductor junction containing no filler.

Abstract: A stacked integrated circuit package system includes: providing a base integrated circuit package, and mounting a top integrated circuit package having a top interposer and a top encapsulation with a cavity therein or the cavity as a space between top intra-stack interconnects and the top interposer, with the top interposer exposed by the cavity, over the base integrated circuit package.

Abstract: A chip package is provided. The chip package includes a semiconductor chip, an isolation layer, a redistributing metal layer, and at least a bonding pad. The semiconductor chip includes at least one conducting disposed on a surface of the semiconductor chip. The isolation layer is disposed on the surface of the semiconductor chip, wherein the isolation layer has at least one first opening to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has at least a redistributing metal line corresponding to the conducting pad, the redistributing metal line is connected to the first conducting pad through the first opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the conducting pad to the bonding pad.

Abstract: A conventional semiconductor device used for a power supply circuit such as a DC/DC converter has problems of heat dissipation and downsizing, in particular has the problems of heat dissipation and others in the event of downsizing. A semiconductor device has a structure formed by covering a principal surface of a semiconductor chip having the principal surface and a plurality of MIS type FETs formed over the principal surface with a plurality of metal plate wires having pectinate shapes; allocating the pectinate parts alternately in a planar view over the principal surface; and further electrically coupling the plural metal plate wires to a plurality of terminals.

Abstract: Apparatus and methods for forming a heat spreader on a substrate to release heat for a semi-conductor package are disclosed. The apparatus comprises a substrate. A dielectric layer is formed next to the substrate and in contact with a surface of the substrate. A heat spreader is formed next to the substrate and in contact with another surface of the substrate. A passivation layer is formed next to the dielectric layer. A connection pad is placed on top of the passivation layer. The substrate may comprise additional through-silicon-vias. The contact surface between the substrate and the heat spreader may be a scraggy surface. The packaging method further proceeds to connect a chip to the connection pad by way of a connection device such as a solder ball or a bump.

Abstract: An integrated heat spreader comprising a heat spreader frame that has a plurality of openings formed therethrough and a plurality of thermally conductive structures secured within the heat spreader frame openings. The thermally conductive structures can be formed to have various thicknesses which compensate for varying heights between at least two microelectronic devices in a multi-chip package. The thermally conductive structures can be secured in the heat spreader frame by sizing the openings and the thermally conductive structures such that the thermally conductive structures can be secured within the openings without requiring welding or adhesives.

Abstract: An electric power semiconductor device includes a power module and a heat dissipating member connected to the power module through a heat-conductive insulating resin sheet in which a mold resin part included in the power module has a protruding part in its peripheral part to prevent the heat-conductive insulating resin sheet from expanding in a planar direction. The heat-conductive insulating resin sheet is slightly thicker than the protruding part and has a resin exuding part exuded from a small gap between the protruding part and the heat dissipating member while the power module and the heat dissipating member are heated and pressurized to be bonded.

Abstract: Through-via structures and methods of their formation are disclosed. One such structure includes a conductor structure, a dielectric via lining and a stress-abating dielectric material. The conductor structure is formed of conducting material extending through a wiring layer of a semiconductor device and through a semiconductor layer below the wiring layer. Here, the wiring layer of the semiconductor device includes a first dielectric material. The dielectric via lining extends along the conductor structure at least in the semiconductor layer. Further, the stress-abating dielectric material is disposed between the conductor structure and the first dielectric material in at least the wiring layer, where the stress-abating dielectric material is disposed over portions of the semiconductor layer that are outside outer boundaries of the via lining.

Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.

Abstract: A semiconductor device includes: a punch stop region formed in a substrate; a plurality of buried bit lines formed over the substrate; a plurality of pillar structures formed over the buried bit lines; a plurality of word lines extending to intersect the buried bit lines and being in contact with the pillar structures; and an isolation layer isolating the word lines from the buried bit lines.

Abstract: A through-silicon-via structure formed within a semiconductor device is provided. The TSV structure may include a trench located within a substrate of the semiconductor device, an insulator layer located on at least one side wall of the trench, an electrically conductive layer located on the insulator layer, a first dielectric layer located on the electrically conductive layer, and a second dielectric layer located on the first dielectric layer and filling the trench. The second dielectric layer includes a higher refractive index relative to the first dielectric layer, such that the first and the second dielectric layer create an optical waveguide.

Abstract: A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals.

Abstract: A power module according to the present invention includes a semiconductor device; a base part formed from an electrically conductive material on which the semiconductor device is mounted; a signal lead part formed from the same material as the base part, the signal lead part being electrically connected to the semiconductor device; and a thin plate lead part formed from the same material as the base part such that it is formed seamlessly from the base part and it is thinner than the base part, the thin plate lead part extending on the same side as the signal lead part with respect to the base part, wherein the thin plate lead part is electrically connected to a predetermined terminal of the semiconductor device via the base part such that it forms a potential detecting terminal for detecting a potential of the predetermined terminal of the semiconductor device.

Abstract: An electronic apparatus includes a packaging enclosure, first and second die pads disposed within the packaging enclosure, first and second semiconductor die disposed on the first and second die pads, respectively, a plurality of packaging leads, each packaging lead projecting outward from the packaging enclosure, a plurality of packaging posts disposed within the packaging enclosure and extending inward from opposite sides of the packaging enclosure between the first and second die pads, each packaging post being connected with a respective one of the plurality of packaging leads, and a plurality of wire bonds disposed within the packaging enclosure. Each packaging post of the plurality of packaging posts is connected via a first wire bond of the plurality of wire bonds to the first semiconductor die and via a second wire bond of the plurality of wire bonds to the second semiconductor die.

Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.

Abstract: A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group.

Abstract: A wiring substrate includes a wiring layer, an outermost insulating layer laminated to the wiring layer, and a pad electrically connected to the wiring layer and exposed from a surface of the outermost insulating layer. The pad consists essentially of a first metal layer and a second metal layer. The first metal layer includes a first surface, which is exposed from the surface of the outermost insulating layer, and a second surface, which is located opposite to the first surface. The second metal layer includes is formed between the second surface of the first metal layer and the wiring layer. The first metal layer is formed from a metal selected from gold or silver or from an alloy including at least one of gold and silver. The second metal layer is formed from palladium or a palladium alloy.

Abstract: A device includes first and second semiconductor chips. The first semiconductor chip includes an edge defining a periphery of the first semiconductor chip. The second semiconductor chip is greater in size than the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip. The second semiconductor chip includes a plurality of wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip, an insulating film which covers the wiring patterns and which includes on or more holes that expose one or more the wiring patterns, and one or more bump electrodes formed on the one or more the wiring patterns. Remaining one or ones of the wiring patterns is kept covered by the insulating layer and includes the first wiring pattern.

Abstract: Systems and methods are provided for an integrated circuit package. A plurality of electrical contacts are configured to provide a structure for electrically connecting the integrated circuit package to a printed circuit board. A package substrate includes at least one patterned metallic layer formed to electrically interconnect I/O contacts of an integrated circuit to the plurality of electrical contacts, and at least one generally uniform metallic layer having a plurality of voids that are respectively situated in axial alignment with corresponding ones of the electrical contacts, and one or more dielectric layers disposed between the plurality of electrical contacts and the metallic layers.

Abstract: A semiconductor package includes a substrate having a vent hole extending through the substrate, a semiconductor chip mounted on an upper surface of the substrate, a plurality of solder ball pads formed on a lower surface of the substrate, and an encapsulant covering the upper surface of the substrate, the semiconductor chip, and an entirety of the lower surface of the substrate except for regions in which the solder ball pads are formed.

Abstract: A method for manufacturing a build-up substrate, the build-up substrate comprising an insulating layer and a wiring pattern layer stacked over a circuit substrate, said method comprising the steps of: (i) applying a photoactive metal oxide precursor material to one or both sides of the circuit substrate with a wiring pattern, and drying the applied photoactive metal oxide precursor material to form an insulating film; (ii) forming an opening for a via hole in the insulating film by exposure and development of the insulating film; (iii) applying a heat treatment to the insulating film to convert the insulating film into a metal oxide film, thereby forming a build-up insulating layer of the metal oxide film; and (iv) plating the build-up insulating layer to form via holes in the openings, forming a metal layer on the build-up insulating layer, and etching the metal layer to form a build-up wiring pattern; and (v) repeating the steps from (i) to (iv) at least one time.

Abstract: Disclosed herein is a plug via stacked structure including: a through hole plating layer plated on a through hole inner wall and around top and bottom of a through hole at thickness t; a via plug filled in an inner space of the through hole plating layer; a circuit pattern formed over the top and bottom of the through hole plating layer and the via plug and making a thickness t? formed on the through hole plating layer thicker than a thickness t; and a stacked conductive via filled in a via hole formed on the top of the through hole and formed at thickness ? from a top of the circuit pattern, wherein T?t?+? is satisfied, T represents a sum of the thicknesses t and t? and t? is a thickness of a portion of the circuit pattern formed on the via plug.

Abstract: A three-dimensional semiconductor device includes first and second selection lines stacked one on the other. An upper line horizontally crosses over the first and second selection lines. First and second vertical patterns vertically cross the first and second selection lines. The first and second vertical patterns are connected in common to the upper line. Each of the first and second vertical patterns constitutes first and second selection transistors that are connected in series to each other. The first selection transistors of the first and second vertical patterns are controlled by the first and second selection lines, respectively.

Abstract: A silicon interposer includes a plurality of patterned metal layers formed on a silicon wafer portion and a plurality of through-silicon vias extending through the silicon wafer portion. The through-silicon vias have an interdiffusion conductive element.

Abstract: Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating.

Abstract: An integrated circuit includes a substrate having a plurality of electronic devices, a plurality of interconnect layers disposed on one or both sides of the substrate, and a plurality of active electrically conductive interconnect layer structures. The plurality of interconnect layers include horizontal interconnect and vertical-interconnect-access (VIA) layers. The plurality of active electrically conductive interconnect layer structures are disposed on at least one of the plurality of interconnect layers and electrically coupled with at least one of the plurality of electronic devices. The integrated circuit also includes a plurality of spare electrically conductive interconnect layer structures disposed on at least one of the plurality of interconnect layers and electrically isolated from the plurality of active electrically conductive interconnect layer structures.

Abstract: A back-end-of-line thin ion beam deposited fuse (204) is deposited without etching to connect first and second last metal interconnect structures (110, 120) formed with last metal layers (LM) in a planar multi-layer interconnect stack to programmably connect separate first and second circuit connected to the first and second last metal interconnect structures.

Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.

Abstract: A device includes a substrate with a recess, having a bottom and sides, extending into the substrate from the substrate's upper surface. The sides include first and second sides oriented transversely to one another. A stack of alternating active and insulating layers overlie the substrate's surface and the recess. At least some of the active layers have an upper and lower portions extending along upper and lower planes over and generally parallel to the upper surface and to the bottom, respectively. The active layers have first and second upward extensions positioned along the first and second sides to extend from the lower portions of their respective active layers. Conductive strips adjoin the second upward extensions of the said active layers. The conductive strips can comprise sidewall spacers on the sides of the second upward extensions, the conductive strips connected to overlying conductors by interlayer conductors.

Abstract: Manufacturing a DC-DC converter on a chip includes: providing a die having a p-type top side and an n-type bottom side; removing an interior portion, creating a hole; flipping the interior portion; inserting the interior portion into the hole; fabricating high-side switch cells in the interior portion's top side and low-side switch cells in the exterior portion's top side; sputtering a magnetic material on the entire top side; burrowing tunnels into the magnetic material; and applying conductive material on the magnetic material and within the tunnels, electrically coupling pairs of high-side and low-side switches, with each pair forming a micro-power-switching phase, where the conductive material forms an output node of the phase, and the conductive material in the burrowed tunnels forms, in each phase, a torodial inductor with a single loop coil and, for the plurality of phases, a directly coupled inductor.

Abstract: A method of forming a buried die module includes providing an initial laminate flex layer and forming a die opening through the initial laminate flex layer. A first uncut laminate flex layer is secured to the first surface of the initial laminate flex layer by way of an adhesive material and a die is positioned within the die opening of the initial laminate flex layer and onto the adhesive material. A second uncut laminate flex layer is secured to the second surface of the initial laminate flex layer by way of an adhesive material and the adhesive materials are then cured. Vias and metal interconnects are formed in and on the first and second uncut laminate flex layers, with each of the metal interconnects extending through a respective via and being directly metalized to a metal interconnect on the initial laminate flex layer or a die pad on the die.

Abstract: Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Abstract: An integrated circuit package including a first substrate, a first die, a second die, a second substrate, and a system on chip. The first substrate includes a first portion including first connections, a second portion including no connections, a third portion including second connections, a first opening between the first portion and the second portion, and a second opening between the second portion and the third portion. The first die is arranged on the first substrate. The first die includes third connections to connect to the first connections via the first opening. The second die is arranged adjacent to the first die on the first substrate. The second die includes fourth connections to connect to the second connections via the second opening. The second substrate is connected to the first substrate. The system on chip is arranged on the second substrate between the first substrate and the second substrate.

Abstract: A semiconductor device includes a carrier, several dies disposed on a surface of the carrier and several scribing lines defined on the surface of the carrier. The scribing lines include several continuous lines along a first direction and several discontinuous lines along a second direction. Further, a method of dies singulation includes providing a carrier, disposing several dies on a surface of the carrier according to several scribing lines including several continuous lines along a first direction and several discontinuous lines along a second direction, cutting the carrier according to the continuous lines along the first direction, and cutting the carrier according to the discontinuous lines along the second direction.

Abstract: A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV.

Abstract: An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors.

Abstract: A semiconductor package with thermal neutron shielding is disclosed. The semiconductor package includes a substrate and an integrated circuit die disposed on the substrate. The semiconductor package also has a thermal neutron shield including a shielding material. The shielding material includes boron-10 and is configured to inhibit a portion of thermal neutrons that encounter the thermal neutron shield from passing through the thermal neutron shield.

Abstract: In some embodiments, a semiconductor device package assembly may include a first substrate. The first substrate may include a first set of electrical conductors which electrically connect the assembly. In some embodiments, the assembly may include at least one electrical conductor coupled to the first substrate such that at least one of the electrical conductors exposes through a perimeter surface of the semiconductor device package assembly. In some embodiments, the assembly may include a first die electrically connected to a second surface of the first substrate using a second set of electrical conductors. The assembly may include an electronic memory module coupled to the first die. In some embodiments, the assembly may include a shield applied to an upper surface of the assembly and electrically coupled to at least one of the exposed electrical conductors. The shield may inhibit, during use, electromagnetic interference.

Abstract: A semiconductor package includes a substrate, a grounding layer, a chip, a package body, and a shielding layer. The substrate includes a lateral surface and a bottom surface. The grounding layer is buried in the substrate and extends horizontally in the substrate. The chip is arranged on the substrate. The package body envelops the chip and includes a lateral surface. The shielding layer covers the lateral surface of the package body and the lateral surface of the substrate, and is electrically connected to the grounding layer, where a bottom surface of the shielding layer is separated from a bottom surface of the substrate.

Abstract: External connection conductors are arranged on a back surface of a base material, and wiring conductors are arranged on a front surface. An insulating layer is provided on surfaces of the wiring conductors. Component mounting conductors are provided on a surface of the insulating layer. The component mounting conductor and the wiring conductor are electrically coupled to each other, and the component mounting conductor and the wiring conductor are electrically coupled to each other. The wiring conductor and the external connection conductor are electrically coupled by a conductor film on an inner wall surface of a hole provided between forming areas of the component mounting conductors. The wiring conductor and the external connection conductor are electrically coupled by a conductor film on an inner wall surface of a hole provided between the forming areas of the component mounting conductors.

Abstract: An integrated circuit package comprising a substrate and at least one semiconductor die is described. A connection unit may provide electrical connections between the substrate and the semiconductor die. The connection unit may comprise a stack of conduction layers and isolation layers stacked atop each other. The stack may include a microstrip line or a coplanar waveguide. The microstrip line or the coplanar waveguide may be part of a balun, a power divider, or a directional coupler.

Abstract: A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.