Abstract: Group III (Al, Ga, In)N single crystals, articles and films useful for producing optoelectronic devices (such as light emitting diodes (LEDs), laser diodes (LDs) and photodetectors) and electronic devices (such as high electron mobility transistors (HEMTs)) composed of III-V nitride compounds, and methods for fabricating such crystals, articles and films.

Abstract: In a manufacturing method of a silicon carbide semiconductor device, a semiconductor substrate made of single crystal silicon carbide is prepared. At a portion of the semiconductor substrate where a first electrode is to be formed, a metal thin film made of electrode material including an impurity is formed. After the metal thin film is formed, the first electrode including a metal reaction layer in which the impurity is introduced is formed by irradiating the metal thin film with a laser light.

Abstract: A joining device for joining substrates with an intermolecular force includes a first holding unit configured to hold a first substrate on a lower surface thereof, a second holding unit installed below the first holding unit and configured to hold a second substrate on an upper surface thereof, and a temperature adjustment mechanism configured to adjust a temperature of the first substrate before the first substrate is held in the first holding unit and a temperature of the second substrate before the second substrate is held in the second holding unit to a predetermined temperature.

Abstract: Provided are a reaction tube, a substrate processing apparatus, and a method of manufacturing a semiconductor device capable of suppressing a non-uniform distribution of a gas in a top region to improve the flow of the gas and film uniformity within and between substrate surfaces. The reaction tube has a cylindrical shape, accommodates a plurality of substrates stacked therein, and includes a cylindrical portion and a ceiling portion covering an upper end portion of the cylindrical portion, the ceiling portion having a substantially flat top inner surface. A thickness of a sidewall of the ceiling portion is greater than that of a sidewall of the cylindrical portion.

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.

Abstract: A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region.

Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a semiconductor substrate that includes a first substrate region, a second substrate region, and a third substrate region; providing a first mask that overlaps the semiconductor substrate; etching, using the first mask, the first semiconductor substrate to form a trench in each of the substrate regions; providing a second mask that overlaps the semiconductor substrate and includes three openings corresponding to the substrate regions; performing first ion implantation through the three openings to form a P-doped region in each of the substrate regions; performing second ion implantation through the three openings to form an N-doped region in each of the substrate regions; and performing third ion implantation through the three openings to form another N-doped region in each of the substrate regions; and forming an isolation member in each of the trenches.

Abstract: In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a semiconductor substrate and a interlayer dielectric (ILD) over the semiconductor substrate. A gate structure is formed within the ILD and disposed on the semiconductor substrate, wherein the gate structure includes a high-k dielectric material layer and a metal gate stack. One or more portions of a protection layer are formed over the gate stack, and a contact etch stop layer is formed over the ILD and over the one or more portions of the protection layer. The metal gate stack includes aluminum and the protection layer includes aluminum oxide.

Abstract: A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a semiconductor device comprises a substrate comprising an isolation region separating and surrounding both a P-active region and an N-active region; a P-work function metal layer in a P-gate structure over the P-active region, wherein the P-work function metal layer comprises a first bottom portion and first sidewalls, wherein the first bottom portion comprises a first layer of metallic compound with a first thickness; and an N-work function metal layer in an N-gate structure over the N-active region, wherein the N-work function metal layer comprises a second bottom portion and second sidewalls, wherein the second bottom portion comprises a second layer of the metallic compound with a second thickness less than the first thickness.

Abstract: Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.

Abstract: Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion.

Abstract: A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film.

Abstract: A method for manufacturing a contact plug is provided. The method includes providing a silicon substrate having at least one opening. A titanium layer is conformably formed in the opening. A first barrier layer is conformably formed on the titanium layer in the opening. A rapid thermal process is performed on the titanium layer and the first barrier layer. After performing the rapid thermal process, a second barrier layer is conformably formed on the first barrier layer in the opening.

Abstract: A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.

Abstract: An etching method and apparatus for etching a silicon oxide film selectively with respect to a silicon nitride film formed on a substrate are provided. A processing gas containing a plasma excitation gas and a CHF-based gas is introduced into a processing chamber such that a flow rate ratio of the CHF-based gas to the plasma excitation gas is 1/15 or higher. By generating a plasma in the processing chamber, the silicon oxide film is etched selectively with respect to the silicon nitride film formed on the substrate in the processing chamber.

Abstract: A method for forming lines in an etch layer on a substrate may comprise providing a ultra-violet (UV) producing gas to a vacuum chamber having a photoresist mask, ionizing the UV producing gas to produce UV rays to irradiate the photoresist mask, and etching the lines into the etch layer through the photoresist mask.

Abstract: There is provided a composition for forming a resist underlayer film having heat resistance for use in a lithography process in semiconductor device production. A composition for forming a resist underlayer film, comprising a polymer that contains a unit structure of formula (1) and a unit structure of formula (2) in a proportion of 3 to 97:97 to 3 in molar ratio: A method for producing a semiconductor device, including the steps of: forming an underlayer film using the composition for forming a resist underlayer film on a semiconductor substrate; forming a hard mask on the underlayer film; further forming a resist film on the hard mask; forming a patterned resist film and developing; etching the hard mask according to the patterned resist film; etching the underlayer film according to the patterned hard mask; and processing the semiconductor substrate according to the patterned underlayer film.

Abstract: A novel diarylamine novolac resin such as a phenylnaphthylamine novolac resin, and further a resist underlayer film-forming composition in which the resin is used in a lithography process for manufacturing a semiconductor device. A polymer including a unit structure (A) of Formula (1): (in Formula (1), each of Ar1 and Ar2 is a benzene ring or a naphthalene ring). A method for manufacturing a semiconductor device, including: forming an underlayer film on a semiconductor substrate with the resist underlayer film-forming composition; forming a hardmask on the underlayer film; forming a resist film on the hardmask; forming a resist pattern by irradiation with light or an electron beam followed by development; etching the hardmask with the resist pattern; etching the underlayer film with the hardmask thus patterned; and processing the semiconductor substrate with the underlayer film thus patterned.

Abstract: A method of forming fin-shaped structures includes the following steps. A plurality of spacers is formed on a substrate. The substrate is etched by using the spacers as hard masks to form a plurality of fin-shaped structures in the substrate. A cutting process is then performed to remove parts of the fin-shaped structures and the spacers formed on the removed parts.

Abstract: A method for lithography is disclosed. The method includes obtaining a self-organizing block-copolymer layer on a neutral layer overlying a substrate, the self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, the self-organizing block-copolymer layer furthermore comprising a copolymer pattern structure formed by micro-phase separation of the at least two polymer components. Further, the method includes etching selectively a first polymer component of the self-organizing block-copolymer layer, thereby remaining a second polymer component. Still further, the method includes applying a plasma etching to the neutral layer using the second polymer component as a mask, wherein the plasma etching comprises an inert gas and H2.

Abstract: Provided is an adhesion-promoting composition between a curable composition for imprints and a substrate, which excellent in adhesiveness and can control pattern failure. An adhesion-promoting composition used between a curable composition for imprints and a substrate, which comprises a compound having a molecular weight of 500 or larger and having a reactive group, and has a content of a compound, with a molecular weight of 200 or smaller, of more than 1% by mass and not more than 10% by mass of a total solid content.

Abstract: Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.

Abstract: To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: Embodiments of mechanisms of a semiconductor structure are provided. The semiconductor device structure includes a substrate and a floating gate having a first sidewall and a second sidewall formed over the substrate. The semiconductor device further includes an insulating layer formed over the substrate to cover the first sidewall and an upper portion of the second sidewall of the floating gate. The semiconductor device further includes a control gate formed over the insulating layer. In addition, the floating gate is formed in a shark's fin shape.

Abstract: A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer.

Abstract: A nanowire field effect transistor (FET) device and method for forming the same is disclosed. The device comprises: a semiconductor substrate; a device layer including a source region and a drain region connected by a suspended nanowire channel; and etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material disposed beneath the suspended nanowire channel and between the etch stop layers. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.

Abstract: A chemical-mechanical polishing (“CMP”) composition (P) comprising (A) inorganic particles, organic particles, or a mixture or composite thereof, (B) at least one type of A/-heterocyclic compound as corrosion inhibitor, (C) at least one type of a further corrosion inhibitor selected from the group consisting of: (C1) an acetylene alcohol, and (C2) a salt or an adduct of (C2a) an amine, and (C2b) a carboxylic acid comprising an amide moiety, (D) at least one type of an oxidizing agent, (E) at least one type of a complexing agent, and (F) an aqueous medium.

Abstract: A method for self-aligned double patterning without needing atomic layer deposition techniques is disclosed. Techniques include using a staircase etch technique to preferentially shrink one material without shrinking an underlying material, followed by a resist-based chemical polishing and planarization technique that yields a narrowed and protruding feature (single-layer thickness) that is sufficiently physically supported, and that can be transferred to one or more underlying layers. After removing a resist coating, the result is a pattern that has been doubled without using ALD techniques. Such techniques improve efficiencies over conventional techniques for self-aligned double patterning.

Abstract: A plasma etching apparatus 11 includes a mounting table that holds a semiconductor substrate W thereon; a first heater 18a that heats a central region of the semiconductor substrate W held on the mounting table 14; a second heater 18b that heats an edge region around the central region of the semiconductor substrate W held on the mounting table 14; a reactant gas supply unit 13 that supplies a reactant gas for a plasma process toward the central region of the semiconductor substrate W held on the mounting table 14; and a control unit 20 that performs a plasma etching process on the semiconductor substrate W while controlling the first heater 18a and the second heater 18b to heat the central region and the edge region of the processing target substrate W held on the mounting table 14 to different temperatures.

Abstract: In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.

Abstract: A method for manufacturing vias in a glass substrate includes bonding, through a bonding layer, a first face of the glass substrate including a plurality of holes to a first face of a glass carrier. The bonding layer has a thickness t between the first face of the glass substrate and the first face of the glass carrier and extends into at least some of the plurality of holes to a depth h from the first face of the glass substrate. The method includes etching back the bonding layer to a depth d through the plurality of holes in the glass substrate. The depth d is less than the sum of the thickness t and the depth h. The method can include filling the plurality of holes with an electrically conductive material, and de-bonding the glass substrate from the bonding layer and the glass carrier.

Abstract: A semiconductor die has first and second discrete semiconductor components mounted over a plurality of wettable contact pads formed on a carrier. Conductive pillars are formed over the wettable contact pads. A semiconductor die is mounted to the conductive pillars over the first discrete components. The conductive pillars provide vertical stand-off of the semiconductor die as headroom for the first discrete components. The second discrete components are disposed outside a footprint of the semiconductor die. Conductive TSV can be formed through the semiconductor die. An encapsulant is deposited over the semiconductor die and first and second discrete components. The wettable contact pads reduce die and discrete component shifting during encapsulation. A portion of a back surface of the semiconductor die is removed to reduce package thickness. An interconnect structure is formed over the encapsulant and semiconductor die. Third discrete semiconductor components can be mounted over the semiconductor die.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: Rinsing methodologies and components to accomplish rinsing of tool surfaces in tools that are used to process one or more microelectronic workpieces. The invention can be used to rinse structures that overlie a workpiece being treated in such a manner to function in part as a lid over the process chamber while also defining a tapering flow channel over the workpiece. Rather than spray rinsing liquid onto the surface in a manner that generates undue splashing, droplet, or mist generation, a swirling flow of rinse liquid is generated on a surface of at least one fluid passage upstream from the surface to be rinsed. The swirling flow then provides smooth, uniform wetting and sheeting action to accomplish rinsing with a significantly reduced risk of generating particle contamination.

Abstract: Suppressed is damage of a semiconductor wafer due to charging of a cleaning liquid used in a single wafer type wafer cleaning step. A chemical solution discharged from a tip of a cleaning nozzle is brought into contact with protrusions of wafer chucks to thereby let static electricity of the chemical solution go to the wafer chucks, and subsequently, the cleaning nozzle is moved above the wafer to supply the chemical solution onto a top surface of the wafer, thereby suppressing abnormal discharge (damage) of the wafer due to charging of the chemical solution.

Abstract: An apparatus is provided, by way of example, a heater for use in semiconductor processing equipment that includes a base functional layer having at least one functional zone. A substrate is secured to the base functional layer, and a tuning layer is secured to the substrate opposite the base functional layer. The tuning layer includes a plurality of zones that is greater in number than the zones of the base functional layer, and the tuning layer has lower power than the base functional layer. Further, a component, such as a chuck by way of example, is secured to the tuning layer opposite the substrate. The substrate defines a thermal conductivity to dissipate a requisite amount of power from the base functional layer.

Abstract: A protective layer is applied to a work piece to protect the surface during charged particle beam processing by directing a fluid toward the surface. The surface is preferably not touched by the applicator. Ink jet print-type print heads are suitable applicators. Ink jet-type print heads allow a wide variety of fluids to be used to form the protective layer. Useful fluids that form protective layers include colloidal silica having small silver particles and hydrocarbon-based inks.

Abstract: Provided are an apparatus and method for treating a substrate, and more particularly, to a substrate treatment apparatus having a cluster structure and a substrate treatment method using the same. The apparatus for treating the substrate includes a load port on which a container for receiving the substrate is placed, a treatment module for treating the substrate, and a transfer module including a robot for transferring the substrate between the container and the treatment module. The treatment module includes a transfer chamber including a robot for transferring the substrate, a load lock chamber disposed between the transfer chamber and the transfer module, a first treatment chamber disposed spaced from the transfer module around the transfer chamber to perform a first treatment process, and a second treatment chamber disposed around the transfer chamber to perform a second treatment process.

Abstract: Methods of dicing substrates having a plurality of ICs are disclosed. A method includes forming a mask comprising a water soluble material layer over the semiconductor substrate. The mask is patterned with a femtosecond laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then etched through the gaps in the patterned mask to singulate the IC and the water soluble material layer is washed off.

Abstract: The present invention provides methods and apparatus capable of routine placement and replacement of fabricator tools in a designated tool location. The tool location can be selected from multiple tool locations arranged in a matrix with horizontal and vertical designations. The operation may be fully automated. In another aspect, the invention describes Cleanspace fabricators which use devices to routinely remove and place tooling.

Abstract: A substrate treating apparatus is provided. The substrate treating apparatus includes a loading/unloading unit, a process unit in which a substrate treating process is performed, a loadlock unit disposed between the loading/unloading unit and the process unit, and a carrying member transferring a substrate between the process unit and the loadlock unit. Herein, the carrying member is provided in the process unit and the loadlock unit, and the loading/unloading unit, the loadlock unit, and the process unit are sequentially disposed.

Abstract: In a transport system, a local track is disposed so as to be below an overhead travelling vehicle track in parallel or substantially in parallel therewith, and furthermore above a loading port of a processing device from upstream of the loading port to downstream of the loading port. A local vehicle including a hoist travels along the local track. Below the local track, a first buffer is disposed upstream of the loading port of the processing device, and a second buffer is disposed downstream of the loading port of the processing device, and the overhead travelling vehicle and the local vehicle can both perform delivery and receipt of the article with the first buffer and the second buffer.

Abstract: A joining device includes a first holding unit configured to load and hold the first member on its top surface; a second holding unit disposed above the first holding unit while facing the first holding unit and configured to hold the second member; and a position adjustment mechanism configured to adjust a joining position between the first member held by the first holding unit and the second member held by the second holding unit. The second holding unit is of a circular plate shape, and the position adjustment mechanism includes four position-adjusting cam members disposed at equal intervals along an outer peripheral surface of the second holding unit, and moves the second holding unit in a horizontal direction.

Abstract: A plasma processing apparatus is provided which includes a processing chamber disposed in a vacuum container, in a decompressed inside of which plasma is formed, a sample stage disposed in a lower part of the processing chamber, on a top surface of which a sample is mounted, a dielectric film made of a dielectric that forms a mounting surface on which the sample is mounted, and electrodes arranged inside the dielectric film and supplied with power for chucking and holding the sample onto the dielectric film, and when the sample is mounted on the sample stage, the sample is kept mounted on the sample stage until a sample temperature becomes a predetermined temperature or until a predetermined time elapses, and power is then supplied to the electrodes to chuck the sample to the sample stage and then start processing on the sample using the plasma.

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

Abstract: An LED leadframe or LED substrate includes a main body portion having a mounting surface for mounting an LED element thereover. A reflection metal layer serving as a reflection layer for reflecting light from the LED element is disposed over the mounting surface of the main body portion. The reflection metal layer comprises an alloy of platinum and silver or an alloy of gold and silver. The reflection metal layer efficiently reflects light emitted from the LED element and suppresses corrosion due to the presence of a gas, thereby capable of maintaining reflection characteristics of light from the LED element.