Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.

Abstract: An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.

Abstract: A display device including TFT elements having satisfactory characteristics and being easy to assemble. In the display device, a pixel emitting red light comprises a red color filter. The red color filter forms a light shielding film for the TFT elements in a driver circuit portion or in a pixel portion.

Abstract: Provided is a semiconductor device including a buffer layer that is on a substrate and includes an inclined surface; a crystalline silicon layer that is on the buffer layer; a gate electrode that is on the crystalline silicon layer while being insulated from the crystalline silicon layer; and a source electrode and a drain electrode that are each electrically connected to the crystalline silicon layer, the angle between the substrate and the inclined surface being in a range of about 17.5 degrees to less than about 70 degrees.

Abstract: An object is at least one of a longer data retention period of a memory circuit, a reduction in power consumption, a smaller circuit area, and an increase in the number of times written data can be read to one data writing operation. The memory circuit has a first field-effect transistor, a second field-effect transistor, and a rectifier element including a pair of current terminals. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of the pair of current terminals of the rectifier element is electrically connected to a source or a drain of the second field-effect transistor.

Abstract: An aperture ratio of a semiconductor device is improved. A driver circuit and a pixel are provided over one substrate, and a first thin film transistor in the driver circuit and a second thin film transistor in the pixel each include a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer over the gate insulating layer, source and drain electrode layers over the oxide semiconductor layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer, and the source and drain electrode layers. The gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source and drain electrode layers, and the oxide insulating layer of the second thin film transistor each have a light-transmitting property.

Abstract: In a semiconductor device which conducts multilevel writing operation and a driving method thereof, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. Because an oxide semiconductor material that is a wide gap semiconductor capable of sufficiently reducing off-state current of a transistor is used, data can be held for a long period.

Abstract: A thin film transistor array substrate includes an active area in which a plurality of pixels are formed; driver integrated circuits (DICs) disposed in a non-active area around the active area and configured to supply a driving signal to each of the plurality of pixels; power input units partially overlapping with the DICs, disposed below the DICs, and configured to supply power voltages to the active area; and a user key mounting area formed not to overlap with the DICs in the non-active area. The thin film transistor array substrate may be used for an organic light-emitting display apparatus.

Abstract: A thin film transistor (TFT) substrate comprises a substrate, a plurality of pixel electrodes, a gate layer, an active layer, a first source layer and a second source layer, and a drain layer. The pixel electrodes are disposed on the substrate. The gate layer is disposed on the substrate. The active layer is disposed corresponding to the gate layer. The first source layer and the second source layer contact the active layer respectively. The drain layer contacts the active layer and is electrically coupled to one of the pixel electrodes. The gate layer, the active layer, the first source layer and the drain layer constitute a first transistor. The gate layer, the active layer, the second source layer and the drain layer constitute a second transistor. When the first and second transistors are disabled, the first and second source layers are electrically isolated from each other.

Abstract: An inexpensive display device, as well as an electrical apparatus employing the same, can be provided. In the display device in which a pixel section and a driver circuit are included on one and the same insulating surface, the driver circuit includes a decoder 100 and a buffer section 101. The decoder 100 includes a plurality of NAND circuits each including p-channel TFTs 104 to 106 connected to each other in parallel and other p-channel TFTs 107 to 109 connected to each other in series. The buffer section 101 includes a plurality of buffers each including three p-channel TFTs 114 to 116.

Abstract: A tri-gate display panel is provided, comprising: a plurality of pixel units each including three sub-pixel units for displaying different colors, wherein each sub-pixel unit is provided with a thin film transistor which has its source connected to a charge electrode of the sub-pixel unit via a capacitor of the sub-pixel unit per se; a plurality of gate lines which are successively arranged along a first direction of the display panel, so as to connect to gates of the thin film transistors of corresponding sub-pixel units; a plurality of data lines, which are successively arranged along a second direction of the display panel, so as to connect to drains of the thin film transistors of corresponding sub-pixel units; and a fanout area including a plurality of fanout lines, wherein output terminals of the plurality of fanout lines are arranged in accordance with the plurality of gate lines and are in pair-wise cross connections to the plurality of gate lines.

Abstract: A display device includes a display unit including a plurality of pixels respectively including thin film transistors; and a terminal unit including an array of a plurality of terminals. The display device includes a first insulating film provided on a substrate; the thin film transistors provided on the first insulating film; a second insulating film that is provided in the display unit and in the terminal unit and has openings located between the plurality of terminals; a plurality of signal lines that are provided on the second insulating film and are respectively connected to the thin film transistors, and a plurality of terminal lines that are provided on the second insulating film in the terminal unit; and a third insulating film that is located on the plurality of signal lines and the plurality of terminal lines and is formed of an organic insulating film.

Abstract: A fabricating method of an array substrate, an array substrate and a display device are provided. The array substrate includes a substrate; a plate electrode, a gate electrode, a gate line, a gate insulating film, semiconductor silicon islands, a source electrode, a drain electrode, a data line, a slit electrode formed on the substrate, and the substrate is also provided with a gate line through hole and a data line through hole. The gate electrode and the gate line include the first transparent conductive material and gate metal material stacked sequentially; the slit electrode is directly connected to the drain electrode; a second transparent conductive material is connected to the gate line through the gate line through hole; and connected to the data line through the data line through hole.

Abstract: The array substrate includes a substrate, a thin film transistor (TFT) and a pixel electrode. The TFT is disposed on the substrate and includes a gate electrode, a gate insulating layer, a patterned semiconductor layer, a patterned etching stop layer, a patterned hard mask layer, a source electrode and a drain electrode. The patterned gate insulating layer is disposed on the gate electrode. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The patterned etching stop layer is disposed on the patterned semiconductor layer. The source and the drain electrodes are disposed on the patterned etching stop layer and the patterned semiconductor layer. The patterned hard mask layer is disposed between the source electrode and the patterned etching stop layer and disposed between the drain electrode and the patterned etching stop layer. The pixel electrode is disposed on the substrate and electrically connected to the TFT.

Abstract: A solid-state imaging apparatus having a plurality of pixels, comprising: a substrate; a wiring layer formed on the substrate and including an insulating film and a plurality of wires; a plurality of lower electrodes formed on the wiring layer in one-to-one correspondence with the plurality of pixels; a photoelectric conversion film formed covering the plurality of lower electrodes; a light-transmissive upper electrode formed on the photoelectric conversion film; and a shield electrode extending through a gap between each pair of adjacent lower electrodes among the plurality of lower electrodes, the shield electrode having a fixed potential and being electrically insulated from the plurality of lower electrodes.

Abstract: An array panel including a substrate, a scanning line, a data line, and a pixel array is disclosed. A pixel unit in the pixel array includes a thin film transistor, a pixel electrode, and a color filter layer disposed between a first plane and a second plane. The first plane is a plane in which a gate electrode of the thin film transistor is located. The second plane is a plane in which the pixel electrode is located. The scanning line, the data line, and the pixel array are disposed on the substrate. The present invention is advantageous since it reduces power consumption.

Abstract: A pixel of an image sensor includes a polysilicon layer, and an active region which needs to be electrically coupled with the polysilicon layer, wherein the polysilicon layer extends over a portion of the active region, such that the polysilicon layer and the active region are partially overlapped, and the polysilicon layer and the active region are coupled through a buried contact structure.

Abstract: The present invention reduces color mixture (cross talk) and the degradation of sensitivity in a peripheral region of a pixel area to achieve a reduction of sensitivity irregularity in the pixel area. A solid-state imaging apparatus having a pixel area including a plurality of photoelectric conversion elements includes: a semiconductor substrate in which the plurality of photoelectric conversion elements are formed; a plurality of air gap formed layers which are arranged above the semiconductor substrate, and correspond to the photoelectric conversion elements in the plurality of photoelectric conversion elements, respectively; and air gaps arranged between the air gap formed layers in the plurality of air gap formed layers, respectively, wherein the air gap in a peripheral region B of the pixel area has a width larger than the air gap in a central region A of the pixel area.

Abstract: A method and device is disclosed for reducing noise in CMOS image sensors. An improved CMOS image sensor includes a light sensing structure surrounded by a support feature section. An active section of the light sensing structure is covered by no more than optically transparent materials. A light blocking portion includes an opaque layer or a black light filter layer in conjunction with an opaque layer, covering the support feature section. The light blocking portion may also cover a peripheral portion of the light sensing structure. The method for forming the CMOS image sensors includes using film patterning and etching processes to selectively form the opaque layer and the black light filter layer where the light blocking portion is desired, but not over the active section. The method also provides for forming microlenses over the photosensors in the active section.

Abstract: A photoelectric conversion apparatus includes a semiconductor substrate having a photoelectric conversion portion. An insulator is provided on the semiconductor substrate. The insulator has a hole corresponding to the photoelectric conversion portion. A waveguide member is provided in the hole. An in-layer lens is provided on a side of the waveguide member farther from the semiconductor substrate. A first intermediate member is provided between the waveguide member and the in-layer lens. The first intermediate member has a lower refractive index than the in-layer lens.

Abstract: The present technology relates to a semiconductor device, a manufacturing method of a semiconductor device, a semiconductor wafer, and electronic equipment, which allow a semiconductor device, in which miniaturization is possible, to be provided. A semiconductor device includes a semiconductor substrate, a wiring layer that is formed on the semiconductor substrate, and a drive circuit that is provided in a circuit forming region of the semiconductor substrate. Then, the semiconductor device is configured to include a pad electrode that is electrically connected to the drive circuit and exposed from the side surface of the wiring layer, and an external connection terminal that is provided in side surfaces of the semiconductor substrate and the wiring layer, and is electrically connected to the pad electrode.

Abstract: An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost.

Abstract: A solid-state imaging device includes a substrate in which a plurality of pixels including photoelectric converters are formed, a wiring layer that includes wirings in a plurality of layers formed via an interlayer insulating film in a front surface side of the substrate, a base electrode pad portion that includes a portion of the wirings formed in the wiring layer, an opening that penetrates the substrate from a rear surface side of the substrate and reaches the base electrode pad portion, and an embedded electrode pad layer that is formed so as to be embedded in the opening by electroless plating.

Abstract: A back-side illumination solid-state imaging apparatus, comprising a light-shielding member including a plurality of openings, and a plurality of pixels corresponding to the plurality of openings, wherein each pixel includes a photoelectric conversion portion, a microlens and an inner lens, the inner lens of a first pixel of an Mth row×an Nth column and the inner lens of a second pixel of an (M+1)th row×an (N+1)th column are separated from each other through a dielectric member, and the dielectric member contacts with part of the light-shielding member between a first opening corresponding to the first pixel and a second opening corresponding to the second pixel.

Abstract: An image sensor package including a PCB including bonding areas, an image sensor including bonding pads on edge portions thereof on the PCB, bonding wires connecting the bonding pads with the bonding areas, an insulating adhesion film attaching the bonding wires to the bonding pads on the edge portions of the image sensor, a heat spread pattern spaced apart from the bonding wires and the image sensor on the insulating adhesion film, a supporting holder spaced apart from the edge portions of the image sensor, encloses the image sensor, contacts a top surface of the heat spread pattern and the PCB, and includes a supporting portion at an upper portion thereof, and a transparent cover covering the image sensor on the supporting portion of the supporting holder and spaced apart from the top surface of the image sensor is provided.

Abstract: Provided is an image pickup element, including: condenser lenses made of a resin containing fine metal particles; photoelectric conversion elements formed in a silicon substrate and each configured to photoelectrically convert incident light that enter from an outside through corresponding one of the condenser lenses; and a protective film made of a silicon compound, the protective film being formed between the condenser lenses and the silicon substrate.

Abstract: A CMOS image sensor including a pixel including: a photodiode in series with a MOS transistor between a first reference potential and a sense node; a MOS transistor connecting the sense node to a second reference potential; and a third MOS transistor assembled as a source follower between the sense node and a read circuit, wherein the oxide thickness of the third transistor is smaller than that of the first and second transistors, the voltage difference between the first and second reference potentials is greater than the maximum voltage capable of being applied between two terminals of the third transistor, and the body or drain region of the third transistor is connected to a third reference potential in the range between the first and second potentials.

Abstract: A method of fabricating an image sensor is provided. The method may include preparing a substrate with first to third pixel regions, coating a first color filter layer on the substrate, sequentially forming a first sacrificial layer and a first protection layer to cover the first color filter layer, forming a first photoresist pattern on the first protection layer to be overlapped with the first pixel region, performing a first dry etching process using the first photoresist pattern as an etch mask to the first sacrificial layer and the first protection layer to form a first color filter, a first sacrificial pattern, and a first protection pattern sequentially stacked on the first pixel region, and selectively removing the first sacrificial pattern to separate the first protection pattern from the first color filter.

Abstract: The present technology includes: bonding a device formation side of a first substrate having a first device and a device formation side of a second substrate having a second device in opposition to each other; forming a protective film on at least an edge of the second substrate having the second device; and reducing a thickness of the first substrate.

Abstract: Disclosed is a manufacturing method of a semiconductor device including a step of attaching semiconductor wafers together, in which it is prevented that the bonding strength between the attached semiconductor wafers may be decreased due to a void caused between the two semiconductor wafers. Moisture, etc., adsorbed to the surfaces of the semiconductor wafers is desorbed by performing a heat treatment on the semiconductor wafers after cleaning the surfaces thereof with pure water. Subsequently, after a plasma treatment is performed on the semiconductor wafers, the two semiconductor wafers are attached together. The wafers are firmly bonded together by subjecting to a high-temperature heat treatment.

Abstract: An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, in an n-type semiconductor substrate, a p-type well as a p-type semiconductor region forming a part of a photodiode is formed and a gate electrode of a transfer transistor is formed. Then, after an n-type well as an n-type semiconductor region forming the other part of the photodiode is formed, a microwave is applied to the semiconductor substrate to heat the semiconductor substrate. Thereafter, a drain region of the transfer transistor is formed.

Abstract: An integrated circuit and a method of making the same. The integrated circuit includes a semiconductor substrate having a major surface. The integrated circuit also includes a thermal conductivity based gas sensor having an electrically resistive sensor element located on the major surface for exposure to a gas to be sensed. The integrated circuit further includes a barrier located on the major surface for inhibiting a flow of the gas across the sensor element.

Abstract: According to one embodiment, a memory device includes a first diffusion layer region on, a second diffusion layer region, a third diffusion layer region, a first gate electrode and a second gate electrode. The memory device also includes a first via contact group, a second via contact group and a variable resistance element. At least one of the plurality of first via contacts is electrically connected to the first diffusion layer region with one end and at least one of the plurality of second via contacts is electrically connected to the third diffusion layer region with one end. The variable resistance element being electrically a first interconnect layer.

Abstract: A white organic light emitting element, a white organic light emitting display device, and a method of manufacturing the white organic light emitting element are provided. The organic light emitting element includes a multi-layered emission layer structure. The multi-layered emission layer structure includes a first electroluminescent layer and a second electroluminescent layer that are arranged to overlap at first area of the white organic light emitting element. The lights from the first and second electroluminescent layers collectively form white light. Among the first and second electroluminescent layers, one of the EL layers is extended out to the second area of the white organic light emitting element. A plurality of color filter elements are used to filter the white light to generate colored lights at the corresponding sub pixel regions.

Abstract: In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented.

Abstract: Provided is a light-emitting device and an information processing device which include a light-emitting element mounted on a housing and an optical component detachable from the housing. The optical component is capable of condensing light emitted from the light-emitting element. This structure allows a user to select the emission of diffused light and condensed light by attaching or detaching the optical component.

Abstract: Disclosed herein is a display including: a pixel array part configured to include pixels that are arranged in a matrix, each having an electro-optical element, a write transistor for writing a video signal, a drive transistor for driving the electro-optical element based on the video signal written by the write transistor, and a holding capacitor connected between the gate and source of the drive transistor, wherein the holding capacitor includes a first electrode, a second electrode disposed to face one surface of the first electrode for forming a first capacitor, and a third electrode disposed to face the other surface of the first electrode for forming a second capacitor, and the first capacitor and the second capacitor are connected in parallel to each other electrically.

Abstract: An organic light emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a flexible substrate and a plurality of OLEDs. The flexibility substrate includes at least one curved portion. The OLEDs are positioned in every pixel area that is set on the flexible substrate and includes a pixel electrode, an organic emission layer, and a common electrode. At least one OLED that is positioned at a curved portion in the OLEDs is formed in a lens shape and concentrates light toward the center of a pixel area.

Abstract: An organic light-emitting diode (OLED) display having thin film transistors (TFTs) is disclosed. In one aspect, TFTs of the OLED display include a substrate and a first semiconductor layer formed over the substrate and including first channel, source, and drain regions and a lightly doped region between the first channel region and the first source and drain regions. The OLED display also includes a second semiconductor layer formed over the substrate and including second channel, source, and drain regions. The OLED display further includes first and second gate electrodes formed over the first semiconductor layer and a third gate electrode formed over the second semiconductor layer. The width of the second gate electrode is less than that of the first gate electrode and the lightly doped region overlaps a portion of the first gate electrode and does not overlap the second gate electrode.

Abstract: An embodiment of the invention provides a display panel, which includes a substrate having a pixel region and a peripheral region, a control element overlying the pixel region of the substrate, a conducting layer overlying the substrate in the peripheral region, a first insulating layer overlying the conducting layer in the peripheral region, wherein a ratio between an area of the first insulating layer and an area of the conducting layer in the peripheral region is between about 0.27 and 0.99, a lower electrode layer overlying the first insulating layer, and a second insulating layer overlying the lower electrode layer.

Abstract: A pixel structure, including a data line, a scan line, at least one active device, a first auxiliary electrode, and a light emitting device, is provided. The at least one active device is electrically connected with the data line and the scan line, and each active device includes a gate, a channel layer, a source, and a drain. The first auxiliary electrode is electrically insulated from the active device. The light emitting device is disposed above the first auxiliary electrode, wherein the light emitting device includes a first electrode layer, a light emitting layer, and a second electrode layer. The first electrode layer is electrically connected with the first auxiliary electrode. The light emitting layer is disposed on the first electrode layer. The second electrode layer is disposed on the light emitting layer, wherein the second electrode layer is electrically connected with the active device.

Abstract: A EL display device has EL display panel including the a display area where a pixel is arranged in matrix, and a wiring pattern formed in a circumferential portion of the display area and supplying voltage to a pixel. The EL display panel includes a flexible substrate having an electrode connected to a source signal line or a gate signal line arranged thereon. The flexible substrate includes an anode reinforcement wiring and a cathode reinforcement wiring which are electrically parallel to the wiring pattern.

Abstract: A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.

Abstract: A method including forming an oxide layer on a top of a substrate; forming a deep trench capacitor in the substrate; bonding a III-V compound semiconductor to a top surface of the oxide layer; and forming a III-V device in the III-V compound semiconductor.

Abstract: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.

Abstract: Provided is a semiconductor device having a structure with which a decrease in electrical characteristics that becomes more significant with miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film, a gate electrode overlapping with the first oxide semiconductor film, a first gate insulating film between the first oxide semiconductor film and the gate electrode, and a second gate insulating film between the first gate insulating film and the gate electrode. In the first gate insulating film, a peak appears at a diffraction angle 2? of around 28° by X-ray diffraction. A band gap of the first oxide semiconductor film is smaller than a band gap of the first gate insulating film, and the band gap of the first gate insulating film is smaller than a band gap of the second gate insulating film.

Abstract: A semiconductor chip has an n+-doped substrate, above which an n-doped epilayer having trenches is introduced, the trenches being filled with p-doped semiconductor material and in each case having a highly p-doped region at their top side, such that an alternating arrangement of n-doped regions having a first width and p-doped regions having a second width is present. A first metal layer functioning as an anode is provided on the front side of the chip and forms a Schottky contact with the n-doped epilayer and forms an ohmic contact with the highly p-doped regions. A second metal layer which represents an ohmic contact and functioning as a cathode is formed on the rear side of the semiconductor chip. A dielectric layer is provided between each n-doped region and an adjacent p-doped region.

Abstract: An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure.

Abstract: Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.

Abstract: An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by an insulating region. The insulating region is formed to includes at least one area in which the insulating region has two insulating extents that are mutually separated from each other by a separation region formed by a part of the substrate.