Abstract: Traditionally, time-lapse videos are constructed from images captured at given time intervals called “temporal points of interests” or “temporal POIs.” Disclosed herein are intelligent systems and methods of capturing and selecting better images around temporal points of interest for the construction of improved time-lapse videos. According to some embodiments, a small “burst” of images may be captured, centered around the aforementioned temporal points of interest. Then, each burst sequence of images may be analyzed, e.g., by performing a similarity comparison between each image in the burst sequence and the image selected at the previous temporal point of interest. Selecting the image from a given burst that is most similar to the previous selected image allows the intelligent systems and methods described herein to improve the quality of the resultant time-lapse video by discarding “outlier” or other undesirable images captured in the burst sequence around a particular temporal point of interest.

Abstract: A computing system processes a video recording to identify a plurality of motion events, each corresponding to a respective video segment along a timeline of the video recording. The computing system identifies at least one object in motion within a scene depicted in the video recording and stores a respective event mask for each event. The computing system receives a definition of a zone of interest within the scene. In response to receiving the definition, the computing system determines, for each motion event, whether the respective event mask of the motion event overlaps with the zone of interest by at least a predetermined overlap factor, and identifies one or more events of interest from the plurality of motion events, wherein the respective event mask of each identified event of interest is determined to overlap with the zone of interest by at least the predetermined overlap factor.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, detecting a first action at a first time during a first presentation of video content of a multimedia stream. The first action is coincident with a visual aspect of an event observable in the video content. A second action is detected at a second time during a second presentation of audio content of an audio stream, wherein the second action is coincident with an audible aspect of the event observable in a the second presentation of the audio content. A time difference is determined between the first time and the second time, wherein the first presentation of the video content and the second presentation of the audio content are synchronized based on the time difference. Other embodiments are disclosed.

Abstract: A computing system device with processor(s) and memory displays a video monitoring user interface on the display, the video monitoring user interface including a video feed from a camera located remotely from the client device in a first region of the video monitoring user interface and an event timeline in a second region of the video monitoring user interface, and the event timeline includes indicators corresponding to motion events previously detected by the camera. The computing system obtains an indication of a detected motion event and associates the detected motion event with a respective category. The computing system displays an indicator for the detected motion event on the event timeline with a display characteristic corresponding to the respective category.

Abstract: A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.

Abstract: A microelectronic package has terminals at a surface of a substrate having first and second half areas, each half area extending from a diagonal that bisects the first surface and a respective opposite corner of the first surface. Terminals for carrying data and address information in the first half area provide first memory channel access to a first memory storage array, and terminals for carrying data and address information in the second half area provide second memory channel access to a second memory storage array. The package may include first and second microelectronic elements overlying a same surface of the substrate which may be stacked in transverse orientations.

Abstract: In some examples, a memory device may have at least a first and a second memory array. In some cases, a portion of the bit cells of the first memory array may be coupled to first PMOS-follower circuitry and to second PMOS-follower circuitry. A portions of the bit cells of the second memory array may also be coupled to the second PMOS-follower circuitry and to third PMOS-follower circuitry. Additionally, in some cases, the portion of bit cells of both the first memory array and the second memory array may be coupled to shared preamplifier circuitry.

Abstract: A portable storage device is provided with a memory part, a free space detecting part, a vibration detecting part, a reporting part, and a controller. The memory part stores data. The free space detecting part detects a free space of the memory part. The vibration detecting part detects vibration. The reporting part reports the free space. The controller performs writing and reading of data for the memory part. If vibration is detected by the vibration detecting part, the controller causes the reporting part to report corresponding to the detection result of the free space of the memory part by the free space detecting part.

Abstract: An embodiment includes a system, comprising a first memory; a plurality of first circuits, wherein each first circuit is coupled to the memory; and includes a second circuit configured to generate a first output value in response to an input value received from the first memory; and an accumulator configured to receive the first output value and generate a second output value; and a controller coupled to the memory and the first circuits, and configured to determine the input values to be transmitted from the memory to the first circuits.

Abstract: Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.

Abstract: A method includes detecting, at a controller, a rate-of-change between first data traffic to be sent to a dynamic random access memory (DRAM) at a first time and second data traffic to be sent to the DRAM at a second time. The method also includes adjusting a data rate of the second data traffic in response to a determination that the rate-of-change satisfies a threshold.

Abstract: Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.

Abstract: It is proposed to determine a reference value on the basis of a plurality of half reference values stored in memory cells, wherein the plurality of half reference values are read from the memory cells, wherein a subset of half reference values is determined from the plurality of half reference values, and wherein the reference value is determined on the basis of the subset of half reference values.

Abstract: The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry.

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

Abstract: Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell.

Abstract: Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations.

Abstract: Systems and methods relate to providing a correct reference voltage for reading a resistive memory element such as a magnetoresistive random access memory (MRAM) bit cell. Two or more reference voltages are provided for each MRAM bit cell and a correct reference voltage is selected from the two or more reference voltages for reading the MRAM bit cell. The correct reference voltage meets sensing margin requirements for reading the MRAM bit cell and overcomes non-idealities and offset voltages in read circuitry for reading the MRAM bit cell. An indication of the correct reference voltage is stored in a non-volatile latch or other non-volatile programmable memory and provided to the read circuitry.

Abstract: Systems and methods for reducing a probability of read disturbance during a read operation on a resistive memory bit cell include a dual stage sensing scheme, which is used to reduce pulse widths of sensing currents for reading the resistive memory bit cell. During a first stage of the read operation on the resistive memory bit cell, a first sensing current is passed in a first direction through the resistive memory bit cell, and during a second stage of the read operation, a second sensing current is passed in an opposite, second direction through the resistive memory bit cell. Durations of the first and second stages are each equal to half of the duration of the read operation, which reduces pulse width of the first and second sensing currents. Probability of read disturbance occurring is limited to at most one of the first or second stages.

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

Abstract: In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet. During a normal write operation, the bits to the other state are written. Other aspects are described herein.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.

Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of reducing power consumption in such arrays.

Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.

Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.

Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: A multi-port hybrid full-swing/low-swing memory circuit in a static random access memory (SRAM) device comprises a first wordline driver that comprises a read wordline driver, a second wordline driver that comprises either a read wordline driver or a read/write wordline driver, a memory cell coupled to the first and second wordline drivers, a sense amplifier coupled to the memory cell, and a latch coupled to the memory cell. The memory circuit is capable of achieving high-speed low-swing or low-speed full-swing operations while avoiding the need for a large circuit area on an integrated circuit.

Abstract: Systems and methods include a static random-access memory (SRAM) bit cell circuit having an access transistor configured to pass a read current to a storage node, the access transistor including an access transistor back gate. The access transistor back gate is biased to enable selective current boosting of the read current during a read operation.

Abstract: Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

Abstract: An electronic device is disclosed that includes n memory cells, a replica memory array, and a sensing unit. Each of the n memory cells stores bit data, in which n is a positive integer. The replica memory array includes a first reference memory cell having a high logic state, a second reference memory cell having a low logic state, n?1 first pseudo reference memory cells having the low logic state, and n?1 second pseudo reference memory cells having the high logic state. The first reference memory cell and the n?1 first pseudo reference memory cells generate a first signal, and the second reference memory cell and the n?1 second pseudo reference memory cells generate a second signal. The sensing unit determines a logic state of the bit data of one of the n memory cells according to the first signal and the second signal.

Abstract: A memory cell based upon thyristors for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. Special circuitry provides lowered power consumption during standby.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

Abstract: A static RAM includes: a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines; a write driver connected between a high potential power source line, of which potential is higher than a reference potential, and a drive line; a column switch having transistor pairs which connect one of the plurality of bit line pairs, which is selected, to the write driver; and a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of writing of the memory cell, wherein a well of the transistor pairs of the column switch is connected to the drive line.

Abstract: A method for performing memory access includes: performing a plurality of sensing operations respectively corresponding to a plurality of different sensing voltages to generate a first digital value of a Flash cell of a Flash memory and a second digital value of the Flash cell of the Flash memory; using the first digital value and the second digital value to obtain soft information of a bit stored in the Flash cell; and using the soft information to perform soft decoding.

Abstract: A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current.

Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

Abstract: Methods for operating a non-volatile storage system are described. The non-volatile storage system includes a plurality of bit lines, a plurality of word line combs each comprising a plurality of word lines, and a plurality of resistance-switching memory elements. Each resistance-switching memory element is coupled between one of the bit lines and one of the word lines. The method includes calibrating a plurality of bias voltages for the word lines and bit lines based on estimates of data values stored in the resistance-switching memory elements.

Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.

Abstract: A method of operating a memory device includes determining a value of an operating current flowing through a selected first signal line, to which a selection voltage is applied, from among a plurality of first signal lines; dividing an array of memory cells into n blocks, n being an integer greater than 1, based on the value of the operating current; and applying inhibit voltages having different voltage levels corresponding to the n blocks to unselected ones of second signal lines included in the n blocks. Each of the unselected second signal lines is a pathway through which leakage current may potentially flow due to the operating current flowing through the selected first signal line and a memory cell addressed by the unselected second signal line and the selected first signal line.

Abstract: Memory modules, controllers, and electronic devices comprising memory modules are described. In one embodiment, a memory module comprises a nonvolatile memory and an interface to a volatile memory bus, at least one input power rail to receive power from a host platform, and a controller comprising logic, at least partially including hardware logic, to convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage. Other embodiments are also disclosed and claimed.

Abstract: A semiconductor memory device may include a plurality of memory chips stacked upon one another, and electrically coupled to one another through a plurality of first TSVs. The semiconductor memory device may include a plurality of second memory chips stacked separately from the first memory chips, and the plurality of second memory chips electrically coupled to one another through a plurality of second TSVs. The semiconductor memory device may include a plurality of external connection electrodes coupled to both to the first memory chips and the second memory chips. Wherein one of the first and second memory chips may be accessed in response to chip select signals inputted through the external connection electrodes.

Abstract: Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory to address individual memory units in the NAND memory can be identified. The defined number of address cycles in which to operate can be selected in order to address the individual memory units in the NAND memory. Either the memory controller or the NAND memory can be configured to operate at the selected number of address cycles where the individual memory units in the NAND memory are uniquely addressable using a multi die select (MDS).

Abstract: Techniques are provided for more accurately programming memory cells by reducing program noise caused by charge loss in a programming pass in which the number of verify tests varies in different program loops. In an nth program loop, at least one programming characteristic is modified based on the number (N) of data states which were subject to verify tests in the n?1st program loop. For example, a reduced step size or pulse duration, or an elevated bit line voltage (Vbl) can be used. The reduction in the step size or pulse duration, or the increase in Vbl, is proportional to N. The modification of the at least one programming characteristic results in a slowdown of the programming of the memory cells so that program noise is reduced.

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming memory cells which share a data storage layer; performing a first strong program operation on first memory cells, arranged in a checker board pattern among the memory cells; performing a first annealing process after the first strong program operation; performing a second strong program operation on second memory cells arranged in a reverse checker board pattern among the memory cells, and performing a slight program operation on the first memory cells; and performing a second annealing process after the second strong program operation and the slight program operation.

Abstract: According to an embodiment, an operation method for a memory device which has a first memory element and a second memory element respectively provided on both sides of a semiconductor member includes applying a first potential on the second word line to write a second data to the second memory and applying a second potential on the first word line to write the first data to the first memory. The first potential increases by a first step voltage and the second potential increases by a second step voltage.

Abstract: Apparatus and methods implemented therein, in response to receiving an indication to program data to both a primary and secondary memory page determine whether a folding operation is in progress. In response to determining that the folding operation is in progress, programming of the data is delayed until completion of the folding operation. In response to determining the completion of the folding operation, data is programmed to the primary memory page and secondary memory page.

Abstract: A hierarchical-GBL/LBL NAND array with a plurality of LG and MG groups in either orthogonal BL/CSL scheme or parallel BL/SL scheme including a plurality of block-decoders with a shared self-timed delay control circuit and a plurality of fully-shielding dynamic CACHE registers made of 2 local broken metal lines within the array and DRAM-like SA is provided. Each DCR capacitor is flexibly expandable by connecting multiple CLGs made by the local broken metal lines of the LGs to form a CMG of a larger MG. Based on the NAND array, multiple randomly selected WLs in multiple random blocks within multiple random LGs within one MG can be selected on basis of one WL per block per LG for performing an ABL pipeline and concurrent SLC program without verification, and on basis of one WL per block per MG for performing an ABL-like or HBL pipeline and concurrent SLC read.