Abstract: A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.

Abstract: The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract: A method of manufacturing a Fin-FET device includes forming a plurality of fins in a substrate, which the substrate includes a center region and a periphery region surrounding the center region. A gate material layer is deposited over the fins, and the gate material layer is etched with an etching gas to form gates, which the etching gas is supplied at a ratio of a flow rate at the center region to a flow rate at the periphery region in a range from 0.33 to 3.

Abstract: A method of manufacturing a semiconductor device includes forming a first metal containing a first conductivity-type impurity above a substrate provided with a first conductivity-type impurity region containing a first conductivity-type impurity and a second conductivity-type impurity region containing a second conductivity-type impurity; and forming a metal silicide containing the first metal by selectively causing, by thermal treatment, a reaction between the first metal and silicon contained in the substrate in the first conductivity-type impurity region.

Abstract: There is provided a technique for easily inspecting the modification state of a film in a semiconductor substrate. A modification processing device modifies a film by irradiating a semiconductor substrate with pulsed light emitted from a light irradiation part. The modification processing device includes an electromagnetic wave detection part for detecting an electromagnetic wave pulse including a millimeter wave or a terahertz wave radiated from the semiconductor substrate in response to the irradiation with the pulsed light. The modification processing device further includes a modification determination part for determining the modification state, based on the intensity of the electromagnetic wave pulse.

Abstract: A method including emitting a terahertz beam from a light source at a layer of molding material; detecting a reflectance of the beam; and determining a thickness of the layer of molding material. A system including a panel supporter operable to support a panel including a plurality of substrates arranged in a planar array; a light source operable to emit a terahertz beam at a panel on the panel supporter; a detector operable to detect a reflection of a terahertz beam emitted at a panel; and a processor operable to determine a thickness of a material on the panel based on a time delay for an emitted terahertz beam to be detected by the detector.

Abstract: A method of manufacturing a semiconductor package includes providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad and a second test pad, each of the connection pad, the first test pad and the second test pad respectively electrically connected to the circuit pattern, evaluating electrical characteristics of the semiconductor chip by applying a first test voltage to the first test pad and a second test voltage to the second test pad, the second test voltage being higher than the first test voltage, and electrically disconnecting the second test pad from the circuit pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a film along a surface of a semiconductor substrate in a first state having a first surface area by supplying a reaction gas at a first flow rate. The method further includes detecting a transition from the first state to a second state having a second surface area different from the first surface area. The method still further includes forming a film by changing the flow rate of the reaction gas from the first flow rate to a second flow rate different form the first flow rate after detecting the transition from the first state to the second state.

Abstract: The present invention provides an array substrate, which includes a plurality of pixel units, each pixel unit includes a thin film transistor, a pixel electrode, a common electrode and a passivation layer, the thin film transistor includes an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode and the pixel electrode are connected, the passivation layer is disposed on the active layer, the source electrode, the drain electrode and the pixel electrode, the common electrode is disposed above the pixel electrode with the passivation layer therebetween, a test electrode is disposed on the active layer and under the passivation layer, the test electrode is electrically insulated from the gate electrode, the source electrode and the drain electrode. Correspondingly, a method for fabricating and a method for testing the array substrate, and a display device including the array substrate are provided.

Abstract: A packaged semiconductor device comprising a stack including a die comprising a functional circuit, and a cap which is wafer bonded to the die for protecting the functional circuit as well as a mold component for packaging the stack. At least the cap and/or the die comprises at least one groove at least partially in contact with the mold component, for increasing adhesion of the mold component to the stack. A corresponding method for manufacturing such a packaged device also is described.

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package substrate; a semiconductor chip mounted on the package substrate and electrically connected to the package substrate; a first protective layer covering the semiconductor chip and having flexibility controlled by at least one of a material type, a thickness, a material composition ratio and viscosity of the first protective layer; and a second protective layer arranged on the first protective layer and having flexibility controlled by at least one of a material type and a thickness of the second protective layer, wherein the first protective layer comprises a first binder resin, a first hardener, and a first hardening catalyst. According to the semiconductor package of the inventive concept, protective layers protecting the semiconductor chip have flexibility, and thus, the semiconductor package may be bent.

Abstract: A method of fabricating a package structure is provided. The method includes providing a carrier having two opposing surfaces, forming dielectric bodies on the two surfaces of the carrier, respectively, each of the dielectric bodies having a wiring layer embedded therein and a conductive layer formed on the wiring layer, and removing the carrier. Therefore, the wiring layers, the conductive layers and the dielectric bodies are formed on the two surfaces of the carrier, respectively, and the production yield is thus increased. The present invention further provides the package structure thus fabricated.

Abstract: An epoxy resin composition for encapsulating a semiconductor device and a semiconductor package, the composition including an epoxy resin; a polyorganosiloxane resin represented by Formula 3, below; a curing agent; a curing accelerator; and an inorganic filler:

Abstract: A method forming packaged semiconductor devices includes providing a completed semiconductor package having a die with bond pads coupled to package pins. Sensor precursors including an ink and a liquid carrier are additively printed directly on the die or package to provide precursors for electrodes and a sensing material between the sensor electrodes. Sintering or curing removes the liquid carrier such that an ink residue remains to provide the sensor electrodes and sensing material. The sensor electrodes electrically coupled to the pins or bond pads or the die includes a wireless coupling structure coupled to the bond pads and the method includes additively printing an ink then sintering or curing to form a complementary wireless coupling structure on the completed semiconductor package coupled to the sensor electrodes so that sensing signals sensed by the sensor are wirelessly transmitted to the bond pads after being received by the wireless coupling structure.

Abstract: A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.

Abstract: An electronic device includes a first electronic unit, a second electronic unit disposed adjacent to the first electronic unit, and a heat radiating unit. The second electronic unit has a first portion and a second portion that is closer to the first electronic unit than the first portion. The heat radiating unit is disposed such that heat generated in the second portion of the second electronic unit is directed towards the first portion of the second electronic unit and from the first portion towards an outside of the electronic device.

Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract: A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.

Abstract: Some examples relate to an electronic system that includes a substrate and a non-volatile memory (NVM) mounted on the substrate. The electronic system further includes a Peltier device mounted to a portion of the NVM to provide on demand short term cooling to the NVM during operation of the NVM. Other examples relate to a method that includes operating a plurality non-volatile memories (NVMs) that is part of an electronic system, and using a plurality of Peltier devices to provide on demand short term cooling to a portion of each NVM.

Abstract: A method and an apparatus for cooling a semiconductor device. The method comprises the steps of contacting a surface of the semiconductor device with respective end portions of an array of contact elements thermally coupled to a cooling fluid, and disposing a flexible, heat conductive sheet between the respective end portions of the contact elements and the surface of the semiconductor device for transferring heat generated in the semiconductor device to the cooling fluid via the sheet and the contact elements.

Abstract: The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Abstract: A quad-flat non-lead package structure includes a film layer, a conducting layer, a die, an encapsulant, and a plurality of metal bumps. The film layer has a plurality of through holes. A pad of the conducting layer and conducting wirings are disposed at the film layer but are not connected to each other. The conducting wirings are disposed at the through holes, respectively. The die is fixedly disposed at the pad and electrically connected to the conducting wirings. The encapsulant covers the conducting layer and the die. The metal bumps are disposed in the through holes, respectively, each have one end electrically connected to a corresponding one of the conducting wirings, and each have the other end protruding from a corresponding one of the through holes. Accordingly, the quad-flat non-lead package structure features reduced likelihood of pin disconnection and enhanced adhesiveness required for surface-mount technology.

Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.

Abstract: A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.

Abstract: A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.

Abstract: An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.

Abstract: To reduce a mounting area while securing a mounting strength of a semiconductor device, a power transistor includes a chip mounting portion, a semiconductor chip, a plurality of leads, and a sealing body. An outer lead portion in each of the plurality of leads includes a first portion protruding from a second side surface of the sealing body in a first direction, a second portion extending in a second direction intersecting with the first direction, and a third portion extending in a third direction intersecting with the second direction. Furthermore, a length of the third portion in the third direction of the outer lead portion is shorter than a length of the first portion in the first direction.

Abstract: A non-insulated power semiconductor module may include a housing, at least a pair of lead frames fixedly seated in the housing and having a plurality of power semiconductor chips mounted on surfaces thereof, and an insulation member disposed between the housing and the pair of lead frames.

Abstract: A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals.

Abstract: An apparatus for a manufacturing semiconductor device including a plate member and a joint member. The apparatus includes a plate-type tool having the plate member mounted thereon, a first fixing tool and a second fixing tool having an inclined surface for abutting an upper edge of an end part in a width direction of plate member. The second fixing tool is fixed onto the plate-type tool adjacent to the end part. An ultrasonic horn applies ultrasonic vibration in the width direction of plate member while pressing the joint member toward the plate member.

Abstract: Methods for forming a semiconductor layer, such as a metal 1 layer, having minimum width features separated by a distance greater than a minimum pitch, and the resulting devices are disclosed. Embodiments may include determining a first shape and a second shape having a minimum width within a semiconductor layer, wherein a distance between the first shape and the second shape is greater than a minimum pitch, determining an intervening shape between the first shape and the second shape, and designating a dummy shape within the intervening shape, wherein the dummy shape is at the minimum pitch from the first shape.

Abstract: A device comprises a first protection layer over sidewalls and a bottom of a first trench in a first dielectric layer, a first barrier layer over the first protection layer, a first metal line in the first trench, a second protection layer over sidewalls and a bottom of a second trench in the first dielectric layer, a second barrier layer over the second protection layer, a second metal line in the first trench, an air gap between the first trench and the second trench and a third protection layer over sidewalls of a third trench in the first dielectric layer, wherein the first protection layer, the second protection layer and the third protection are formed of a same material.

Abstract: A semiconductor substrate according to some examples of the disclosure may include a substrate with a cavity in a top surface of the substrate, a plurality of cavity interconnections embedded below a bottom surface of the cavity and extending to a bottom surface of the substrate, and a plurality of side interconnections to either side of the cavity extending from the top surface of the substrate to the bottom surface of the substrate. Each of the plurality of side interconnections may include an electrically conductive stop etch layer in the same horizontal plane as the bottom of the cavity.

Abstract: A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the conductive line and the via, and the dielectric material and the via are planarized.

Abstract: A semiconductor device includes a base body, an insulating layer, first contacts and a first wiring. The insulating layer is disposed above the base body. The first contacts are disposed in the insulating layer. The first contacts are in contact with the base body. The first wiring is disposed around the first contacts. The first wiring has a lower height than the first contacts have. The first wiring includes convex portions in a part of a bottom portion thereof.

Abstract: Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.

Abstract: A semiconductor package according to some examples of the disclosure may include a base with a first redistribution layer on one side, first and second side by side die attached to the base on an opposite side from the first redistribution layer, an interposer attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias extending from the first and second die to a second redistribution layer on a surface of the package opposite the first redistribution layer, and a plurality of package vias extending through the package between the first and second redistribution layers.

Abstract: Disclosed herein is a device comprising a first redistribution layer (RDL) having first lands disposed on a bottom surface of the first RDL and active contact pads disposed on a top surface of the first RDL. The first RDL electrically connects the first lands to the active contact pads. A molding compound layer is disposed on the top surface of the first RDL. Active vias extend through the molding compound layer and are in electrical contact with the active contact pads. Dummy vias extending through the molding compound layer. Top surfaces of the active vias and top surfaces of the dummy vias are substantially planar with a top surface of the molding compound layer, and the dummy vias are electrically insulated from the active vias and the first lands.

Abstract: An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Abstract: A method is provided for fabricating a photolithography alignment mark structure. The method includes providing a substrate; thrilling a first grating, a second grating, a third grating and a fourth grating in the substrate; forming a photoresist layer on a surface of the substrate; obtaining a first alignment center along a first direction and a second alignment center along a second direction based on the first grating and the fourth grating, respectively; providing a mask plate having a fifth grating pattern and a sixth grating pattern; aligning the mask plate with the substrate by using the first alignment center as an alignment center along the first direction and the second alignment center as an alignment center along the second direction; reproducing the fifth grating pattern and the sixth grating pattern in the photoresist layer: and forming a fifth grating and a sixth grating on the substrate by removing a portion of photoresist layer.

Abstract: A stacked optoelectronic packaged device includes a bottom die having a top surface including bottom electrical traces and a light source die coupled to ?1 bottom electrical traces. A first cavity die is on the bottom die. An optics die is on the first cavity die and a second cavity die on the optics die. A mounting substrate is on the second cavity die including top electrical traces. A photodetector die is optically coupled to receive light from the light source. The bottom and top electrical traces are both positioned substantially symmetrically on sides of a mirror plane so that when conducting equal and opposite currents a first magnetic field emanating from the first side and a second magnetic field emanating from the second side cancel one another to provide a reduction in magnetic flux density by more than 50% at one or more die locations on the optics die.

Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.

Abstract: Shielded radio-frequency (RF) module having reduced area. In some embodiments, an RF module can include a packaging substrate configured to receive a plurality of components, and a plurality of shielding wirebonds implemented on the packaging substrate and configured to provide RF shielding functionality for one or more regions on the packaging substrate. The packaging substrate can include a first area associated with implementation of each shielding wirebond. The RF module can further include one or more devices mounted on the packaging substrate. The packaging substrate can further include a second area associated with mounting of each of the one or more devices. Each device can be mounted with respect to a corresponding shielding wirebond such that the second area associated with the device overlaps at least partially with the first area associated with the corresponding shielding wirebond.

Abstract: In an embodiment, an apparatus includes a packaging substrate and a die on the packaging substrate. The die includes an integrated passive device and a contact providing an electrical connection to the integrated passive device. A conductive trace of the packaging substrate is in an electrical path between the contact of the die and a ground potential. Such an integrated passive device and conductive trace can be included in a matching network configured to receive an amplified radio frequency signal from a power amplifier, for example. The packaging substrate can be, for example, a laminate substrate.

Abstract: Aspects of this disclosure relate to a termination circuit configured to mitigate crosstalk from a radio frequency (RF) input/output (I/O) path to a second I/O path, such as a digital I/O path. Such crosstalk can be due to coupling between adjacent bond wires, for example. The termination circuit can include a low impedance loss path, such as a series RC shunt circuit. According to certain embodiments, an electrostatic discharge (ESD) protection circuit can be in parallel with the termination circuit.

Abstract: A method of making a semiconductor package can include forming a plurality of redistribution layer (RDL) traces disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die. The method can include disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces. The method can also include forming a via through the encapsulant material to expose at least one of the plurality of RDL traces, forming an electrical interconnect disposed within the via and coupled to the at least one RDL trace, and singulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 ?m of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die.

Abstract: A semiconductor device includes a through electrode penetrating a substrate such that a first end portion of the through electrode protrudes from a first surface of the substrate, a passivation layer covering the first surface of the substrate and a sidewall of the first end portion of the through electrode, a bump having a lower portion penetrating the passivation layer and coupled to the first end portion of the through electrode, and a lower metal layer disposed between the bump and the first end portion of the through electrode. The lower metal layer extends onto a sidewall of the bump and has a concave shape.

Abstract: An embodiment is a structure comprising a die having a pad on a surface and an encapsulant at least laterally encapsulating the die. The pad is exposed through the encapsulant. The structure further includes a first dielectric layer over the encapsulant and the die, a first conductive pattern over the first dielectric layer, and a second dielectric layer over the first conductive pattern and the first dielectric layer. The first dielectric layer and the second dielectric layer have a first opening to the pad of the die. The structure further includes a second conductive pattern over the second dielectric layer and in the first opening. The second conductive pattern adjoins a sidewall of the first dielectric layer in the first opening and a sidewall of the second dielectric layer in the first opening.

Abstract: A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon via (TSV) extending through the semiconductor substrate, and a copper pad electrically connected to the TSV and having a coupling side. The semiconductor device further includes a copper element that projects away from the coupling side of the copper pad. In another embodiment, a bonded semiconductor assembly comprises a first semiconductor substrate with a first TSV and a first copper pad electrically coupled to the first TSV, wherein the first copper pad has a first coupling side. The bonded semiconductor assembly further comprises a second semiconductor substrate, opposite to the first semiconductor substrate, the second semiconductor substrate comprising a second copper pad having a second coupling side. A plurality of copper connecting elements extend between the first and second coupling sides of the first and second copper pads.

Abstract: There are provided are an adhesive composition that keeps storage stability and further gives a cured product wherein metallic bonds are formed in the state that the cured product wets its components and is satisfactorily spread between the components (or parts), thereby turning excellent in adhesive property, electroconductivity, and reliability for mounting such as TCT resistance or high-temperature standing resistance; an electronic-component-mounted substrate using the same; and a semiconductor device. The adhesive composition comprises electroconductive particles (A) and a binder component (B), wherein the electroconductive particles (A) include a metal (a1) having a melting point equal to or higher than the reflow temperature and containing no lead, and a metal (a2) having a melting point lower than the reflow temperature and containing no lead, and the binder component (B) includes a thermosetting resin composition (b1) and an aliphatic dihydroxycarboxylic acid (b2).