Abstract: A method is for hydrophobization of a surface of a silicon-containing film by atomic layer deposition (ALD), wherein the surface is subjected to atmospheric exposure. The method includes: (i) providing a substrate with a silicon-containing film formed thereon; and (ii) forming on a surface of the silicon-containing film a hydrophobic atomic layer as a protective layer subjected to atmospheric exposure, by exposing the surface to a silicon-containing treating gas without exciting the gas. The treating gas is capable of being chemisorbed on the surface to form a hydrophobic atomic layer thereon.

Abstract: According to one embodiment, a substrate processing apparatus includes a first liquid supplier, a second liquid supplier, and a controller. The first liquid supplier supplies a substrate with a sulfuric acid solution having a first temperature equal to or higher than the boiling point of hydrogen peroxide water. The second liquid supplier supplies a surface to be treated of the substrate with a mixture of sulfuric acid solution and hydrogen peroxide water having a second temperature lower than the first temperature. The controller controls the first liquid supplier to supply the sulfuric acid solution so as to heat the substrate to the boiling point of hydrogen peroxide water or higher. When the temperature of the substrate becomes equal to or higher than the second temperature, the controller controls the first liquid supplier to stop supplying the sulfuric acid solution and controls the second liquid supplier to supply the mixture.

Abstract: An exemplary embodiment of the present invention provides a method of depositing of a film on semiconductor wafers. In a first step, a film thickness of 3 um or less is deposited on wafers accommodated in a wafer boat in a vertical furnace at a deposition temperature of the furnace while a deposition gas is flowing. During the first step, the temperature may be held substantially constant. In a second step, a temperature deviation or variation of at least 50° C. from the deposition temperature of the first step is applied and the furnace temperature is returned to the deposition temperature of the first step while the flow of the deposition gas is stopped. The first and second steps are repeated until a desired final film thickness is deposited.

Abstract: Methods are described for forming a flowable low-k dielectric film on a patterned substrate. The film may be a silicon-carbon-oxygen (Si—C—O) layer in which the silicon and carbon constituents come from a silicon and carbon containing precursor while the oxygen may come from an oxygen-containing precursor activated in a remote plasma region. Shortly after deposition, the silicon-carbon-oxygen layer is treated by exposure to a hydrogen-and-nitrogen-containing precursor such as ammonia prior to curing. The treatment may remove residual moisture from the silicon-carbon-oxygen layer and may make the lattice more resilient during curing and subsequent processing. The treatment may reduce shrinkage of the silicon-carbon-oxygen layer during subsequent processing.

Abstract: A method of forming a dielectric layer includes the following steps. First of all, a high-k dielectric layer is formed on a substrate. Next, a nitridation process is performed on the high-k dielectric layer immediately after the high-k dielectric layer is formed. Then, a post-nitridation process is performed on the high-k dielectric layer after the nitridation process is performed.

Abstract: A method for making semiconductor devices may include forming a phosphosilicate glass (PSG) layer on a semiconductor wafer, with the PSG layer having a phosphine residual surface portion. The method may further include exposing the phosphine residual surface portion to a reactant plasma to integrate at least some of the phosphine residual surface portion into the PSG layer. The method may additionally include forming a mask layer on the PSG layer after the exposing.

Abstract: The invention is for fabricating large-area, thickness-modulated MoS2, varying from single to few layer MoS2 films on various substrates using a combination of magnetron sputtering followed by chemical vapor deposition. The thickness dependent energy bandgap engineering and surface induced polarity change is disclosed.

Abstract: Disclosed is a method for growing a nitride-based semiconductor with high quality, the method including: forming a first mask layer on a substrate and forming a second mask layer on the first mask layer; performing dry etching on the first mask layer and the second mask layer to form an opening in which a part of the substrate is exposed; performing selective wet etching on the first mask layer in the opening to form a recess in which a part of the substrate is exposed; depositing a third mask layer in the recess; and growing a nitride-based semiconductor from the exposed part of the substrate on sides of the third mask layer and expanding the growth via the opening.

Abstract: Methods and materials for making a semiconductor device are described. The method includes providing a substrate, forming a middle layer comprising a floating additive polymer (FAP) at an upper surface of the middle layer, the FAP chemically bound to a photoacid generator (PAG) and including a fluorine-containing material over the substrate, forming a photoresist layer over the middle layer, exposing the photoresist layer and the middle layer to an exposure energy to produce acid bound to the middle layer in the exposed areas of the middle layer, and developing the photoresist layer.

Abstract: In producing a MOS silicon carbide semiconductor device, after a first heat treatment (oxynitride) is performed in an oxidation atmosphere including nitrous oxide or nitric oxide, a second heat treatment including hydrogen is performed, whereby in the front surface of a SiC epitaxial substrate, a gate insulating film is formed. A gate electrode is formed and after an interlayer insulating film is formed, a third heat treatment is performed to bake the interlayer insulating film. After contact metal formation, a fourth heat treatment is performed to form a reactive layer of contact metal and the silicon carbide semiconductor. The third and fourth heat treatments are performed in an inert gas atmosphere of nitrogen, helium, argon, etc., and a manufacturing method of a silicon carbide semiconductor device is provided achieving a normally OFF characteristic and lowered interface state density.

Abstract: The method for performing activation of n-type or p-type dopants in a GaN-base semiconductor includes the following steps: providing a substrate including a GaN-base semiconductor material layer, performing the following successive steps at least twice: implanting electric dopant impurities in the semiconductor material layer, performing heat treatment so as to activate the electric dopant impurities in the semiconductor material layer, a cap layer covering the semiconductor material layer when the heat treatment is performed, two implantation steps of electric dopant impurities being separated by a heat treatment step.

Abstract: The invention relates to a post-activation method of dopants in a doped and activated GaN-base semiconductor layer, including the following successive steps: providing said doped and activated substrate, eliminating a part of the semiconductor material layer.

Abstract: A method of forming a semiconductor device includes forming a gate stack over a first portion of a source and a first portion of a drain. The method includes depositing a first cap layer comprising silicon over a second portion of the source and depositing a second cap layer comprising silicon over a second portion of the drain. The method includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer. The method includes annealing the semiconductor device until all of the silicon in the first and second cap layers reacts with metal from the metal layer, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source, and the drain. Annealing the semiconductor device includes forming a salicide layer having a germanium concentration less than 3% by weight.

Abstract: A method for forming a semiconductor device includes forming a conductive structure of a silicon material on a substrate and forming a planarized dielectric layer adjacent the conductive structure. The method also includes removing a portion of the dielectric layer to expose a top portion of the conductive structure and removing an outer portion of the exposed top portion of the conductive structure such that the top portion of the gate structure has a narrower width than the unexposed portion. The method further includes forming a metal layer over the exposed portion of the gate structure and a top surface of the dielectric layer, and forming a silicide layer over the top portion of the conductive structure. The width of the silicided top portion of the conductive structure is substantially the same as the width of the bottom portion of the conductive structure.

Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.

Abstract: According to various embodiments, a method for processing a carrier may include: performing a dry etch process in a processing chamber to remove a first material from the carrier by an etchant, the processing chamber including an exposed inner surface including aluminum and the etchant including a halogen; and, subsequently, performing a hydrogen plasma process in the processing chamber to remove a second material from at least one of the carrier or the inner surface of the processing chamber.

Abstract: Embodiments of the invention describe a method for controlling etching in pitch doubling. According to one embodiment, the method includes receiving a substrate having a pattern thereon defined by spacers formed on sidewalls of a plurality mandrels, and transferring the pattern defined by the spacers into the substrate using a plasma etch process that etches the mandrels and the substrate, the transferring forming first recessed features in the substrate below the mandrels and second recessed features in the substrate between the mandrels, where the plasma etch process utilizes an etching gas containing O2 gas, and the relative amount of O2 gas in the etching gas is selected to control the depth of the first recessed features relative to the depth of second recessed features. According to another embodiment, the substrate contains a mask layer thereon and a pattern on the mask layer.

Abstract: Methods that enable fin cut at very tight pitch are provided. After forming a first set of paired sidewall image transfer (SIT) spacers and a second set of paired SIT spacers composed of different materials, portions of the first set of the paired SIT spacers can be selectively removed without adversely affecting the second set of the paired SIT spacers, even portions of both sets of the paired SIT spacers are exposed by the cut mask due to the different etching characteristics of the different materials.

Abstract: In a substrate processing apparatus, chemical-solution processing is performed by supplying a chemical solution to the upper surface of a substrate in a state where a top plate is located at a first relative position. Also, cleaning processing is performed by supplying a cleaning liquid to the upper surface of the substrate in a state where the top plate is located at a second relative position closer to the substrate than the first relative position is. Moreover, dry processing is performed on the substrate by rotating the substrate in a state where the top plate is located at a third relative position closer to the substrate than the second relative position is. This allows a chemical atmosphere above the substrate to be efficiently removed during the cleaning processing. Consequently, the occurrence of particles due to the chemical atmosphere above the substrate can be suppressed during the dry processing.

Abstract: The invention relates to a method for producing a multilevel microelectronic structure, comprising at least: the formation of a first layer (236); the production of at least one second layer (239) at least partially covering the first layer (236); the production of at least one microelectronic pattern (220, 220a, 220b) on or in the second layer (239); characterised in that: the second layer (239) is formed so as to generate a mechanical stress in it; the first layer (236) forms for the second layer (239) a support preventing relaxation of said stress; and in that it comprises at least the following steps performed after the production of at least one microelectronic pattern (220, 220a, 220b), elimination of at least part of the first layer (236), thus making it possible to relax at least part of the mechanical stress on the second layer (239) so that at least a portion of the second layer (239) covering said eliminated part of the first layer (236) moves; fixing the moved portion of the second lay

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than an exposed silicon nitride portion. The inclusion of the oxygen-containing precursor may suppress the silicon nitride etch rate and result in unprecedented silicon oxide etch selectivity.

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than a second exposed portion. The inclusion of the oxygen-containing precursor may suppress the second exposed portion etch rate and result in unprecedented silicon oxide etch selectivity.

Abstract: A method of making crystal semi-conducting material-based elements, including providing a support having amorphous semi-conducting material-based semi-conducting elements, the support being further provided with one or more components and with a reflective protective area configured so as to reflect a light radiation in a given wavelength range, exposing the element(s) to a laser radiation emitting in the given wavelength range so as to recrystallize the elements, the reflective protective area being arranged on the support relative to the elements and to the components so as to reflect the laser radiation and protect the components from this radiation.

Abstract: The present invention provides a technology that includes: forming an intermediate film on a substrate having an insulating film formed thereon; and forming a metal film on the intermediate film. The intermediate film is more susceptible to oxidation than the metal film and has a smaller thickness than the metal film.

Abstract: A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.

Abstract: The method for performing activation of p-type dopants in a GaN-base semiconductor comprises a first step consisting in providing a substrate comprising (i) a GaN-base semiconductor material layer comprising p-type electric dopant impurities, (ii) a cap block devoid of any silicon-base compound, in contact with the semiconductor material layer, and (iii) a silicon-base covering layer covering the cap block. The method comprises a second heat treatment step at a temperature of more than 900° C. so as to activate the p-type electric dopant impurities in the semiconductor material layer.

Abstract: A multigate transistor device such as a fin-shaped field effect transistor (FinFET) is fabricated by applying a self-aligned diffusion break (SADB) mask having an opening positioned to expose an area of at least one portion of at least one gate stripe designated as at least one tie-off gate in the multigate transistor device and removing the tie-off gate through the opening of the SADB mask to isolate transistors adjacent to the tie-off gate.

Abstract: Provided is a configuration capable of suppressing a variation in characteristics of transistor. The configuration includes: a process chamber; a gas supply unit configured to supply a hard mask forming gas into the process chamber; a substrate support table configured to support a substrate Wn of an nth lot having a film to be etched formed thereon; a heater embedded in the substrate support table; and a controller configured to control a temperature distribution of the heater based on an etching information of a substrate Wm of an mth lot processed prior to the nth lot.

Abstract: A method for forming a semiconductor device includes providing a semiconductor structure which has a substrate and N sub-stack structures numbered from 1 to N, where N is an integer. Each sub-stack structure includes two sub-stacks, and a mask layer overlying the N sub-stack structures. The method also includes repeatedly removing a portion of the mask layer and removing exposed portions of the sub-stack structures to form a first stepped structure, and forming first spacers on sidewalls of the mask layer and the sub-stack structures in the stepped structure, each spacer covering a portion of the exposure portions of the sub-stack structures. The method further includes using the mask layer and the first spacers as masks to remove exposed portions of an upper sub-stack in the first stepped structure, and removing the mask layer and the spacers to form a second stepped structure.

Abstract: A process for a substrate having a component-disposing area is provided, and includes the following steps. A core layer including a first surface, a metallic layer and a component-disposing area is provided. The metallic layer is disposed on the first surface and patterned to form a patterned metallic layer including pads located in the component-disposing area. A first dielectric layer is formed on the first surface and covers the patterned metallic layer. A laser-resistant metallic pattern is formed on the first dielectric layer and surrounds a projection area of the first dielectric layer. A release film is disposed on the projection area and covers a portion of the laser-resistant metallic pattern within the projection area. A second dielectric layer is formed on the first dielectric layer and covers the release film and the laser-resistant metallic pattern. A first open hole and a plurality of second open holes are formed.

Abstract: A processing liquid is supplied from a supply tank to a processing liquid nozzle of a processing unit, and the processing liquid is supplied from the processing liquid nozzle to a substrate. The processing liquid used in the processing unit is collected and selectively supplied to first and second replenishment tanks. In a period in which the used processing liquid is supplied to the first replenishment tank, the supply tank is replenished with the processing liquid in the second replenishment tank, and the processing liquid in the first replenishment tank circulates while being heated by a heater. In a period in which the used processing liquid is supplied to the second replenishment tank, the supply tank is replenished with the processing liquid in the first replenishment tank and the processing liquid in the second replenishment tank circulates while being heated by the heater.

Abstract: The method includes holding a substrate horizontally with a holding and rotating mechanism; introducing processing liquid from a fluid introduction portion of, in a processing liquid pipe in which a processing liquid nozzle having a discharge port at a tip end is provided at one end, the other end of the processing liquid pipe into the processing liquid pipe so as to discharge the processing liquid from the discharge port toward the substrate; introducing, after stopping the processing liquid discharge step, a gas from the fluid introduction portion into the processing liquid pipe so as to extrude the processing liquid within the processing liquid pipe and within the processing liquid nozzle outwardly; and stopping, after starting the introduction of the gas, the introduction of the gas into the processing liquid pipe with the processing liquid being left within the processing liquid pipe and/or the processing liquid nozzle.

Abstract: Disclosed is a substrate liquid processing method. The method includes: supplying a first processing liquid to a central portion of a substrate at a first flow rate by a first nozzle while rotating the substrate using a substrate holding unit; supplying a second processing liquid to a location between the central portion and an outer circumferential end of the substrate by a second nozzle while supplying the first processing liquid to the central portion of the substrate at the first flow rate; and changing the flow rate of the first processing liquid supplied from the first nozzle to a second flow rate lower than the first flow rate, so as to continue forming of the liquid film on the overall surface of the substrate while supplying the second processing liquid by the second nozzle to the substrate that is formed with a liquid film on the overall surface thereof.

Abstract: Provided are an initiator and a method for debonding a wafer supporting system. The initiator for debonding a wafer supporting system includes a rotation chuck having an upper surface on which a wafer supporting system (WSS), which includes a carrier wafer, a device wafer, and a glue layer for bonding the carrier wafer and the device wafer to each other, is seated to rotate the wafer supporting system, a detecting module detecting a height and a thickness of the glue layer and a laser module generating a fracture portion on the glue layer through irradiating a side surface of the glue layer with a laser on the basis of the height and the thickness of the glue layer.

Abstract: A substrate heat treatment apparatus includes: a placement unit on which a substrate is placed; a heat treatment unit for heating or cooling the substrate on the placement unit; a plurality of temperature sensors positioned correspondingly to a plurality of locations of the substrate on the placement unit; and a control unit. The control unit is configured to control the heat treatment unit based on temperatures detected by the temperature sensors, to calculate a position of a thermal center of gravity of the substrate based on the temperatures detected by the temperature sensors, and to detect heat treatment condition of the substrate based on the position of the thermal center of gravity.

Abstract: Disclosed is a processing apparatus. The processing apparatus includes: a load port in which a conveyance container accommodating a plurality of semiconductor wafers is placed; a dummy wafer storage area in which a conveyance container accommodating a plurality of dummy wafers is placed; a normal-pressure conveyance room in which a first conveyance arm is installed; an equipment that processes the plurality of semiconductor wafers in a state where the semiconductor wafers and the dummy wafers which are conveyed are placed in slots, respectively; and a controller that controls each component of the processing apparatus. The controller classifies the dummy wafers accommodated in the conveyance container into a plurality of groups, and controls the first conveyance arm to preferentially convey the dummy wafers within one of the classified groups to the equipment and, in replacing the dummy wafers, to perform replacement of the dummy wafers group to group as classified.

Abstract: A method and apparatus for heating a substrate in a chamber are provided. an apparatus for positioning a substrate in a processing chamber. In one embodiment, the apparatus comprises a substrate support assembly having a support surface adapted to receive the substrate and a plurality of centering members for supporting the substrate at a distance parallel to the support surface and for centering the substrate relative to a reference axis substantially perpendicular to the support surface. The plurality of the centering members are movably disposed along a periphery of the support surface, and each of the plurality of centering members comprises a first end portion for either contacting or supporting a peripheral edge of the substrate.

Abstract: A wafer processing laminate including a support, a temporary adhesive material layer formed on the support, and a wafer laminated on the temporary adhesive material layer, the wafer having a circuit-forming front surface and back surface to be processed, wherein the temporary adhesive material layer includes a complex temporary adhesive material layer having two-layered structure including a first temporary adhesive layer composed of a thermoplastic organopolysiloxane polymer layer (A) having a film thickness of less than 100 nm and a second temporary adhesive layer composed of a thermosetting siloxane-modified polymer layer (B), the first temporary adhesive layer being releasably laminated to the front surface of the wafer, the second temporary adhesive layer being releasably laminated to the first temporary adhesive layer and the support. A temporary adhesive material for a wafer processing which withstand a thermal process at high temperature exceeding 300° C.

Abstract: A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Abstract: A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of alternating sacrificial layers and insulating layers located over a major surface of a substrate. A contact mask having contact mask openings is provided over the stack, and a first over mask having first over mask openings is provided over the contact mask. A subset of the contact mask openings is substantially aligned with the first over mask openings. Contact openings are formed through the stack, wherein each of the contact openings extends substantially perpendicular to the major surface of the substrate to a respective one of the sacrificial layers. A plurality of electrically conductive via contacts is formed in the plurality of the contact openings.

Abstract: A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.

Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.

Abstract: A method for fabricating a semiconductor device includes forming a silicon-containing layer; forming a metal-containing layer over the silicon-containing layer; forming an undercut prevention layer between the silicon containing layer and the metal containing layer; etching the metal-containing layer; and forming a conductive structure by etching the undercut prevention layer and the silicon-containing layer.

Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.

Abstract: A semiconductor device is manufactured at least partially in a semiconductor substrate. The substrate has first and second opposing main surfaces. The method includes forming a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, and forming the cell field portion by at least forming a transistor. The method further includes insulating a part of the semiconductor substrate from other substrate portions to form a connection substrate portion, forming an electrode adjacent to the second main surface so as to be in contact with the connection substrate portion, forming an insulating layer over the first main surface, forming a metal layer over the insulating layer, forming a trench in the first main surface, and filling the trench with a conductive material, and electrically coupling the connection substrate portion to the metal layer via the trench.

Abstract: A method for forming through silicon vias (TSVs) in a silicon substrate is disclosed. The method involves forming a silicon post as an annulus in a first side of a silicon substrate, removing material from an opposite side to the level of the annulus, removing the silicon post and replacing it with a metal material to form a metal via extending through the thickness of the substrate.

Abstract: A method for forming through silicon vias (TSVs) in a silicon substrate is disclosed. The method involves forming a silicon post as an substantially continuous annulus in a first side of a silicon substrate, removing material from an opposite side to the level of the substantially continuous annulus, removing the silicon post and replacing it with a metal material to form a metal via extending through the thickness of the substrate. The substantially continuous annulus may be interrupted by at least one tether which connects the silicon post to the silicon substrate. The tether may be formed of a thing isthmus of silicon, or some suitable insulating material.

Abstract: A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of each substrate. Each tapered hole is filled up with a tapered through silicon via. A recessed portion is formed on the wider end of each tapered through silicon via. A part of the substrate is removed until the narrower end of each tapered through silicon via protrudes from the other surface of the substrate. The substrates is stacked one after another by fitting and jointing the narrower end of each tapered through silicon via on one substrate into a corresponding recessed portion of the tapered through silicon via of another substrate.

Abstract: A method of assembling semiconductor devices with semiconductor dies of alternative different configurations uses the same substrate panel. The dies of the selected configuration are placed in an array, mounted, and connected to internal electrical contact pads on a first face of the panel using main fiducial markings and an array of subsidiary fiducial markings corresponding universally to arrays of semiconductor dies of the different alternative configurations. The pitch of the subsidiary fiducial markings is equal to the spacing between adjacent rows of the internal electrical contact pads on the panel and is a sub-multiple of the pitch of the array of dies.

Abstract: The invention relates to a method for producing chips (13) by dividing a wafer along dividing lines (11, 12) defining dimensions of the chip, wherein a focus (18) of a preferably pulsed laser radiation (16) is moved along the dividing lines on a first and at least a second path (25, 26) within the wafer body, wherein the laser radiation is applied to the wafer from a rear side (17) of the wafer, and the power density for producing the defects (28) on the first path (25) is lower than the power density for producing the defects (29) on the second path (26), and/or the number of defects on the first path is smaller than the number of defects on the second path.