Patents Issued in July 28, 2016
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Publication number: 20160217827Abstract: Disclosed is a video stream processing method and apparatus that may identify a target picture to be edited among a I-picture and at least one B-picture subsequent to the I-picture, the I-picture and the at least one B-picture constituting a group of pictures (GOP) included in a video stream, and process the target picture, wherein pictures included in the video stream may be decoded in a playback order.Type: ApplicationFiled: January 25, 2016Publication date: July 28, 2016Inventors: Suk Hee CHO, Sung Chang LIM, Jong Ho KIM, Hui Yong KIM, Dae Yeol LEE, Joo Young LEE, Se Yoon JEONG
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Publication number: 20160217828Abstract: A method and a system for automatically generating a video clip from one or more still images are provided herein. The method includes: obtaining one or more images containing at least one object over a background; detecting at least one object in the one or more images; deriving one or more relationships between at least two of: the background, the at least one object, or a portion thereof; determining, based on the derived one or more relationships, a spatio-temporal arrangement of at least two of: at least one portion of said one or more images, the at least one detected object, or a portion thereof; and producing a clip based on the determined spatio-temporal arrangement. The system may implement the method over a smartphone platform.Type: ApplicationFiled: February 2, 2016Publication date: July 28, 2016Inventors: Alexander RAV-ACHA, Oren Boiman
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Publication number: 20160217829Abstract: A system for synchronizing audio and video of selectably presentable multimedia content includes a memory for storing a plurality of selectably presentable multimedia content segments. Each content segment defines a portion of one or more content paths and includes a decision period during which a user may select a subsequent content segment as the content segment is playing. An assembly engine seamlessly assembles a subset of the content segments into one of the content paths, ultimately forming a multimedia presentation. A configuration manager determines an audio file and a video file to be played based on a content segment that is selected to be played immediately following the currently playing content segment. An audio engine processes the audio file for playback, and a video engine synchronizes playback of the video file with the playback of the audio file.Type: ApplicationFiled: December 30, 2015Publication date: July 28, 2016Inventors: Yoni Bloch, Tal Zubalsky, Barak Feldman
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Publication number: 20160217830Abstract: Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.Type: ApplicationFiled: January 15, 2016Publication date: July 28, 2016Inventors: Masashi TSUBUKU, Masashi FUJITA
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Publication number: 20160217831Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.Type: ApplicationFiled: April 5, 2016Publication date: July 28, 2016Inventors: Graziano Mirichigni, Corrado Villa
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Publication number: 20160217832Abstract: A system and method of operating a twin-transistor single bit multi-time programmable memory cell to provide a high gain, sensing scheme for small signals. The memory cell includes a pair of a first transistor and a second transistor providing a differential signal output. The first transistor of the memory cell couples a first circuit leg having a first current source load transistor and the second transistor couples a second circuit leg having a second current source load transistor. A programmed value is represented by a voltage threshold shift in one of the first or second transistors. A feedback circuit receives one of: a first signal or a second signal of the differential signals, and generates, in response, a feedback signal which is simultaneously applied to bias each current source load transistor in each the first and second circuit legs to amplify a voltage differential between the differential signal outputs.Type: ApplicationFiled: January 23, 2015Publication date: July 28, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Balaji Jayaraman, Thejas Kempanna, Toshiaki Kirihata, Ramesh Raghavan, Krishnan S. Rengarajan, Rajesh R. Tummuru
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Publication number: 20160217833Abstract: A sense amplifier may include an amplifying section configured to amplify data of a segment line pair when an enable signal is activated and output amplified data to a local line pair, and including latches electrically coupled in a cross-coupled type. The sense amplifier may include a switching section configured to selectively electrically couple the segment line pair and the local line pair in response to an input/output switch signal.Type: ApplicationFiled: June 5, 2015Publication date: July 28, 2016Inventors: Kyu Nam LIM, Woong Ju JANG
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Publication number: 20160217834Abstract: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes. Because of the rules governing abstracts, this abstract should not be used to construe the claims.Type: ApplicationFiled: April 5, 2016Publication date: July 28, 2016Applicant: Micron Technology, Inc.Inventor: Tae Kim
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Publication number: 20160217835Abstract: A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay buffer coupled to the second memory to compensate for a difference in the first access time and the second access time; and a circuit for merging outputs of the first memory and delayed outputs of the second memory to generate ordered output data. A method of controlling the operation of a memory system is also disclosed.Type: ApplicationFiled: January 28, 2015Publication date: July 28, 2016Applicant: XILINX, INC.Inventors: Michaela Blott, Ling Liu, Kornelis A. Vissers
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Publication number: 20160217836Abstract: A semiconductor device includes a buffer block configured to generate a strobe signal by buffering an external strobe signal inputted through a first pad, output the strobe signal to a first node of a first input/output line, generate data by buffering external data inputted through a second pad, and output the data to a second node of a second input/output line; a first channel configured to store the data loaded on the second input/output line in synchronization with the strobe signal loaded on the first input/output line; and a second channel configured to store the data loaded on the second input/output line in synchronization with the strobe signal loaded on the first input/output line.Type: ApplicationFiled: May 21, 2015Publication date: July 28, 2016Inventor: Byung Deuk JEON
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Publication number: 20160217837Abstract: A semiconductor device may include a first channel configured to output a first rising clock, a first falling clock, first rising data, and first falling data. The semiconductor device may include a second channel configured to output a second rising clock, a second falling clock, second rising data, and second falling data. The semiconductor device may include an I/O control unit configured to receive the first rising clock, the first falling clock, the first rising data, and the first falling data, generate output data, and externally output the output data through a pad unit or receive the second rising clock, the second falling clock, the second rising data, and the second falling data, generate the output data, and externally output the output data through the pad unit.Type: ApplicationFiled: May 22, 2015Publication date: July 28, 2016Inventor: Byung Deuk JEON
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Publication number: 20160217838Abstract: A semiconductor device may include an active controller configured to count pulses of an active signal, and activate an active masking signal for masking an active operation when the counted number of the active signal is greater than predetermined activation times of the active signal during a predetermined bank active section.Type: ApplicationFiled: April 28, 2015Publication date: July 28, 2016Inventor: Young Geun CHOI
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Publication number: 20160217839Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory module includes multiple device sites coupled to the a data query (DQ) buffer component via data lines and coupled to a command and address (CA) buffer component via chip select (CS) lines. A first number of the CS lines between the CA buffer component and any combination of two or more of the multiple device sites is greater than a second number of the CS lines between the CA buffer component and a single one of the multiple device sites.Type: ApplicationFiled: September 24, 2014Publication date: July 28, 2016Inventors: Frederick A. WARE, Suresh RAJAN
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Publication number: 20160217840Abstract: Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.Type: ApplicationFiled: April 4, 2016Publication date: July 28, 2016Inventors: Steven Craig Bartling, Sudhanshu Khanna
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Publication number: 20160217841Abstract: A reconfigurable semiconductor memory apparatus may include a memory cell array including a plurality of sub arrays. The reconfigurable semiconductor memory apparatus may include an information storage unit configured to store status information for each sub array, and a reset address according to the status information.Type: ApplicationFiled: April 13, 2015Publication date: July 28, 2016Inventors: Bo Ra CHOI, Ji Hyae BAE, Jun Gi CHOI
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Publication number: 20160217842Abstract: A structure includes a tetragonal Heusler of the form Mn1+cX, in which X includes an element selected from the group consisting of Ge and Ga, with 0?c?3. The tetragonal Heusler is grown directly on (or more generally, over) a substrate oriented in the direction (001) and of the form YMn1+d, wherein Y includes an element selected from the group consisting of Ir and Pt, with 0?d?4. The tetragonal Heusler and the substrate are in proximity with each other, thereby allowing spin-polarized current to pass from one through the other. This structure may form part of a magnetic tunnel junction magnetoresistive device, and an array of such magnetoresistive devices may together form an MRAM.Type: ApplicationFiled: January 26, 2015Publication date: July 28, 2016Inventors: JAEWOO JEONG, Stuart S.P. Parkin, Mahesh G. Samant
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Publication number: 20160217843Abstract: The present disclosure describes DRAM architectures and refresh controllers that allow for scheduling of an opportunistic refresh of a DRAM device concurrently with normal row activate command directed toward the DRAM device. Each activate command affords an “opportunity” to refresh another independent row (i.e., a wordline) within a memory device with no scheduling conflict.Type: ApplicationFiled: February 18, 2016Publication date: July 28, 2016Inventors: Richard Perego, Thomas Vogelsang, John Brooks
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Publication number: 20160217844Abstract: A semiconductor device includes an output controller and a data strobe signal generator. The output controller generates a period signal and a control clock signal according to a read operation signal generated to execute a read operation, an internal clock signal generated in synchronization with a clock signal, and an expansion control signal. The data strobe signal generator generates a data strobe signal according to the control clock signal during a period that the period signal is enabled. The period that the period signal is enabled expands according to the expansion control signal.Type: ApplicationFiled: May 20, 2015Publication date: July 28, 2016Inventor: Young Jun YOON
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Publication number: 20160217845Abstract: An information processing apparatus includes a memory that is volatile, a memory controller connected to the memory in an information exchangeable manner, and a clock enable (CKE) controller. The CKE controller controls a CKE signal in response to a request for a proxy in self-refresh control, the CKE signal being transmitted from the memory controller to the memory and being controlled to be kept low until cancellation of the proxy is requested. At a time of shifting to a power-saving mode, the memory controller stores information held by a central processing unit (CPU) in the memory and causes the memory to shift to a self-refresh mode. At a time of recovery from the power-saving mode, the memory controller requests the CKE controller for the cancellation of the proxy in the self-refresh control and thereafter cancels the self-refresh mode of the memory.Type: ApplicationFiled: July 28, 2015Publication date: July 28, 2016Applicant: FUJI XEROX CO., LTD.Inventors: Tsutomu NAKAMINATO, Yoshinobu TERUI, Tomokazu KANEKO, Katsuma NAKAMOTO, Yoshitaka TERUI, Asahito SHIOYASU
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Publication number: 20160217846Abstract: A semiconductor device may include a refresh controller and a bank active signal generator. The refresh controller may be suitable for generating a level signal, setting a level of the level signal in response to a refresh pulse signal while operating in a test mode, and suitable for receiving a refresh flag signal and generating a first period signal and a second period signal in response to the level signal. The bank active signal generator may be suitable for generating bank active signals for a first bank group in response to the first period signal, and generating bank active signals for a second bank group in response to the second period signal.Type: ApplicationFiled: May 6, 2015Publication date: July 28, 2016Inventors: Chul Moon JUNG, Man Keun KANG, Mi Hyun HWANG
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Publication number: 20160217847Abstract: A memory system including a plurality of dynamic random access memory (DRAM) devices and a DRAM controller is provided. The plurality of DRAM devices includes one or more DRAM groups. Each of the one or more DRAM groups includes at least two DRAM devices. The DRAM controller outputs a clock enable signal, and controls a selection signal used to select a target DRAM device that operates in a normal mode in response to the clock enable signal. At least one target DRAM device is selected from the one or more DRAM groups. One or more stand-by DRAM devices other than the at least one target DRAM device operates in a self-refresh mode.Type: ApplicationFiled: December 11, 2015Publication date: July 28, 2016Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taewoong HA, Byungchul KO, Daekyoung KIM, Jonghwan KIM
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Publication number: 20160217848Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.Type: ApplicationFiled: January 12, 2016Publication date: July 28, 2016Inventors: Takahiko ISHIZU, Wataru UESUGI, Kiyoshi KATO, Tatsuya ONUKI
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Publication number: 20160217849Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.Type: ApplicationFiled: January 20, 2016Publication date: July 28, 2016Inventors: Nhan Do, Xian Liu, Vipin Tiwari, Hieu Van Tran
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Publication number: 20160217850Abstract: A metal-insulator phase transition (MIT) flip-flop employs a selected one of a pair of bi-stable operating states to represent a logic state of the MIT flip-flop. The MIT flip-flop includes an MIT device having a current-controlled negative differential resistance (CC-NDR) to provide the pair of bi-stable operating states. A bi-stable operating state of the pair is capable of being selected by a programing voltage. Once the bi-stable operating state is selected, the bi-stable operating state is capable of being maintained by a bias voltage applied to the MIT device.Type: ApplicationFiled: March 30, 2016Publication date: July 28, 2016Inventors: Gilberto Medeiros Ribeiro, Matthew D. Pickett
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Publication number: 20160217851Abstract: A resistive random access memory device includes: a first control line, a second control line, a RRAM cell, a first programmable current source and a first programmable voltage source. The RRAM cell is coupled between the first control line and the second control line, and has a programmable resistive element. The first programmable current source is coupled to the first control line, and for selectively providing a configuration current to the RRAM cell. The first programmable voltage source is coupled to the first control line, and for selectively providing a configuration voltage to the RRAM cell. Additionally, a state of the programmable resistive element of the RRAM cell is configured according to the configuration current and the configuration voltage. Under architecture of the RRAM cell of the present invention, a reading circuit for the RRAM device can be implemented with a simple inverter instead of a complicated current sensing amplifier.Type: ApplicationFiled: January 27, 2015Publication date: July 28, 2016Inventors: Chih-Hao Lai, Chih-Kai Huang, Jou-Hung Wang
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Publication number: 20160217852Abstract: A memory operating method comprises the following steps: a first read voltage is applied to the memory cell to read a first group of data levels of the memory cell; and if the data of the memory cell can not be read with the first read voltage, a second read voltage is applied to the memory cell to read a second group of data levels of the memory cell.Type: ApplicationFiled: May 14, 2015Publication date: July 28, 2016Inventor: Chao-I Wu
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Publication number: 20160217853Abstract: A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read.Type: ApplicationFiled: September 7, 2015Publication date: July 28, 2016Inventors: Sandeep K. Guliani, Kiran Pangal, Balaji Srinivasan, Chaohong Hu
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Publication number: 20160217854Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.Type: ApplicationFiled: March 31, 2016Publication date: July 28, 2016Applicant: SanDisk Technologies Inc.Inventors: Chang Siau, Jeffrey Koon Yee Lee, Tianhong Yan, Yingchang Chen, Gopinath Balakrishnan, Tz-yi Liu
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Publication number: 20160217855Abstract: Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include using measurement and storage elements to measure the electrical response of one or more selected cells within an array and then comparing that stored electrical response to the electrical response of a reference element within the array to determine the resistive state of the one or more selected cells. These methods also include programming methods wherein selectable current limiting elements are used to permit or inhibit programming currents from flowing through selected and unselected cells, respectively. These methods further include programing methods that use specific biasing of array lines to provide sufficient programing currents through only selected cells.Type: ApplicationFiled: March 24, 2016Publication date: July 28, 2016Inventors: Claude L. BERTIN, Lee CLEVELAND
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Publication number: 20160217856Abstract: A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.Type: ApplicationFiled: March 30, 2016Publication date: July 28, 2016Inventors: Frederick Perner, Wei Yi, Matthew D. Pickett
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Publication number: 20160217857Abstract: A method is provided for programming a memory cell connected to a selected word line in a memory device. The method includes performing one programming pass of a multi-pass programming operation for the memory cell, wherein a first set of program pulses is applied to the selected word line during the one programming pass, determining a number of the program pulses applied to the selected word line during the one programming pass, determining a difference between the determined number of program pulses applied to the selected word line during the one programming pass and a predetermined number of program pulses, adjusting a parameter of a second set of program pulses for the another programming pass based on the determined difference, and performing the another programming pass for the set of memory cells, wherein the second set of program pulses is applied to the selected word line during the another programming pass.Type: ApplicationFiled: January 22, 2015Publication date: July 28, 2016Applicant: SanDisk Technologies Inc.Inventors: Rajan Paudel, Jagdish Sabde, Sagar Magia
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Publication number: 20160217858Abstract: A system and method of programming user data into a memory cell includes receiving a first user data to be programmed in a memory controller, selecting a memory cell for programming the first user data and measuring at least one health characteristic of the selected memory cell. At least one programming parameter of the selected memory cell is adjusted and the first user data is programmed to the selected memory cell using the adjusted programming parameter corresponding to the selected memory cell.Type: ApplicationFiled: January 28, 2015Publication date: July 28, 2016Inventors: Ariel Navon, Eran Sharon, Alexander Bazarsky, Noam Presman
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Publication number: 20160217859Abstract: A semiconductor device includes a memory block including memory cells coupled to word lines, and an operation circuit configured to perform a program loop on memory cells coupled a selected word line, wherein the operation circuit is configured to change a program permission voltage applied to a bit line of a program target memory cell when a number of times the program loop is performed exceeds a reference number.Type: ApplicationFiled: April 1, 2016Publication date: July 28, 2016Inventor: Hye Lyoung LEE
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Publication number: 20160217860Abstract: A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.Type: ApplicationFiled: July 8, 2015Publication date: July 28, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Chun-hung Lai, Cheng-Kuan Yin, Shih-Chung Lee, Deepanshu Dutta, Ken Oowada
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Publication number: 20160217861Abstract: A memory including an array of non-volatile latch (NVL) cells and method of operating the same are provided. In one embodiment, each NVL cell includes a non-volatile portion and a volatile portion. The non-volatile portion includes a first non-volatile memory (NVM) device and a first pass gate transistor coupled in series between a first output node and a bitline true, and a second NVM device and a second pass gate transistor coupled in series between a second output node and a bitline complement. The volatile portion includes cross-coupled first and second field effect transistors (FET), the first FET coupled between a supply voltage (VPWR) and the first output node, and the second FET coupled between VPWR and the second output node. A gate of the first FET is coupled to the second output node, and a gate of the second FET is coupled to the first output node.Type: ApplicationFiled: September 18, 2015Publication date: July 28, 2016Inventors: Jayant Ashokkumar, Vijay Raghavan, Venkatraman Prabhakar, Swatilekha Saha
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Publication number: 20160217862Abstract: A non-volatile memory device receives a start command through a command line, receives an address through an address line, receives at least one setting value through the address line, receives a confirm command corresponding to the start command through the command line, sets at least one parameter of the non-volatile memory device as the setting value based on the start command, a number of the setting value, and the confirm command, and executes an operation that corresponds to the start command, on a memory cell that corresponds to the address, based on the set parameter.Type: ApplicationFiled: April 4, 2016Publication date: July 28, 2016Inventors: MYUNG-HOON CHOI, JAE-WOO IM, KI-TAE PARK
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Publication number: 20160217863Abstract: A semiconductor device includes a plurality of memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of pages; and an operation circuit configured to output operating voltages to local lines of a selected memory block, among the plurality of memory blocks, to perform a program operation, a read operation and an erase operation on the selected memory block, wherein the operation circuit is configured to apply a dummy pulse having a positive potential to the local lines of the selected memory block after completing the program operation, the read operation and the erase operationType: ApplicationFiled: April 4, 2016Publication date: July 28, 2016Inventor: Chi Wook AN
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Publication number: 20160217864Abstract: A non-volatile memory device that a semiconductor substrate of a first conductivity type. An array of non-volatile memory cells is in the semiconductor substrate arranged in a plurality of rows and columns. Each memory cell comprises a first region on a surface of the semiconductor substrate of a second conductivity type, and a second region on the surface of the semiconductor substrate of the second conductivity type. A channel region is between the first region and the second region. A word line overlies a first portion of the channel region and is insulated therefrom, and adjacent to the first region and having little or no overlap with the first region. A floating gate overlies a second portion of the channel region, is adjacent to the first portion, and is insulated therefrom and is adjacent to the second region. A coupling gate overlies the floating gate. A bit line is connected to the first region. A negative charge pump circuit generates a first negative voltage.Type: ApplicationFiled: March 30, 2016Publication date: July 28, 2016Inventors: Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
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Publication number: 20160217865Abstract: Read disturb is reduced for dummy memory cells in a charge-trapping memory device such as a 3D memory device. The memory device includes a selected NAND string and an unselected NAND string. In the unselected NAND string, a dummy memory cell is adjacent to a select gate transistor. During a read operation involving the selected NAND string, a voltage of the dummy memory cell is increased in two steps to minimize a gradient in a channel of the unselected NAND string between the dummy memory cell and the select gate transistor. During the first step, the select gate transistor is conductive so that the channel is connected to a driven bit line. During the second step, the select gate transistor is non-conductive. Voltages on unselected word lines can also be increased in two steps to set a desired channel boosting level in the unselected NAND string.Type: ApplicationFiled: October 27, 2015Publication date: July 28, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Hong-Yan Chen, Yingda Dong, Wei Zhao
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Publication number: 20160217866Abstract: A semiconductor device, wherein the semiconductor device includes a high-voltage supply circuit suitable for supplying a high voltage; a discharge circuit suitable for discharging the high voltage; and an auxiliary-voltage supply circuit suitable for supplying a first auxiliary voltage, which varies according to an operation state of the high-voltage supply circuit, to a reference node of the discharge circuit.Type: ApplicationFiled: April 1, 2016Publication date: July 28, 2016Inventor: Yeonghun LEE
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Publication number: 20160217867Abstract: The present disclosure includes apparatuses and methods for inferring threshold voltage distributions associated with memory cells via interpolation. A number of embodiments include determining soft data for a group of memory cells each programmed to one of a number of data states, wherein the soft data comprises a number of different soft data values, determining a quantity of memory cells associated with each of the different soft data values, and inferring at least a portion of a threshold voltage distribution associated with the group of memory cells via an interpolation process using the determined quantities of memory cells associated with each of the different soft data values.Type: ApplicationFiled: April 5, 2016Publication date: July 28, 2016Inventors: Zhenlei Shen, William H. Radke
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Publication number: 20160217868Abstract: A memory device includes memory cells arranged in NAND strings between select gate transistors. A threshold voltage (Vth) distribution of the select gate transistors is evaluated, such as in response to a program, erase or read command involving a block or sub-block of memory cells. For example, a lower tail and an upper tail of the Vth distribution can be evaluated using read voltages. If the Vth is out-of-range, such as due to read disturb, data retention loss or defects in the memory device, the block or sub-block is marked as being bad and previously-programmed data in the block or sub-block can be copied to another location. If the Vth is in range, the command can be executed. Also, a control gate voltage for the select gate transistors can be set based on a Vth metric which is obtained from the evaluation.Type: ApplicationFiled: July 24, 2015Publication date: July 28, 2016Applicant: SanDisk Technologies Inc.Inventors: Deepanshu Dutta, Shota Murai, Hideto Tomiie, Masaaki Higashitani
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Publication number: 20160217869Abstract: A double lockout programming technique is provided having a hidden delay between programming and verification. A temporary lockout stage and a permanent lockout stage are provided for double lockout programming. The temporary lockout stage precedes the permanent lockout stage and is used to initially determine when a memory cell should be locked out a first time for one or more program pulses. When a memory cell initially passes verification for its target state, it is temporarily locked out from programming for one or more program pulses. The memory cell enters a permanent lockout stage where it is verified again for its target state. When the memory cell passes verification a second time, it is permanently locked out for programming during the current program phase. The memory cell may be programmed at one or more reduced program rates in the permanent lockout stage.Type: ApplicationFiled: October 30, 2015Publication date: July 28, 2016Applicant: SANDISK TECHNOLOGIES INC.Inventors: Huai-Yuan Tseng, Deepanshu Dutta
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Publication number: 20160217870Abstract: Provided are a shift register unit, a gate drive circuit, and a display panel. The shift register unit includes a first to sixth transistor and a first and second capacitor.Type: ApplicationFiled: January 22, 2016Publication date: July 28, 2016Inventors: Ying-Hsiang Tseng, Lina Xiao
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Publication number: 20160217871Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V(n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.Type: ApplicationFiled: April 5, 2016Publication date: July 28, 2016Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroyuki HIGASHIJIMA, Yoshihiro KOTANI, Shuuichirou MATSUMOTO
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Publication number: 20160217872Abstract: Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators.Type: ApplicationFiled: January 26, 2015Publication date: July 28, 2016Inventors: Masum Hossain, Maruf H. Mohammad
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Publication number: 20160217873Abstract: A post package repair (PPR) device is disclosed, which relates to a technology for masking a rupture operation in case of a post package repair (PPR) operation. The post package repair (PPR) device includes: a plurality of bank groups, each including a fuse indicating repair information, configured to share a predetermined number of fuses; a resource detection unit configured to generate a resource signal which determines whether the fuses from among the plurality of bank groups are available; and a masking controller configured to output a masking signal which prevents repeated execution of a rupture operation when there is no unused fuse in response to the resource signal and a bank active signal.Type: ApplicationFiled: April 28, 2015Publication date: July 28, 2016Inventor: Young Kyu NOH
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Publication number: 20160217874Abstract: A molten salt reactor includes: a fluoride fuel salt; and a metal hydride moderator.Type: ApplicationFiled: September 26, 2014Publication date: July 28, 2016Inventors: Leslie C. Dewan, Mark Massie
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Publication number: 20160217875Abstract: A system for draining a containment vessel may include a drain inlet located in a lower portion of the containment vessel. The containment vessel may be at least partially filled with a liquid, and the drain inlet may be located below a surface of the liquid. The system may further comprise an inlet located in an upper portion of the containment vessel. The inlet may be configured to insert pressurized gas into the containment vessel to form a pressurized region above the surface of the liquid, and the pressurized region may operate to apply a surface pressure that forces the liquid into the drain inlet. Additionally, a fluid separation device may be operatively connected to the drain inlet. The fluid separation device may be configured to separate the liquid from the pressurized gas that enters the drain inlet after the surface of the liquid falls below the drain inlet.Type: ApplicationFiled: January 28, 2015Publication date: July 28, 2016Applicant: NuScale Power, LLCInventor: Scott G. HARRIS
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Publication number: 20160217876Abstract: Systems and methods for fabricating metallic nuclear fuels are described. Methods may include preparing a metal feedstock charge; injection casting the metal feedstock charge into one or more molds to form one or more injection cast fuel slugs; determining one or more properties of the one or more injection cast fuel slugs; inserting one or more injection cast fuel slugs with acceptable properties into one or more jackets to form a plurality of fuel pins; and assembling a plurality of fuel pins into a multi-pin fuel assembly. The method may produce at least one multi-pin fuel assembly per day, wherein each of the at least one multi-pin fuel assemblies includes at least one hundred fuel pins.Type: ApplicationFiled: January 21, 2016Publication date: July 28, 2016Inventor: Leon C. Walters