Abstract: The present techniques provide methods and systems for recording micro-holograms on a holographic disk using a plurality of counter-propagating light beams in parallel. The parallel counter-propagating light beams overlap to form interference patterns on a data layer and over multiple data tracks in the holographic disk. Rotating the disk enables the parallel recording of micro-holograms over multiple data tracks, thus reducing recording time. Further, the illumination pattern may include illuminated spots and non-illuminated regions, such that each illumination spot may cover a relatively small fraction of the data layer plane, possibly controlling the depth spread of the recorded micro-hologram. In some embodiments, data in the parallel signal beams may be retrieved from a master holographic disk or may be modulated into the parallel signal beams.

Abstract: An audio video display device (AVDD) can present recorded content that can be paused. During pausing, ancillary AV content is shown until such time as a play or other signal is received.

Abstract: Embodiments are provided for managing playback of media content by a media playback system based on identified preference data associated with one of a plurality of user accounts interfacing with the media playback system. In one embodiment, a computing device may maintain a plurality of user accounts associated with a media playback system, and receive user data identifying which of the plurality of user accounts are currently interfacing with the media playback system. Then, the computing device may receive media data identifying a media item to be played by the media playback system, identifying for at least one of the plurality of user accounts that are currently interfacing with the media playback system, preference data associated with the media item. Based on the identified preference data, the computing device may determine that the media item is not to be played by a media playback system.

Abstract: A data storage device and associated methods may provide at least a data storage medium that is separated from a heat assisted magnetic recording data writer and is connected to a controller. The controller can be configured to change a laser power of the heat assisted magnetic recording data writer in response to a tested bit error rate of a median data track of a plurality of adjacent data tracks reaching an identified threshold.

Abstract: Implementations disclosed herein provide for sequential readback of program data in from a cached data region of a storage device. In particular, the disclosed technology provides for storing a sequence of logical addresses associated with execution of a program, the sequence of logical addresses including at least two consecutive logical addresses associated with non-consecutive data blocks in a user data region; writing data corresponding to the at least two consecutive logical addresses to sequential data blocks in a cached data region; determining that a sequence of read commands from a host computer is associated with the data; and reading the data from the cached data region.

Abstract: A testing system that is capable of testing individual data storage components may have testing, loader, and exchange assemblies with the testing assembly having a plurality of test slots each having long and short axes. The loader assembly can be configured to transport and install a test deck or data storage device from the exchange assembly to a test slot of the plurality of test slots with a long axis of the test deck continuously aligned with the long axis of the test slot while being transported.

Abstract: Graphical User Interfaces (GUIs) for a digital media player application are disclosed. In one aspect, a GUI is generated that presents a “histogram view” of digital media items of a digital media source. The histogram view associates visual representations of the digital media items with a media attribute, such as associating songs with a recording artist who recorded the songs. In another aspect, a GUI is generated that presents a “stack view” including stacks of visual representations of digital media items that are associated with a media attribute, such as a playlist or artist. The stacks of visual representations can be scrubbed by a user (e.g., using a touch gesture) to select digital media items in the stack for playback.

Abstract: A computer-implemented method, including detecting an event associated with an image displayed on a display device within a software application, loading a media player into the software application behind the image, where the media player is configured to play a media file associated with the image, and causing a representation of a frame of the media file to be displayed within the media player instead of the image.

Abstract: A method for creating a content in an electronic device is provided. The method includes acquiring first media data acquired by at least one external electronic device, acquiring second media data on a basis of at least a part of the first media data, recognizing a feature of the second media data acquired by the at least one external electronic device, and creating the content on a basis of at least a part of the feature of the second media data.

Abstract: Systems and associated methods for generating custom media products along various story arcs are described. The story arcs correspond to sub-themes for organizing media content within a larger theme, or story, into a custom media product. The media content can include stock media content, guest-specific or custom media content, which can include rendered content. Embodiments utilize authoring tools and automated workflow mechanisms to take various forms of raw media content and create customized media products for individual guests or groups of guests.

Abstract: This disclosure relates to dynamic split-frame preview of video editing effects. An editing component determines a set of editing effects for the video, generates a copy of the video, applies the set of editing effects to the copy, and provides the video and the copy to a rendering component. The rendering component generates a mask based on a set of mask criteria, renders a split-frame composite video using the video and the edited video based at least in part on the mask, and provides playback of the split-frame composite video. The split-frame composite video provides a dynamic split-frame preview of video editing effects, wherein one frame includes the video, and another frame includes the edited copy of the video.

Abstract: An apparatus comprising an interface and a processor. The interface may be configured to (i) receive a first clip of video generated by a camera through a network, (ii) receive edit information through the network, (iii) transfer parsing information to the camera and (iv) receive one or more segments of a second clip of video generated by the camera as identified by the parsing information through the network. The processor may be configured to (i) send/receive data to/from the interface, (ii) edit the first clip in response to the edit information, (iii) generate the parsing information based on the edit information and (iv) create a third clip of video by editing the segments according to the edit information. The second clip may be a higher resolution version of the first clip. The third clip may have the higher resolution.

Abstract: An information processing device includes a control unit configured to store in a recording medium a piece of attribute information specified by a user input from among a plurality of sequential pieces of the attribute information in association with a predetermined time period of a content stored in the recording medium.

Abstract: A method of recording multiple highlights concurrently includes steps of collecting N game videos concurrently, choosing one of the game videos to execute a highlight recording treatment, inserting an in point and an out point for a highlight picture, and concurrently copying time position information of the aforementioned in point and the out point of the game video in N?1 video games to form respective highlight segment records. Thus, human and material resources involved in collecting videos at multiple viewpoints for the sport live broadcast can be largely reduced.

Abstract: The area consumed by switching transistors for a 3D NAND memory array can be reduced with 3D voltage switching transistors with reduced aggregate area in comparison with 2D voltage switching transistors such as transistors in the substrate. The integrated circuit comprises a 3D NAND array of memory transistors; a plurality of bit lines, with different ones of the plurality of bit lines electrically coupled to different parts of the 3D NAND array; and a plurality of transistor pairs with a stack of semiconductor layers. Different layers in the stack of semiconductor layers include different transistor pairs of the plurality of transistor pairs. Each of the plurality of transistor pairs includes first and second transistors with first, second, and third source/drain terminals. The first transistor includes the first and the third source/drain terminals, and the second transistor includes the second and the third source/drain terminals.

Abstract: A semiconductor device may include a target voltage generation section configured to generate first and second target voltages. The semiconductor device may include a comparison signal generation section configured to compare levels of the first and second target voltages with levels of first and second internal voltages, and generate first and second comparison signals. The semiconductor device may include a latch code generation section configured to latch global codes and output first and second latch codes in response to the first and second comparison signals. The semiconductor device may include a selection code generation section configured to generate first and second selection codes for adjusting levels of the first and second internal voltages using either the global codes or the first and second latch codes.

Abstract: A semiconductor memory device may include a memory cell array, a plurality of page buffers respectively connected to a plurality of bit lines of the memory cell array, and a control logic configured to control the plurality of page buffers to perform an operation on the memory cell array, wherein each of the plurality of page buffers senses a current amount, which varies according to a potential level of a corresponding bit line among the plurality of bit lines, at a sensing node to read data, and a precharge potential level at the sensing node is adjusted according to a temperature.

Abstract: Disclosed here is an apparatus that comprises a data terminal, a data output circuit including a plurality of output buffers coupled in common to the data terminal, and an impedance control circuit coupled to the data output circuit, wherein the impedance control circuit is configured to generate first impedance code and second impedance code different from the first impedance code and to apply a selected one of the first impedance code and the second impedance code to at least one of the output buffers.

Abstract: Systems and methods for monitoring and controlling repetitive accesses to a dynamic random-access memory (DRAM) row are disclosed. A method for monitoring and controlling repetitive accesses to a DRAM can include dividing a bank of the DRAM into a number of logical blocks, mapping each row of the bank to one of the logical blocks, monitoring accesses to the logical blocks, and controlling accesses to the logical blocks based on the monitoring.

Abstract: A integrated circuit may include an input buffer suitable for buffering a strobe signal in response to a buffer enablement signal to generate an internal strobe signal, an internal clock generator suitable for receiving the internal strobe signal to generate internal clock signals including different phases. The integrated circuit may include a strobe signal driver suitable for driving the strobe signal in response to a drive control signal. The drive control signal may be enabled prior to the buffer enablement signal being enabled.

Abstract: Disclosed is a semiconductor memory device including: a sense amplifier capable of sensing and amplifying data loaded on a data-line pair based on a pull-up driving voltage and a pull-down driving voltage; a pull-up driving unit capable of supplying a first voltage as the pull-up driving voltage for first and third active sections of an active mode, and supplying a second voltage having a voltage level lower than the first voltage as the pull-up driving voltage for a second active section of the active mode, between the first and third active sections of the active mode; and a pull-down driving unit capable of supplying a third voltage as the pull-down driving voltage for the first to third active sections of the active mode and for an initial section of a precharge mode after the active mode.

Abstract: A semiconductor memory apparatus may include a memory cell array. The semiconductor memory apparatus may include an impedance calibration circuit configured to perform an impedance matching operation by generating an impedance code based on a voltage of an interface node determined by an external reference resistor or an internal reference resistor unit according to whether or not to the external reference resistor is coupled to the impedance calibration circuit. The semiconductor memory apparatus may include a data input/output (I/O) driver configured to receive input data from the memory cell array and generate output data in response to the impedance code.

Abstract: A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.

Abstract: A memory macro includes a plurality of segments corresponding to a plurality of tracking circuits. Each segment of the plurality of segments thereby corresponds to one tracking circuit of the plurality of tracking circuits. In response to a read operation of a memory cell of a segment, a tracking circuit corresponding to the segment is configured to generate an edge of a tracking signal based on which a first edge of a cell signal associated with the memory cell is generated.

Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Abstract: A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile memory of the solid-state drive to define an unsafe zone in response to the determining that the last power-down of the solid-state drive was the unsafe power-down. Step (C) may define a pad zone comprising one or more of the pages subsequent to the unsafe zone. Step (D) may resume operation of the solid-state drive by writing new data subsequent to the pad zone.

Abstract: An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array and a control circuit. The configurable storage block may receive a mode selection command. The control circuit may determine to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order based on the mode selection command. Thus, the configurable storage block may implement first-in first-cut modules or last-in first-out modules and variations thereof in addition to implementing memory modules with random access.

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

Abstract: Methods and apparatus for computer systems having first and second memory tier having regions, physical memory having page caches that are shareable with multiple ones of the regions in the first memory tier and the regions in the second memory tier, and virtual memory having mmaps of ones of the regions in the first memory tier and ones of the regions in the second memory tier, wherein the mmaps are associated with multiple ones of the pages caches.

Abstract: The disclosure relates to semiconductor memory devices and related methods. A semiconductor memory device comprises: a single-ended sense amplifier circuit for reading data sensed from selected memory cells in a memory array, the sense amplifier having a first node used to feed in a reference signal, a second node coupled to a bit line, and sense transistors responsible for amplifying the content of a selected memory cell during a sense operation, a reference circuit having replica transistors of the sense transistors and further comprising a regulation network designed so that each replica transistor operates in a stable operating point, and wherein the regulation network generates a control voltage that is applied to the sense amplifier circuit.

Abstract: Provided is a memory device with a reduced layout area. The memory device includes a sense amplifier electrically connected to first and second wirings and positioned in a first layer, and first and second circuits positioned in a second layer over the first layer. The first circuit includes a first switch being turned on and off in accordance with a potential of a third wiring, and a first capacitor electrically connected to the first wiring via the first switch. The second circuit includes a second switch being turned on and off in accordance with a potential of a fourth wiring, and a second capacitor electrically connected to the second wiring via the second switch. The first wiring intersects the third wiring and does not intersect the fourth wiring in the second layer. The second wiring intersects the fourth wiring and does not intersect the third wiring in the second layer.

Abstract: Tri-level-cell dynamic random access memory (DRAM) stores 3 levels of voltage (0, VDD/2, VDD) into a plurality of memory cells. Selected memory cell connected to bitline (BLT) to develop signal voltage, and adjacent reference bitline (BLR) develops reference voltage at VDD/2. An asymmetrical sensing amplifier (ASA), which has alternative positive offset and negative offset, is used to sense signal voltage and reference voltage for both their difference and sameness. ASA control signals, A and B, switch at different timing points or at different voltage level or the combination of both to have offset voltage set at either positive or negative polarity. Two consecutive read out from one ASA or one single read out from two ASA can be implemented to read memory cells data to local IOs. Output from ASA will be used to restore voltage back to the accessed memory cells.

Abstract: Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Abstract: The present invention is directed to a multi-state current-switching magnetic memory element configured to store a state by current flowing therethrough to switch the state including two or more magnetic tunneling junctions (MTJs) coupled in parallel between a top electrode and a bottom electrode. Each MTJ includes a free layer with a switchable magnetic orientation perpendicular to a layer plane thereof, a fixed layer with a fixed magnetic orientation perpendicular to a layer plane thereof, and a barrier layer interposed between the free layer and the fixed layer. The magnetic memory element is operable to store more than one bit of information.

Abstract: A semiconductor memory device is configured to perform a first verification operation by setting an initial voltage level of a verification voltage to a first voltage level and boosting the verification voltage during a first period. The semiconductor memory device includes a memory cell array that stores program data, a sensor generating sensing data, and a condition determination unit comparing the program data and the sensing data.

Abstract: A variable resistance memory apparatus and a method of manufacturing the same are provided. The variable resistance memory apparatus includes a plurality of memory cells. Each of the memory cells includes a plurality of data storage regions. The plurality of data storage regions have different widths from each other.

Abstract: An evaluation signal is applied to a memory cell in an array of resistance variable memory cells. The evaluation signal is configured to cause the memory cell to switch from a first state to a second state. Responses from the memory cell are sensed at three or more sample points. Differences between the responses are determined. For example, with three sample points, a first delta is determined between the first two responses and a second delta is determined between the last two responses. A difference of deltas is determined as a difference between the first and second delta, or vice versa. It is determined that the memory cell changes from the first to the second state if the difference of deltas is above a threshold. It is determined that the memory cell remains in the second state if the difference of deltas is below the threshold.

Abstract: A nonvolatile semiconductor memory device includes: a memory cell (MC0) including a cell transistor (TC0) and a variable resistance element (RR0); a memory cell (MC1) including a cell transistor (TC1) and a variable resistance element (RR1); a word line (WL0) connected to the cell transistor (TC0); a word line (WL1) connected to the cell transistor (TC1); a data line (SL0) connecting the cell transistor (TC0) and the variable resistance element (RR1) to each other; and a data line (BL0) connecting the variable resistance element (RR0) and the cell transistor (TC1) to each other.

Abstract: An object of this invention is to provide a semiconductor memory device capable of increasing the read transfer rate by performing the read operation in parallel while suppressing the voltage drop when a large current is passed to a memory chain and reducing a chip area by reducing the number of peripheral circuits to feed power. A semiconductor memory device according to this invention includes upper and lower electrodes in a flat plate shape, first and second select transistors extending in first and second directions respectively, and a wire arranged between the first select transistor and the second select transistor and the wire and the lower electrode are configured to be electrically insulated from each other by turning off the first select transistor (see FIG. 2).

Abstract: A method of operating a cross-point memory device, having an array of multilevel cells, includes performing a first reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a first state and performing a second reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a second state. A difference between a level of a first voltage used in a first sensing operation and a level of a second voltage used in a second sensing operation in the first reading operation is different from a difference between a level of a third voltage used in a first sensing operation and a level of a fourth voltage used in a second sensing operation in the second reading operation.

Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.

Abstract: Circuits and methods for detecting write operation and limiting cell current in resistive random access memory (RRAM or ReRAM) cells are provided. RRAM cells can include a select transistor and a programmable resistor. Current can flow through the programmable resistor responsive to word line voltage VWL applied to the gate of the select transistor and a bit line voltage VBL applied to the source of the select transistor. Responsive to the current, the programmable resistor can change between relatively high and low resistances (“SET”), or between relatively low and high resistances (“RESET”). It can be desirable to accurately characterize the resistance of the programmable resistor, that is, to accurately detect write operations such as SET or RESET. Additionally, it can be undesirable for the current to exceed a certain value (“over-SET”). The present circuits and methods can facilitate detecting write operations or limiting current, or both, in an RRAM cell.

Abstract: A method for programming a memory device comprises the following steps: performing an interleaving programming, including: programming a first memory cell during a first time interval and correspondingly verifying the first memory cell during a second time interval; programming a second memory cell during a third time interval and correspondingly verifying the second memory cell during a fourth time interval between the first and second time intervals; and inserting at least one dummy cycle between the first and second time intervals to ensure that a resistance change per unit of time of the first memory cell is less than a threshold.

Abstract: A semiconductor memory device includes a column address generation circuit suitable for generating contents addressable memory (CAM) column addresses for duplicated CAM data, a column selection circuit suitable for allocating columns to the duplicated CAM data according to the CAM column addresses, and a plurality of page buffer units, each unit being coupled to a corresponding memory group through the allocated columns, and suitable for storing the duplicated CAM data in the memory groups through the allocated columns. The allocated columns are of arranged sequentially within each memory group in a circular order, and a part of the CAM column addresses represent columns which are physically apart by a predetermined number of columns within a memory group.

Abstract: A memory device is provided as follows. A memory cell array includes strings including first and second strings. Each string includes a ground selection transistor and cell transistors. First and second ground selection lines are connected to a gate of a first ground selection transistor of the first string and a gate of a second ground selection transistor of the second string, respectively. First and second cell gate lines are connected to a gate of a first cell transistor of the first string and a gate of a second cell transistor of the second string, respectively. A first interconnection unit electrically connects a first portion of the first cell gate line to a first portion of the second cell gate line. A second interconnection unit electrically connects a second portion of the first cell gate line to a second portion of the second cell gate line.

Abstract: A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

Abstract: Apparatuses, systems, and methods are disclosed for a read operation for a non-volatile memory. A method includes determining whether one or more non-volatile storage cells satisfy a predefined condition. A method includes preparing the one or more non-volatile storage cells for use prior to satisfying a read request from a storage client using the one or more non-volatile storage cells in response to determining that a predefined condition is satisfied.

Abstract: A memory system includes a semiconductor memory device and a controller. The semiconductor memory device performs a writing operation with either a first writing method or a second writing method. The controller selects one of the first writing method and the second writing method upon receipt of a write instruction and output a write command indicating the selected writing method to the semiconductor memory device. The controller selects the writing method in accordance with a storage location in the semiconductor memory device targeted by the write instruction.

Abstract: In a general aspect, a method of writing data in a nonvolatile memory can include performing a first erase or program cycle to write regular data in a first memory cell of the non-volatile memory by (i) applying at least one erase or program pulse to the first memory cell and (ii) determining the state, erased or programmed, of the first memory cell, and repeating (i) and (ii) if the first memory cell is not in the desired state. The method can also include applying a predetermined number of erase or program pulses to write fake data in a second memory cell.

Abstract: A non-volatile memory device receives a start command through a command line, receives an address through an address line, receives at least one setting value through the address line, receives a confirm command corresponding to the start command through the command line, sets at least one parameter of the non-volatile memory device as the setting value based on the start command, a number of the setting value, and the confirm command, and executes an operation that corresponds to the start command, on a memory cell that corresponds to the address, based on the set parameter.