Abstract: Provided is a charged particle beam exposure apparatus configured as follows. An electron beam emitted from an electron gun is deformed by an asymmetric illumination optical system to have an elongated section. The electron beam is then applied to a beam shaping aperture plate provided with a plurality of apertures arranged in a line, thereby generating a plurality of electron beams. Exposure of a predetermined pattern is performed on a semiconductor substrate by moving a stage device in a direction orthogonal to line patterns on the semiconductor substrate and turning the plurality of electron beams on or off in synchronization with the movement of the stage device by use of a blanker plate and a final aperture plate.

Abstract: The present disclosure discusses a power delivery system, and methods of operation, configured to monitor characteristics of a generator, a match network, and a plasma load, via one or more sensors, and control these components via a local controller in order to improve power delivery accuracy and consistency to the plasma load. Control can be based on a unified monitoring of power characteristics in the power delivery system as well as variations between components and even non-electrical characteristics such as plasma density, end point, and spectral components of plasma light emission, to name a few.

Abstract: Provided is plasma block for a remote plasma source, and more particularly, is a plasma block that induces plasma to be generated and to flow between a remote plasma source and a vacuum chamber during a cleaning process performed on the vacuum chamber by the remote plasma source. The plasma block includes an external connection path and an internal connection path, which are formed as two sub-blocks connected to each other are combined, wherein the internal connection path includes a linear extending portion that extends in a straight line along a length direction of the internal connection path, and a curve extending portion that extends in a curve to form a curved surface based on a location where the internal connection path and the external connection path contact each other, wherein the curve extending portion has a spherical surface of a complex spherical surface.

Abstract: An apparatus for creating an angled ion beam for implanting into a substrate is disclosed. The apparatus includes a plasma chamber in which plasma is created. The extraction aperture includes a plurality of rotatable plates. Ion beamlets are extracted through apertures defined by the plurality of rotatable plates. The degree to which these plates are rotated determines the angle of extraction for the extracted ion beam. These plates may be formed in a plurality of different shapes, which may increase the maximum extraction angle that is achievable. Additionally, electrodes may be disposed near the plates to affect the extraction angle.

Abstract: The present invention provides novel plasma sources useful in the thin film coating arts and methods of using the same. More specifically, the present invention provides novel linear and two dimensional plasma sources that produce linear and two dimensional plasmas, respectively, that are useful for plasma-enhanced chemical vapor deposition. The present invention also provides methods of making thin film coatings and methods of increasing the coating efficiencies of such methods.

Abstract: A photomultiplier tube includes a semiconductor photocathode and a photodiode. Notably, the photodiode includes a p-doped semiconductor layer, an n-doped semiconductor layer formed on a first surface of the p-doped semiconductor layer to form a diode, and a pure boron layer formed on a second surface of the p-doped semiconductor layer. A gap between the semiconductor photocathode and the photodiode may be less than about 1 mm or less than about 500 ?m. The semiconductor photocathode may include gallium nitride, e.g. one or more p-doped gallium nitride layers. In other embodiments, the semiconductor photocathode may include silicon. This semiconductor photocathode can further include a pure boron coating on at least one surface.

Abstract: An ionic liquid ion source can include a microfabricated body including a base and a tip. The body can be formed of a porous material compatible with at least one of an ionic liquid or room-temperature molten salt. The body can have a pore size gradient that decreases from the base of the body to the tip of the body, such that the at least one of an ionic liquid or room-temperature molten salt is capable of being transported through capillarity from the base to the tip.

Abstract: Mass spectrometers and related methods of making and using the same are disclosed herein that generally involve positioning a blocking or masking element in the path of an ion beam passing through the mass spectrometer so as to selectively block at least a portion of the ions in the ion beam from entering an accelerator. Mass spectrometers and related methods are also disclosed in which an ion beam passing through the mass spectrometer is deflected or otherwise aimed so as to approach a TOF axis of an accelerator at a non-zero angle.

Abstract: Described herein are methods and systems related to the use of the pre-existing ion injection pathway of a mass spectrometer to perform beam-type collision-activated dissociation, as well as other dissociation methods. The methods can be practiced using a wide range of mass spectrometer configurations and allows MSn experiments to be performed on very basic mass spectrometers, even those without secondary mass analyzers and/or collision cells. Following injection and selection of a particular ion type or population, that population can be fragmented via beam-type collision-activated dissociation (CAD), as well as other dissociation methods, using the pre-existing ion injection pathway or inlet of a mass spectrometer. For CAD applications, this is achieved by transmitting the ions back along the ion injection pathway with a high degree of kinetic energy. As the ions pass into the higher pressure regions located in or near the atmospheric pressure inlet, the ions are fragmented and then trapped.

Abstract: A lighting device includes a casing having an inlet that introduces external air at one side and an outlet that discharges the introduced air at the other side. A fan is located within the casing to flow external air from an inlet direction to an outlet direction. An inlet cover blocks at least an upper area of the inlet to prevent external air from being directly introduced into the inlet. An air flow channel communicates the inlet and the outside, and includes two contracting flow channels having a reducing sectional area in an advancing direction of air. The two expanding flow channels communicate with the contracting flow channels and have an increasing sectional area in an advancing direction of air, so that in a connection portion of the contracting flow channel and the expanding flow channel, the advancing direction of air is changed.

Abstract: Disclosed is a liquid chemical for forming a water-repellent protecting film on a wafer. The liquid chemical is a liquid chemical containing a water-repellent-protecting-film-forming agent for forming the water-repellent protecting film, at the time of cleaning the wafer which has a finely uneven pattern at its surface and contains at least at a part of a surface of a recessed portion of the uneven pattern at least one kind of matter selected from the group consisting of titanium, titanium nitride, tungsten, aluminum, copper, tin, tantalum nitride, ruthenium and silicon, at least on the surface of the recessed portion. The liquid chemical is characterized in that the water-repellent-protecting-film-forming agent is a water-insoluble surfactant. The water-repellent protecting film formed with the liquid chemical is capable of preventing a pattern collapse of the wafer, in a cleaning step.

Abstract: Systems and methods for operating a substrate processing system include processing a substrate arranged on a substrate support in a processing chamber. At least one of precursor gas and/or reactive gas is supplied during the processing. The substrate is removed from the processing chamber. Carrier gas and purge gas are selectively supplied to the processing chamber. RF plasma is generated in the processing chamber during N cycles, where N is an integer greater than one. The RF plasma is on for a first period and off for a second period during each of the N cycles. The purge gas is supplied during at least part of each of the N cycles.

Abstract: In various embodiments, a method for coating a workpiece is provided. The method may include drying a workpiece, the workpiece being coated with at least one oxide layer as an uppermost layer; depositing a dielectric layer over the uppermost layer of the dried workpiece; wherein the workpiece is continuously subject to a pressure which is lower than atmospheric pressure during the drying process and during the depositing process.

Abstract: Disclosed is a method of forming a nitride film on a substrate to be processed (“processing target substrate”) in a processing container. The method includes an adsorption step of supplying a precursor gas including a silicon-containing gas into the processing container, and adsorbing a molecule of the precursor gas onto a surface of the processing target substrate, and a reaction step of supplying a reaction gas including a nitrogen- and hydrogen-containing gas while supplying microwaves from an antenna to generate plasma of the reaction gas just above the processing target substrate, and performing a plasma processing, by the generated plasma, on a surface of the substrate to be processed on which the molecule of the precursor gas has been adsorbed.

Abstract: Methods of depositing and tuning deposition of sub-stoichiometric titanium oxide are provided. Methods involve depositing highly pure and conformal titanium on a substrate in a chamber by (i) exposing the substrate to titanium tetraiodide, (ii) purging the chamber, (iii) exposing the substrate to a plasma, (iv) purging the chamber, (v) repeating (i) through (iv), and treating the deposited titanium on the substrate to form sub-stoichiometric titanium oxide. Titanium oxide may also be deposited prior to depositing titanium on the substrate. Treatments include substrate exposure to an oxygen source and/or annealing the substrate.

Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a container configured to contain a wafer, and a supporter configured to support the wafer in the container. The apparatus further includes a plasma generator including a plasma tube, and configured to form a film on the wafer by generating plasma in the container with the plasma tube during a first period and during a second period after the first period. The apparatus further includes a controller configured to set a distance between the plasma tube and the wafer to be a first distance during the first period, and set the distance to be a second distance longer than the first distance during the second period.

Abstract: A thin film that has a predetermined composition and containing predetermined elements is formed on a substrate by performing a cycle of steps a predetermined number of times, said cycle comprising: a step wherein a first layer containing the predetermined elements, nitrogen and carbon is formed on the substrate by alternately performing, a predetermined number of times, a process of supplying a first source gas containing a predetermined element and a halogen group to the substrate and a process of supplying a second source gas containing a predetermined element and an amino group to the substrate; a step wherein a second layer is formed by modifying the first layer by supplying an amine-based source gas to the substrate; and a step wherein a third layer is formed by modifying the second layer by supplying a reaction gas that is different from the source gases to the substrate.

Abstract: A method is for hydrophobization of a surface of a silicon-containing film by atomic layer deposition (ALD), wherein the surface is subjected to atmospheric exposure. The method includes: (i) providing a substrate with a silicon-containing film formed thereon; and (ii) forming on a surface of the silicon-containing film a hydrophobic atomic layer as a protective layer subjected to atmospheric exposure, by exposing the surface to a silicon-containing treating gas without exciting the gas. The treating gas is capable of being chemisorbed on the surface to form a hydrophobic atomic layer thereon.

Abstract: A method for forming on a substrate a doped silicon oxide film with a cap film, includes: forming an arsenosilicate glass (ASG) film as an arsenic (As)-doped silicon oxide film on a substrate; continuously treating a surface of the ASG film with a treating gas constituted by Si, N, and H without excitation; and continuously forming a silicon nitride (SiN) film as a cap film on the treated surface of the ASG film.

Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a belt supporting module including a first portion that is provided around a first axis, a second portion that is provided around a second axis different from the first axis, a third portion connecting the first and second portions, and a fourth portion connecting the first and second portions and positioned below the third portion. The apparatus further includes a belt provided on the belt supporting module, and configured to rotate around the first axis in a first direction and rotate around the second axis in a second direction reverse to the first direction. The apparatus further includes a wafer supporting module provided on the belt and configured to support a wafer. The apparatus further includes raw material feeding heads provided above the belt and configured to feed a raw material of a film to be formed on the wafer.

Abstract: Provided is a technique of forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes: forming a first layer by supplying a gas containing a first element to the substrate, wherein the first layer is a discontinuous layer, a continuous layer, or a layer in which at least one of the discontinuous layer or the continuous layer is overlapped; forming a second layer including the first layer and a discontinuous layer including a second element stacked on the first layer; and forming a third layer by supplying a gas containing a third element to the substrate to modify the second layer under a condition where a modifying reaction of the second layer by the gas containing the third element is not saturated.

Abstract: A method of manufacturing a semiconductor element includes a first step of epitaxially growing an AlN layer on a substrate, a second step of forming a buffer layer on the AlN layer by epitaxially growing AlxGayInzN where x, y, and z satisfy x+y+z=1 and y is not zero without adding Fe, a third step of forming a resistance layer on the buffer layer by epitaxially growing AlxGayInzN where x, y, and z satisfy x+y+z=1 and y is not zero while adding Fe, a step of epitaxially growing a channel layer on the resistance layer, a step of epitaxially growing an electron supply layer above the channel layer, and a step of forming an electrode above the electron supply layer.

Abstract: In some aspects, methods of forming a metal sulfide thin film are provided. According to some methods, a metal sulfide thin film is deposited on a substrate in a reaction space in a cyclical process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase sulfur reactant. In some aspects, methods of forming a three-dimensional architecture on a substrate surface are provided. In some embodiments, the method includes forming a metal sulfide thin film on the substrate surface and forming a capping layer over the metal sulfide thin film. The substrate surface may comprise a high-mobility channel.

Abstract: A method for depositing a Group III nitride semiconductor film on a substrate is provided that comprises: providing a sapphire substrate; placing the substrate in a vacuum chamber; conditioning a surface of the substrate by etching and providing a conditioned surface; holding the substrate away from a substrate facing surface of a heater by a predetermined distance; heating the substrate to a temperature by using the heater whilst the substrate is held away from the substrate facing surface of the heater, and depositing a Group III nitride semiconductor film onto the conditioned surface of the substrate by a physical vapour deposition method whilst the substrate is held away from the substrate facing surface of the heater and forming an epitaxial Group III nitride semiconductor film with N-face polarity on the conditioned surface of the substrate.

Abstract: The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiOxNyCz:Hw, where w, x, y, and z can vary in concentration from 0% to 100%, is produced as a hardmask with optical properties that are substantially matched to the photo-resists at the exposure wavelength. Thus making the hardmask optically planarized with respect to the photo-resist. This allows for multiple sequences of litho and etches in the hardmask while the photo-resist maintains essentially no optical topography or reflectivity variations.

Abstract: Graphite-based devices with a reduced characteristic dimension and methods for forming such devices are provided. One or more thin films are deposited onto a substrate and undesired portions of the deposited thin film or thin films are removed to produce processed elements with reduced characteristic dimensions. Graphene layers are generated on selected processed elements or exposed portions of the substrate after removal of the processed elements. Multiple sets of graphene layers can be generated, each with a different physical characteristic, thereby producing a graphite-based device with multiple functionalities in the same device.

Abstract: A method of vapor-diffusing impurities into a diffusion region of a target substrate to be processed using a dummy substrate is provided. The method includes loading the target substrate and the dummy substrate in a substrate loading jig, accommodating the substrate loading jig loaded with the target substrate and the dummy substrate in a processing chamber of a processing apparatus, and vapor-diffusing impurities into the diffusion region of the target substrate in the processing chamber having the accommodated substrate loading jig. The vapor-diffused impurities are boron, an outer surface of the dummy substrate includes a material having properties not allowing boron adsorption.

Abstract: The invention relates to a post-activation method of dopants in a doped and activated GaN-base semiconductor layer, including the following successive steps: providing said doped and activated substrate, eliminating a part of the semiconductor material layer.

Abstract: A method of manufacturing a semiconductor structure, and the resultant structure. The method includes forming an oxide layer above a substrate. The method includes forming a metal layer above the oxide layer. The method includes forming a first capping layer above the metal layer. A material forming the first capping layer may be titanium oxide, or titanium oxynitride. The method includes annealing the semiconductor structure. Annealing the semiconductor structure may result in diffusing a metal from the metal layer into the oxide layer.

Abstract: A number of variations may include a method that may include depositing a first layer on a first semiconductor epi layer (epitaxial layer) in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer. The layer may include a first metal and a second metal. The first semiconductor epi layer may be subjected to at least a first annealing act to provide a first structure. At least a portion of the first structure may be stripped to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act. Thereafter, the stripped first structure may be subjected to a second annealing act.

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

Abstract: Apparatus and methods for plasma etching are disclosed. In one embodiment, a method of etching a plurality of features on a wafer includes positioning a wafer on a feature plate within a chamber of a plasma etcher, providing a plasma source gas within the chamber, providing an anode above the feature plate and a cathode below the feature plate, connecting a portion of the cathode to the feature plate, generating plasma ions using a radio frequency power source and the plasma source gas, directing the plasma ions toward the wafer using an electric field, and providing an electrode shield around the cathode. The electrode shield is configured to protect the cathode from ions directed toward the cathode including the portion of the cathode connected to the feature plate.

Abstract: A sacrificial-post templating method is presented for directing block copolymer (BCP) self-assembly to form nanostructures of monolayers and bilayers of microdomains. The topographical post template can be removed after directing self-assembly and, therefore, is not incorporated into the final microdomain pattern. The sacrificial posts can be a material removable using a selective etchant that will not remove the material of the final pattern block(s). The sacrificial posts may be removable, at least in part, using a same etchant as for removing one of the blocks of the BCP, for example, a negative tone polymethylmethacrylate (PMMA) when a non-final pattern block of polystyrene is removed and polydimethylsiloxane (PDMS) remains on the substrate.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A first dielectric layer is deposited on the substrate. A patterned photoresist layer is formed on the first dielectric layer. The patterned photoresist layer is trimmed. The first dielectric layer is etched through the trimmed patterned photoresist layer to form a dielectric feature. A sacrificing energy decomposable layer (SEDL) is deposited on the dielectric feature and etched to form a SEDL spacer on sides of the dielectric feature. A second dielectric layer is deposited on the SEDL spacer and etched to form a dielectric spacer. The SEDL spacer is decomposed to form a trench.

Abstract: The present disclosure provides a method of manufacturing an integrated circuit device in some embodiments. In the method, a semiconductor substrate is processed through a series of operations to form a topographically variable surface over the semiconductor substrate. The topographically variable surface varies in height across the semiconductor substrate. A polymeric bottom anti-reflective coating (BARC) is provided over the topographically variable surface. Chemical mechanical polishing is performed to remove a first portion of the BARC, and etching effectuates a top-down recessing of the BARC.

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch using plasma effluents formed in a remote plasma. The remote plasma excites a fluorine-containing precursor in combination with an oxygen-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor or an alcohol. The combination react with the patterned heterogeneous structures to remove an exposed silicon oxide portion faster than a second exposed portion. The inclusion of the oxygen-containing precursor may suppress the second exposed portion etch rate and result in unprecedented silicon oxide etch selectivity.

Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

Abstract: A method of removing titanium nitride hardmask is described. The hardmask resides above a low-k dielectric layer prior to removal and the low-k dielectric layer retains a relatively low net dielectric constant after the removal process. The low-k dielectric layer may be part of a dual damascene structure having copper at the bottom of the vias. A non-porous carbon layer is deposited prior to the titanium nitride hardmask removal to protect the low-k dielectric layer and the copper. The titanium nitride hardmask is removed with a gas-phase etch using plasma effluents formed in a remote plasma from a chlorine-containing precursor. Plasma effluents within the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride.

Abstract: Techniques disclosed herein include methods for DSA patterning and curing of DSA patterns. Techniques include curing phase-separated block copolymers using vacuum ultraviolet (VUV) light exposure at wavelengths from about 100 nanometers to 170 nanometers. VUV light can be generated using a plasma process system and from energizing various VUV-generating process gasses. A VUV curing step is executed (fully or partially) prior to executing an etch process to etch away one of the block copolymers. Such VUV exposure can selectively harden one block copolymer while weakening another block copolymer. This hardening and weakening increases etch selectivity enabling more effective etching and results in better patterns.

Abstract: A method for forming patterns includes forming ellipse pillars on an underlying layer. The ellipse pillar has an elongated feature and includes nose sides and long sides connecting the nose sides, and the four ellipse pillars form a diamond array around a separation space. A guide lattice attached to sides of the ellipse pillars is formed to open first windows in the separation space. Second windows are formed in the guide lattice by selectively removing the ellipse pillars. A block copolymer layer is formed to fill the first and second windows. The block copolymer layer is phase-separated to form a first domain and a first matrix in the first window and to form a plurality of second domains and second matrix in the second window. The first and second domains are selectively removed to form first openings and second openings.

Abstract: Methods for repairing low-k dielectrics using a plasma immersion carbon doping process are provided herein. In some embodiments, a method of repairing a low-k dielectric material disposed on a substrate having one or more features disposed through the low-k dielectric material may include depositing a conformal oxide layer on the low-k dielectric material and within the one or more features; and doping the conformal oxide layer with carbon using a plasma doping process.

Abstract: Methods of depositing highly conformal and pure titanium films at low temperatures are provided. Methods involve exposing a substrate to titanium tetraiodide, purging the chamber, exposing the substrate to a plasma, purging the chamber, and repeating these operations. Titanium films are deposited at low temperatures less than about 450° C.

Abstract: Embodiments of the invention provide a substrate etching method, which includes: a deposition operation for depositing a polymer on a side wall of a silicon groove, an etching operation for etching the side wall of the silicon groove, and repeating the deposition operation and the etching operation at least twice. In the process of completing all cycles of the etching operation, a chamber pressure of a reaction chamber is decreased from a preset highest pressure to a preset lowest pressure according to a preset rule. The substrate etching method, according to various embodiments of the invention, avoid the problem of damaging the side wall, thereby making the side wall smooth.

Abstract: A low-pressure chemical vapor deposition (LPCVD) apparatus and a thin-film deposition method thereof. The apparatus comprises a reaction furnace, having reaction gas input pipelines respectively arranged at a furnace opening part and a furnace tail part. During thin film deposition, each reaction gas is synchronously introduced into the reaction furnace through the input pipeline at the furnace opening part and the input pipeline at the furnace tail part.

Abstract: An improved superjunction semiconductor device includes a charged balanced pylon in a body region, where a top of the pylon is large to create slight charge imbalance. A MOSgated structure is formed over the top of the pylon and designed to conduct current through the pylon. By increasing a dimension of the top of the pylon, the resulting device is less susceptible to variations in manufacturing tolerances to obtain a good breakdown voltage and improved device ruggedness.

Abstract: An electronic system, a reduced-noise reference voltage platform for a voltage converter device, and a method of manufacture of a reduced-noise reference voltage platform for a voltage converter device are disclosed. For example, the reduced-noise reference voltage (e.g., ground) platform includes a first conductor unit, a second conductor unit, and an insulator unit interposed between a first surface of the first conductor unit and a first surface of the second conductor unit. The reduced-noise reference voltage platform also includes a phase terminal connected to the first conductor unit, and a reference voltage (e.g., ground) terminal connected to the second conductor unit, wherein a second surface of the second conductor unit forms a platform coupled to the reference voltage (e.g., ground).

Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a chip having a plurality of joint pads; a component having a plurality of metal caps on one side and having a grinded surface on the other side, wherein the metal caps are in contact with the joint pads of the chip.

Abstract: Embodiments of mechanisms for cleaning a wafer are provided. A method for cleaning a wafer includes cleaning a wafer by using a wafer scrubber and cleaning the wafer scrubber in a scrubber cleaning module. An agitated cleaning liquid is applied on the wafer scrubber to clean the wafer scrubber. The method also includes cleaning the wafer or a second wafer by the wafer scrubber after the wafer scrubber is cleaned by the agitated cleaning liquid.

Abstract: A substrate liquid processing apparatus includes a substrate holding unit configured to hold and rotate a substrate; a processing liquid nozzle configured to supply a processing liquid to the substrate; a cylindrical liquid receiving cup configured to receive and recover the processing liquid scattered from the substrate; a housing configured to accommodate the substrate holding unit and the liquid receiving cup; a cup exhaust path connected to the liquid receiving cup to exhaust atmosphere inside the liquid receiving cup; a cup exhaust path pressure sensor configured to detect pressure in the cup exhaust path; a housing pressure sensor configured to detect pressure in the housing outside the liquid receiving cup; and a control unit configured to alert when a difference between a value detected by the housing pressure sensor and a value detected by the cup exhaust path pressure sensor is a predetermined determination reference value or less.

Abstract: A semiconductor processing tool is disclosed, the tool having a frame forming at least one chamber with an opening and having a sealing surface around a periphery of the opening, a door configured to interact with the sealing surface for sealing the opening, the door having sides perpendicular to the door sealing surface and perpendicular to a transfer plane of a substrate, and at least one drive located on the frame to a side of at least one of the sides that are substantially perpendicular to the door sealing surface and substantially perpendicular to the transfer plane of the substrate, the drive having actuators located at least partially in front of the sealing surface and the actuators being coupled to one of the sides of the door for moving the door from a sealed position. The at least one drive is located outside of a substrate transfer zone.