Abstract: Embodiments of substrate supports having a wire mesh plasma containment are provided herein. In some embodiments, a substrate support may include a plate comprising a first surface, an opposing second surface, a thickness bounded by the first and second surfaces, and a first perimetrical surface; a first heater element disposed between the first and second surfaces; a wire mesh disposed between the first and second surfaces; a ground connector mounted to a surface of the plate; at least one electrical connection between the wire mesh and the ground connector; and an elongate shaft comprising a first end and an opposite second end, wherein the plate second surface is mounted to the first end of the shaft.

Abstract: Disclosed is a thermal treatment system which enables a uniform temperature distribution and a uniform concentration distribution of reaction gas in an entire reaction space for a thermal treatment process, a method of performing a thermal treatment, and a method of manufacturing a CIGS solar cell using the same, wherein the thermal treatment system may include a reaction chamber with a reaction space, an external chamber surrounding the reaction chamber, a door chamber provided to open or close the reaction space of the reaction chamber, and an air flow adjusting apparatus for circulation of an flow inside the reaction space of the reaction chamber, wherein the air flow adjusting apparatus includes a driving axis, an air flow suction unit connected with the driving axis, and an air flow discharging unit connected with the air flow suction unit.

Abstract: Disclosed is a process tunnel (102) through which substrates (140) may be transported in a floating condition between two gas bearings (124, 134). To monitor the transport of the substrates through the process tunnel, the upper and lower walls (120, 130) of the tunnel are fitted with at least one substrate detection sensor (S1, . . . , S6) at a respective substrate detection sensor location, said substrate detection sensor being configured to generate a reference signal reflecting a presence of a substrate between said first and second walls near and/or at said substrate detection sensor location. Also provided is a monitoring and control unit (160) that is operably connected to the at least one substrate detection sensor (S1, . . . , S6), and that is configured to record said reference signal as a function of time and to process said reference signal.

Abstract: A wafer container for holding a spaced stack of thin wafers, comprising an H-bar carrier, a base portion for receiving same, a base wafer cushion attached at the bottom wall positioned below the H-bar carrier, the cushion having a plurality of ribs defining slots each with a bottom wafer seating region having a curvature and a pair of ends, each of the ends having a flare whereby the seating region flares outwardly at the ends, a cover portion that connects with the base portion to form a closed interior. The cover portion having an uppermost wall a wafer cushion secured thereto. The cover wafer cushion having a row of wafer engaging finger portions, the finger portions Y shaped and having two legs extending from a support portion and alternatingly extending from opposing support portions, the finger portions may be S shaped with a wafer pad flared in two direction.

Abstract: An apparatus including a stator configured to be stationarily connected to a housing; and a rotor configured to have a robot arm connected thereto. The rotor includes a shaft and an robot arm mount adjustably connected to the shaft. The stator and the rotor include mechanical reference locators to temporarily stationarily locate the robot arm mount to the stator for subsequently stationarily fixing the robot arm mount to the shaft.

Abstract: A production system to facilitate the commonization of front chambers among a plurality of production devices that are different in the kind of a process to be performed for a processing substrate. Control units are provided separately in a processing chamber and a front chamber of a small production device. When the processing-chamber control unit outputs a load request signal, the front-chamber control unit loads a processing substrate to the processing chamber, and outputs a load acknowledgment signal. When the load acknowledgment signal is input, the processing-chamber control unit performs a process for the processing substrate, and outputs an unload request signal after the completion of the process. When the unload request signal is input, the front-chamber control unit unloads the processing substrate, and outputs an unload acknowledgment signal. When the unload acknowledgment signal is input, the processing chamber starts the preparation of the next process.

Abstract: Mechanisms are provided for sacrificial carrier dicing of semiconductor wafers. A bottom layer of a semiconductor wafer is bonded to a top layer of a sacrificial carrier. The semiconductor wafer is diced into a set of chips, such that the dicing cuts through the semiconductor wafer and into the sacrificial carrier and such that the sacrificial carrier dresses a diamond blade of a saw so as to expose one or more new, sharp layers of diamonds on the diamond blade.

Abstract: The present invention provides a dicing tape-integrated film for semiconductor back surface, including a film for flip chip type semiconductor back surface for protecting a back surface of a semiconductor element flip chip-connected onto an adherend, and a dicing tape, the dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material, the film for flip chip type semiconductor back surface being formed on the pressure-sensitive adhesive layer, in which the pressure-sensitive adhesive layer is a radiation-curable pressure-sensitive adhesive layer whose pressure-sensitive adhesive force toward the film for flip chip type semiconductor back surface is decreased by irradiation with a radiation ray.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a shadow ring assembly for a plasma processing chamber includes an annular body including a thermally conductive material. The annular body includes a top surface to face an interior of the plasma chamber, and a bottom surface to face a substrate carrier in the plasma chamber. A plurality of posts are attached to the annular body and positioned substantially below the bottom surface of the annular body. Each of the plurality of posts includes an inner core of thermal pyrolytic graphite (TPG). The shadow ring assembly also includes a plasma resistant coating on the annular body and the plurality of posts.

Abstract: A device includes a semiconductor substrate, a channel region in the semiconductor substrate having a first conductivity type, and a composite drift region in the semiconductor substrate, having a second conductivity type. The composite drift region includes a first drift region and a second drift region spaced from the channel region by the first drift region. The device further includes a drain region in the semiconductor substrate, spaced from the channel region by the composite drain region, and having the second conductivity type. The first drift region has a dopant concentration profile with a first concentration level where adjacent the channel region and a second concentration level where adjacent the second drift region, the first concentration level being higher than the second concentration level. In some embodiments, the first and second drift regions are stacked vertically, with the first drift region being shallower than the second drift region.

Abstract: Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.

Abstract: A method and apparatus for integrating individual III-V MMICs into a micromachined waveguide package is disclosed. MMICs are screened prior to integration, allowing only known-good die to be integrated, leading to increased yield. The method and apparatus are used to implement a micro-integrated Focal Plane Array (mFPA) technology used for sub millimeter wave (SMMW) cameras, although many other applications are possible. MMICs of different technologies may be integrated into the same micromachined package thus achieving the same level of technology integration as in multi-wafer WLP integration.

Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures, and an etch buffer layer. The etch buffer layer includes an overhang component disposed on the upper portion of the gate structures with an edge that extends laterally. The width between the edges of adjacent overhang components is narrower than the width between adjacent gate structures.

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. Embodiments described herein control selectivity of deposition by preventing damage to the dielectric surface, repairing damage to the dielectric surface, such as damage which can occur during the cobalt deposition process, and controlling deposition parameters for the cobalt layer.

Abstract: Wide and narrow mandrels that are used to form sidewall spacers for patterning are formed in a sacrificial layer with openings in wide mandrels near sides of the wide mandrels. Sidewall spacers are formed on the sides of mandrels and the sacrificial layer is removed. The sidewall spacers are then used for patterning of underlying layers.

Abstract: Methods of forming a SAV using a selective SAQP or SADP process are provided. Embodiments include providing on a TiN layer and dielectric layers alternating mandrels and non-mandrel fillers, spacers therebetween, and a metal cut plug through a mandrel or a non-mandrel filler; removing a non-mandrel filler through a SAV patterning stack having an opening over the non-mandrel filler and adjacent spacers, forming a trench; removing a mandrel through a second SAV patterning stack having an opening over the mandrel and adjacent spacers, forming a second trench; etching the trenches through the TiN and dielectric layers; forming plugs in the trenches; removing the mandrels and non-mandrel fillers, forming third trenches; etching the third trenches through the TiN layer; removing the metal cut plug and spacers and etching the third trenches into the dielectric layer; removing the plugs; and filling the trenches with metal.

Abstract: A semiconductor device and method of fabricating the semiconductor device are provided. The semiconductor device includes a first substrate including a front-end device containing a transistor, a radio frequency (RF) device and a first interconnect structure, and a second substrate containing a cavity disposed at a location corresponding to a location of the RF device. The first substrate and the second substrate are bonded together such that the first surface of the first substrate is facing the cavity in the second substrate, and the cavity is over the RF device. Because of the cavity, the distance between the second substrate and the RF device is relatively large so that the second substrate has less impact on the performance of the RF device, thereby improving the performance of the semiconductor device.

Abstract: A method for manufacturing a through-hole silicon via (TSV) employs the conventional trench insulation process to readily manufacture a through-hole silicon via (TSV) with achievement of an effective electrical insulation between the through-hole silicon via (TSV) and the silicon.

Abstract: A method of processing a wafer having a device area where a plurality of devices are formed and a peripheral marginal area surrounding the device area on the front side of the wafer is disclosed. The devices are formed in regions defined by division lines. Each device has a plurality of bump electrodes on the front side. A first laser beam is applied through dicing tape from the back side along the boundary between the device area and the peripheral marginal area, with the focal point of the first laser beam set inside the wafer, thereby forming an annular modified layer inside the wafer. A second laser beam is applied through the dicing tape from the back side along each division line with the focal point of the second laser beam set inside the wafer, thereby forming a modified layer inside the wafer along each division line.

Abstract: A method comprises removing a dummy gate electrode layer to form a gate trench in a dielectric layer over a substrate, forming a resistor trench over the substrate, depositing a plurality of films on a bottom of the gate trench, a bottom of the resistor trench, sidewalls of the gate trench and sidewalls of the resistor trench, depositing a gate electrode layer over the plurality of films and removing an upper portion of the gate electrode layer until the gate electrode layer is removed from the resistor trench.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary fabrication method involves forming a layer of gate electrode material overlying a semiconductor substrate, forming a layer of masking material overlying the gate electrode material, and patterning the layer of masking material to define a channel region within a well region in the semiconductor substrate that underlies the gate electrode material. Prior to removing the patterned layer of masking material, the fabrication process etches the layer of gate electrode material to form a gate structure overlying the channel region using the patterned layer of masking material as an etch mask and forms extension regions in the well region using the patterned layer of masking material as an implant mask. Thereafter, the patterned layer of masking material is removed after forming the gate structure and the extension regions.

Abstract: A semiconductor structure includes non-metal semiconductor alloy containing contact structures for an n-type field effect transistor (nFET) and a metal semiconductor alloy containing contact structures for a p-type field effect transistor (pFET). Notably, each non-metal semiconductor alloy containing contact structure includes a titanium liner that directly contacts a topmost surface of a source/drain region of the nFET, while each metal semiconductor alloy containing contact structure includes a Ni—Pt semiconductor alloy contact that directly contacts a surface of a source/drain region of the pFET.

Abstract: Among other things, an integrated circuit and method for routing electrical pathways of an integrated circuit is provided. The integrated circuit comprises a buffer chain coupling a first cell of the integrated circuit to a second cell of the integrated circuit. An electrical pathway coupling a first inverter of the buffer chain with a second inverter of the buffer chain extends through a first set of metal layers and is routed to form a pulse-like shape having an apex at a top layer of the first set.

Abstract: An embodiment of a process for manufacturing a system for electrical testing of a through via extending in a vertical direction through a substrate of semiconductor material envisages integrating an electrical testing circuit in the body to enable detection of at least one electrical parameter of the through via through a microelectronic buried structure defining an electrical path between electrical-connection elements towards the outside and a buried end of the through via; the integration step envisages providing a trench and forming a doped buried region at the bottom of the trench, having a doping opposite to that of the substrate so as to form a semiconductor junction, defining the electrical path when it is forward biased; in particular, the semiconductor junction has a junction area smaller than the area of a surface of the conductive region in a horizontal plane transverse to the vertical direction, in such a way as to have a reduced reverse saturation current.

Abstract: Presented herein is a device comprising a common node disposed in a first wafer' a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node.

Abstract: Substrate components for packaging IC chips and electronic device packages are disclosed. A substrate component for packaging IC chips comprises: a glass core base with at least one conductive through via connecting a combination of metallization and dielectric structures on both an upper surface and a lower surface of the glass core base; and, tapered edges created at a peripheral region of the glass core base; wherein dielectric layers are disposed over the tapered edges at the peripheral region of the glass core base. In accordance with an embodiment of the invention, the dielectric layers have a substantial planar upper surface, a lower surface conformably interfaced with the tapered edges at peripheral region of the glass core base, and a steep cutting face with the tapered edges of the glass core base.

Abstract: A method for fabrication of a lid for a microelectronic device is described, wherein the microelectronic device comprises of a die and a laminate. A gel is formed having a coefficient of thermal expansion (CTE) within a threshold percentage value of either a CTE of the die or a CTE of the laminate of the microelectronics device. A metal piece is inserted into the gel to form a lid.

Abstract: Methods and apparatus are disclosed for a package or a package-on-package (PoP) device. An IC package or a PoP device may comprise an electrical path connecting a die and a decoupling capacitor, wherein the electrical path may have a width in a range from about 8 um to about 44 um and a length in a range from about 10 um to about 650 um. The decoupling capacitor and the die may be contained in a same package, or at different packages within a PoP device, connected by contact pads, redistribution layers (RDLs), and connectors.

Abstract: An apparatus includes a package structure. The package structure includes a chip, a conductive structure over the chip, a molding structure surrounding and underneath the chip, and a first passivation layer over the conductive structure. The chip includes an optical component and a chip conductive pad. The conductive structure is electrically coupled to the chip conductive pad. The conductive structure has a planar portion substantially in parallel with an upper surface of the chip. The first passivation layer has a first opening defined therein. The first opening exposes a portion of the planar portion. The package structure is configured to receive an electrical coupling through the first opening in the first passivation layer.

Abstract: A package for a microelectronic die (110) includes a first substrate (120) adjacent to a first surface (112) of the die, a second substrate (130) adjacent to the first substrate, and a heat spreader (140) adjacent to a second surface (111) of the die. The heat spreader makes contact with both the first substrate and the second substrate.

Abstract: A semiconductor device includes a semiconductor element having a semiconductor chip and connection terminals, a cooling fin to which the semiconductor element is fixed, and an external cooling body having a passage for cooling medium, the cooling fin being fixed to the external cooling body. The semiconductor element has a protruding cooling block that is inserted and fixed to the cooling fin, which in turn is fixed to the external cooling body such that the cooling fin is in contact with the cooling medium.

Abstract: Electronic device assemblies employing dual phase change materials and vehicles incorporating the same are disclosed. In one embodiment, an electronic device assembly includes a semiconductor device having a surface, wherein the semiconductor device operates in a transient heat flux state and a normal heat flux state, a coolant fluid thermally coupled to the surface of the semiconductor device, and a phase change material thermally coupled to the surface of the semiconductor device. The phase change material has a phase change temperature at which the phase change material changes from a first phase to a second phase. The phase change material absorbs heat flux at least when the semiconductor device operates in the transient heat flux state.

Abstract: A thermal management system is provided. The thermal management system includes at least one heat sink including one or more respective fins, wherein the one or more fins include one or more respective cavities. The thermal management system also includes a synthetic jet stack including at least one synthetic jet mounted within each of the respective cavities employing at least one engaging structure to provide a rigid positioning of the synthetic jet stack within the fins, wherein the synthetic jet includes at least one orifice through which a fluid is ejected.

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract: An electrode layer is formed on a gate insulating film. An interlayer insulating film is formed on the gate insulating firm. A lower pad is formed by a damascene method. Next, a through hole is formed, and a first interlayer insulating film, which is provided with a projected portion that is in the same pattern as a lower insulating film, is exposed within the through hole at the same time. After etching the first interlayer insulating film so that a part of the projected portion remains as an etching residue, a via insulating film is formed and the via insulating film at the bottom of the through hole is etched. After that, a through electrode is formed by plating an electrode material on the inner side of the via insulating film on the through hole.

Abstract: One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, and a plurality of solder bump structures. The substrate includes a first plurality of interconnects disposed on a first surface of the substrate. The integrated circuit die includes a second plurality of interconnects disposed on a first surface of the integrated circuit die. The plurality of solder bump structures couple the first plurality of interconnects to the second plurality of interconnects. The first plurality of interconnects are configured to be substantially aligned with the second plurality of interconnects when the integrated circuit package is at a first temperature within a range of about 0° C. to about ?100° C. The first plurality of interconnects are configured to be offset from the second plurality of interconnects when the integrated circuit package is at a temperature above the first temperature.

Abstract: The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a lead frame having a die paddle and a lead. A chip is disposed over the die paddle of the lead frame. The semiconductor device further includes a clip, which is disposed over the chip. The clip couples a pad on the chip to the lead of the lead frame. The clip also includes a heat sink.

Abstract: A semiconductor device has a first semiconductor die. A first interconnect structure, such as a conductive pillar including a bump formed over the conductive pillar, and second interconnect structure are formed in a peripheral region of the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die between the first interconnect structure and the second interconnect structure. A height of the second semiconductor die is less than a height of the first interconnect structure. A footprint of the second semiconductor die is smaller than a central region of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and second semiconductor die. Alternatively, the second semiconductor die is disposed over a semiconductor package including a plurality of interconnect structures. External connectivity from the single side fo-WLCSP is performed without the use of conductive vias to provide a high throughput and device reliability.

Abstract: A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV.

Abstract: A semiconductor package includes a substrate including connection pads, a first semiconductor, and conductive wires. The first semiconductor chip is stacked on the substrate and includes bonding pads, non-bonding pads, and a routing area that is provided adjacent a center of an edge of the first semiconductor chip. The conductive wires are connected to the bonding pads and the connection pads. The bonding pads are disposed to form at least one column in a direction extending along the edge of the first semiconductor chip and are not disposed in the routing area. The non-bonding pads are disposed to form a column different from the at least one column formed by the bonding pads.

Abstract: In one embodiment, the present invention includes a semiconductor device mounted to a first side of a circuit board; and at least one voltage regulator device mounted to a second side of the circuit board, the second side opposite to the first side. Examples of the voltage regulator devices include output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.

Abstract: The width of scribe lines may be reduced in semiconductor devices by applying a process technique in which trenches may be formed first from the rear side on the basis of a required width of the corresponding trenches, while subsequently it may be cut into the substrate from the front side on the basis of a reduced thickness of the corresponding saw blades, thereby also enabling a reduction of the scribe line width. Furthermore, contamination of the front side, i.e., of the metallization system, may be reduced, for instance, by performing an optional intermediate cleaning process.

Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.

Abstract: Integrated circuit packages with openings surrounding a conductive via on a substrate layer are disclosed. An integrated circuit package may include a substrate layer with upper and lower surfaces. A conductive via may extend between the upper and lower surfaces of the substrate layer. The integrated circuit package further includes multiple openings in the substrate layer that may be distributed evenly in the substrate layer surrounding the conductive via. The multiple openings reduce signal insertion loss of the conductive via.

Abstract: An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second conductive line on a second metal level of the integrated circuit. The integrated circuit further includes a slot via electrically connecting the first conductive line with the second conductive line. The slot via overlaps with the first conductive line and the second conductive line. The slot via extends beyond a periphery of at least one of the first conductive line or the second conductive line.

Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Abstract: Digital data system disposed on a substrate includes a digital data device and at least one digital data interconnect disposed on the substrate. The digital data interconnect is comprised of a plurality of material layers stacked to form a three-dimensional structure. The material layers form a conductive shield, a plurality of straps which are periodically spaced along an interior length of the shield, and a core which includes one or more conductors. The conductors extends along the length of the tubular form parallel to the opposing walls and are suspended on the straps, separated from the conductive shield by an air gap. First and second conductors of the core can facilitate a differential signaling mode.

Abstract: A low-stress contact via structure for a device employing an alternating stack of insulating layers and electrically conductive layers over a substrate can be formed by forming a trench extending to the substrate through the alternating stack. After formation of an insulating spacer and a diffusion barrier layer, a remaining volume of the trench can be filled with a combination of an aluminum portion and a non-metallic material portion to form a contact via structure. The non-metallic material portion can include a semiconductor material portion or a dielectric material portion, and can prevent reflow of the aluminum portion and generation of a cavity in subsequent thermal processes. If a semiconductor material portion is employed, the aluminum portion and the semiconductor material portion can exchange places during a metal induced crystallization anneal process of the semiconductor material.

Abstract: A wafer to wafer structure includes a first wafer, a second wafer. A first bonding layer and a second bonding layer are disposed between the first wafer and the second wafer. A plurality of first interconnects are disposed within the he first bonding layer. A plurality of second interconnects are disposed within the second bonding layer. An interface is disposed between the first bonding layer and the second bonding layer. At least a through silicon via penetrates the first wafer, the first bonding layer and the interface to enter the second bonding layer. The through silicon via contacts one of the first interconnects and one of the second interconnects.