Abstract: A method of erasing a nonvolatile memory device which includes a plurality of memory blocks includes receiving an erase command; erasing a selected memory block among the plurality of memory blocks in response to the erase command; and performing an operation of checking whether a threshold voltage of a selection transistor connected to at least one selection line for selecting strings included in the selected memory block is changed while performing an erase verification operation for checking whether the selected memory block is normally erased.

Abstract: A multiple-time programmable (MTP) structure is provided that can operate using a power supply with a supply voltage of 1.5 V to 5.5 V. When the supply voltage is above a first voltage, a first circuit is configured to induce a second constant voltage at a drain of a second transistor, and to induce the second constant voltage on a terminal in a third circuit. In some embodiments, the third circuit provides a third constant voltage on a gate of a third transistor. When the supply voltage is below the first voltage, a fifth circuit is configured to induce a fourth constant voltage on a terminal in the third circuit. The fourth constant voltage is substantially equal to the second constant voltage.

Abstract: A method of reading data in a memory system including a non-volatile memory device, includes reading first data stored in a first block using a first read scheme capable of detecting/correcting an error in the first data, and upon determining an uncorrected error in the first data, setting the first block as a first temporary bad block and reading second data stored in the first temporary bad block using a second read scheme different from the first read scheme.

Abstract: In a method of reading a memory device, difference information is generated based on a distance difference between a position of a read word-line and a position of a boundary word-line. The read word-line corresponds to a read address. The boundary word-line corresponds to a last programmed word-line in a memory block included in a memory cell array. A read word-line voltage and an adjacent word-line voltage are determined based on the difference information. The read word-line voltage is applied to the read word-line. The adjacent word-line voltage is applied to an adjacent word-line that is adjacent to the read word-line. A read data corresponding to the read address is outputted based on the read word-line voltage and the adjacent word-line voltage.

Abstract: An operation method of a nonvolatile memory system in accordance with example embodiments of inventive concepts includes detecting an on-cell count of the memory cells using a sampling start voltage, comparing the detected on-cell count with a reference value, setting a plurality of sampling voltages based on the comparison result, performing a sampling operation with respect to the memory cells using the sampling voltages, and detecting an optimum read voltage for distinguishing any one program state among the program states based on a result of the sampling operation.

Abstract: A semiconductor memory device according to an embodiment includes a control circuit, during data write to a memory cell, sequentially executing: an erasing stage in which a threshold value of the memory cell is transitioned into an erase distribution; a preliminary programming stage in which the threshold value is transitioned into a temporal distribution corresponding to write data; and a main programming stage in which the threshold value is transitioned into a program distribution corresponding to the write data, and the control circuit executing a main reading stage, during the data read to a first memory cell, which includes a main reading step of adjusting a read pass voltage to be applied to a neighboring word line based on a magnitude of a threshold value of the neighboring memory cell, and reading whether the first memory cell is an erase level.

Abstract: A nonvolatile memory device includes a first resistive memory cell connected to a first word line, a second resistive memory cell connected to a second word line that is different from the first word line, a clamping unit connected between a sensing node and the first resistive memory cell to provide a clamping bias to the first resistive memory cell, a reference current supplying unit connected to the second resistive memory cell to supply a reference current, and a sense amplifier connected to the sensing node to sense a level change of the sensing node, wherein when the first word line is enabled, the second word line is disabled.

Abstract: A non-volatile memory system may include a mechanism for analyzing and measuring/predicting data loss without reading data in memory cells of the non-volatile memory. The system may include a data management module that utilizes charge loss measurements of a reference charge device that is independent of the memory cells that are configured to store data. The measured charge loss may be correlated with a predetermined data loss profile for the non-volatile memory that corresponds with charge loss on the reference charge device. The method may include charging the reference charge device when the non-volatile memory system is being powered down and making the charge loss measurement, and estimating data loss, when the non-volatile memory system is later powered up. The non-volatile memory cells may be refreshed when the estimated data loss is above a predetermined threshold.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Abstract: A disclosed example includes selectively precharging first bitlines of first multi-level cell (MLC) memory cells of a wordline without precharging second bitlines of second MLC memory cells of the wordline during a program verify. First strobe state outputs of the first MLC memory cells are obtained based on first sensed threshold voltage levels of the first MLC memory cells sensed at a first time. Second strobe state outputs of the first MLC memory cells are obtained based on second sensed threshold voltage levels of the first MLC memory cells sensed at a second time. Based on the first and second strobe state outputs, a first MLC memory cell of the first MLC memory cells is programmed using a first programming pulse, and a second MLC memory cell of the first MLC memory cells is programmed using a second programming pulse having a relatively higher voltage than the first programming pulse.

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode.

Abstract: A memory device includes a memory cell which has one cell selection section and a storage section which is connected in series with respect to the cell selection section and which is selected as an access target for writing or reading by the cell selection section, in which the storage section is provided with a plurality of memory elements which are able to be written one time only and where information is held by changing resistance values in a non-written state and a written state.

Abstract: Embodiments include circuits, apparatuses, and systems for programmable memory device sense amplifiers. In embodiments, an electronic circuit may include a programmable memory device having a first resistance in a first state and a second resistance in a second state, a reference element, an amplifier to generate a first output signal based at least in part on the resistance of the programmable memory device and a second output signal based at least in part on a current from the reference element, and a comparator to determine a state of the programmable memory device based on the first and second output signals from the amplifier. Other embodiments may be described and claimed.

Abstract: Provided is a magnetic domain wall displacement memory cell, including a recording layer including a magnetic film, the recording layer including: a magnetization reversal region in which magnetization is reversible; and first and second magnetization fixed regions that supply a spin-polarized electron to the magnetization reversal region. The magnetic domain wall displacement memory cell is configured so that a first region in which magnetization reversal occurs due to a first current flowing in a direction parallel to a film surface of the recording layer and a first magnetic field component in the direction parallel to the film surface of the recording layer is formed, and a second region in which no magnetization reversal occurs is formed.

Abstract: Provided is a shift register unit, a gate driving circuit and method, and a display apparatus. The shift register unit comprises an input module, a pulling-up module, a first control module, a second control module, a first reset module and a pulling-down module. It can be avoided that a relative large drift occurs in a threshold voltage of a pulling-down TFT (T8) by controlling a voltage at the pulling-down control node (PD) of the shift register unit, thus effectively increasing reliability of the shift register unit in operation.

Abstract: The present disclosure provides a bi-directional scanning gate driver and its shift register unit. The shift register unit comprises a shift trigger signal/reset signal input terminal (1), a reset signal/shift trigger signal input terminal (2), the first clock terminal (6) and an output terminal (8). The shift trigger signal/reset signal input terminal (1) and the reset signal/shift trigger signal input terminal (2) are coupled to one of the shift trigger signal and the reset signal. When it is switched between the forward shift and the reverse shift, the signals coupled to the shift trigger signal/reset signal input terminal (1) and the reset signal/shift trigger signal input terminal (2) are exchanged. The first clock terminal (6) is coupled to a clock signal for providing a driving level to the output terminal (8). The circuit of such a shift register unit is constituted of at least four transistors and one capacitor.

Abstract: Described herein are techniques, systems, and circuits for addressing image data according to blocks. For example, in some cases, the address space may be divided into high order address bits and low order address bits. In these cases, an address circuit may twist an address space by shifting the high order bits and low order bits of an address in a rightward direction, shifting the low order bits of the address in a leftward direction, and shifting the high order bits and the low order bits of the address in the leftward direction. The circuit may modify the address value and untwist the address space. For example, the untwisting may include shifting the high order bits and the low order bits of an address in the rightward direction, shifting the low order bits of the address in the rightward direction, and shifting the high order bits and the low order bits of the address in the leftward direction.

Abstract: System and method for implementing a memory test language compiler. The compiler includes a fast semantic processor for interpreting programming patterns in a test program, including converting stateful patterns into stateless patterns, and a device access timing generation module for generating an output based on the stateless patterns. The fast semantic processor can generate a closure for a device access line as the output. In the state of the closure, each device access line is in a closed state. A functor is formed from the interdependency of the variables and the loop dependency and a cache is used to handle recursive variables. The functor is propagated to device access lines as output, wherein the functor references the cache when needed.

Abstract: An integrated circuit memory includes a memory array, including a plurality of data lines. A buffer structure is coupled to the plurality of data lines, including a plurality of storage elements to store bit-level status values for the plurality of data lines. The memory includes logic to indicate bundle-level status values of corresponding bundles of storage elements in the buffer structure based on the bit-level status values of bits in the corresponding bundles. A plurality of bundle status circuits is arranged in a daisy chain and coupled to respective bundles in the buffer structure, producing an output of the daisy chain indicating detection of a bundle in the first status. Control circuitry executes cycles to determine the output of the daisy chain, each cycle clearing a bundle status circuit indicating the first status if the output indicates detection of a bundle in the first status in the cycle.

Abstract: A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program.

Abstract: A memory device may include a plurality of normal word lines; a plurality of redundancy word lines capable of replacing the word lines; a hammering information storage unit capable of storing an address of a row hammering word line of the normal word lines and the redundancy word lines; an address generation unit capable of generating an address of a normal word line or redundancy word line adjacent to a normal word line or redundancy word line corresponding to the address stored in the hammering information storage unit; and a refresh control unit capable of selecting the normal word line or redundancy word line corresponding to the address generated by the address generation unit for performing an additional refresh operation.

Abstract: An integral pressurized light water reactor having most of the components of a primary side of a pressurized water reactor nuclear steam supply system housed in a single pressure vessel with a pressurizer separated from the remaining reactor system by a surge separator having multiple layers of separated steel plates with a number of concentric baffles extending therebetween. A circuitous flow path is provided through and between the plates and concentric baffles and a relatively stagnant pool of coolant is maintained within an innermost zone between the plates to provide thermal isolation.

Abstract: A residual heat removal system for a nuclear power plant. The residual heat removal system for a nuclear power plant may include an air duct provided on an outside of a reactor containment building, a heat exchanger disposed on an inside of the air duct, a first pipe to transfer, to the heat exchanger, steam generated in a steam generator disposed on an inside of the reactor containment building, and second pipe to transfer, to the steam generator, water condensation that is cooled and condensed in the heat exchanger, wherein the heat exchanger is air-cooled using outside air flowing inside of the air duct.

Abstract: A method of operating a power generator is provided. The method includes determining an amount of oxides on a heat transfer surface of the power generator as a function of a concentration of a noble metal substance in the oxides; and altering operation of the power generator when the amount of oxides on the heat transfer surface reaches a predetermined value. A method of operating a nuclear reactor is also provided.

Abstract: A method of removing the upper internals assembly from a nuclear reactor pressure vessel for refueling that simultaneously disconnects two or more of the in-core instrument thimble assemblies from the reactor vessel penetrations through which their signal cables extend. The signal cables are connected to the penetrations with an electrical connector that supports the two or more in-core instrumentation thimble assembly signal leads. Before the electrical connector is disconnected, water in the vessel is lowered below the connection so that the process is performed in a dry environment.

Abstract: The method for filling water into and changing the air of a main circuit of a water-cooled nuclear reactor includes a step of placing a connection and fluid isolation device which is connected to a hot leg of each cooling loop of the main circuit so as to substantially insulate, from inside the vessel, the assembly of hot legs. The method also includes a step of injecting water through an injection circuit on at least one hot leg until each cooling loop is filled with water having changed the air from a steam generator and until the water level in the vessel reaches above the side openings of the vessel that correspond to the loops, after which the connecting device is taken out of the vessel. The connecting device is capable of using telescopic connection elements.

Abstract: A method for preparing low level radioactive hazardous wastes (LLHZ) for disposal in a landfill. The method includes providing a softsided transportable container at a hazardous debris collection site, where the softsided container has at least three layers of materials, an outer, middle and an inner layer, where the middle layer is a water impervious material. Each layer has a closable opening located on the top of the softsided layer. Hardsided closed containers containing LLHZ located in the interior of the hard container are loaded into the interior of the softsided container. Each layer of the softsided container is then closed, and the package transported and shipped to a disposal site for burial.

Abstract: A Cu—Si—Co-based alloy having an enhanced spring limit is provided. The copper alloy comprises 0.5-2.5 mass % of Co, 0.1-0.7 mass % of Si, the balance Cu and inevitable impurities, wherein, from a result obtained from measurement of an X ray diffraction pole figure, using a rolled surface as a reference plane, a peak height at ? angle of 90° among diffraction peaks in {111} Cu plane with respect to {200} Cu plane by ? scanning at ?=35° is at least 2.5 times that of a standard copper powder.

Abstract: An end-to-end system/process for producing advantageous end products from a raw biomass feedstock is provided. The process includes steps for enhancing biomaterial feedstock, biochar generation and end-product fabrication. The method steps may be employed in selecting, treating and handling biomass materials and their additive inputs to tailor their end performance. Each operative step in the process may be employed to enhance the overall effectiveness of biochar generation and use. Charring furnace design and operational parameters are provided that generate desirable biochar material for various applications, including specifically fabrication of ultra-capacitor electrodes and electric battery components.

Abstract: Employing a compact molded from powder of metal or the like as an electrode 11, generating pulsed discharges between the electrode 11 and a treating portion Wa of work W in working oil L as a mixture with powder of semiconductor or conductor mixed therein, using discharge energy thereof for locally fusing surface regions of the treating portion Wa of work W, showering molten pieces of electrode material or reactants of the electrode material onto the treating portion Wa of work W, forming a covering film C on the treating portion Wa of work W.

Abstract: The present invention aims to provide electroconductive microparticles which are less likely to cause disconnection due to breakage of connection interfaces between electrodes and the electroconductive microparticles even under application of an impact by dropping or the like and are less likely to be fatigued even after repetitive heating and cooling, and an anisotropic electroconductive material and an electroconductive connection structure each produced using the electroconductive microparticles. The present invention relates to electroconductive microparticles each including at least an electroconductive metal layer, a barrier layer, a copper layer, and a solder layer containing tin that are laminated in said order on a surface of a core particle made of a resin or metal, the copper layer and the solder layer being in contact with each other directly, the copper layer directly in contact with the solder layer containing copper at a ratio of 0.

Abstract: Durable fine wire electrical conductors are robust, durable, small in profile, and light weight, yet capable of operating under extreme environmental conditions. Formed of a glass, silica, sapphire or crystalline quartz fiber core with a metal coating and one or more polymer layers, a unipolar electrical conductor can have an outer diameter as small as about 300 microns or even smaller. The metal buffer coating may be deposited directly on the glass/silica fiber, or upon an intermediate layer between the glass/silica fiber and metal, consisting of carbon and/or polymer. The resulting metallized glass/silica fibers are extremely durable, can be bent through small radii and will not fatigue even from millions of iterations of flexing. Bipolar electrical conductors can include several insulated metallized glass/silica fibers residing side by side, or can be coaxial with two or more insulated metal conductive paths. An outer protective sheath of a flexible polymer material can be included.

Abstract: A method for manufacturing a high frequency cable that includes covering a central conductor made from aluminum or an aluminum alloy with a covering layer made from copper; and wire drawing of the central conductor covered by the covering layer using dies at multiple steps, each of the dies having a cross-section reduction rate of 20% to 29% with an entire reduction angle of 16 degrees, to form a fiber-like structure in a longitudinal direction in the covering layer, and to form an intermetallic compound layer having greater volume resistivity than the covering layer between the central conductor and the covering layer.

Abstract: Exemplary methods for manufacturing a wire and resultant wires are disclosed herein. The method includes extruding a cross-linkable polymer that is substantially free of curing agent about a conductive core, then adding a curing agent to the extruded wire pre-product, then heat-curing the extruded wire pre-product.

Abstract: The present invention concerns a control device for an electrical circuit integrated on a substrate made of polymeric material, incorporating carbonaceous conductive structures which define at least one track having improved electrical conductivity properties with respect to the substrate, which control device includes an operating area adapted to be acted on by a user and having a pressure-deformable structure adapted to disturb the electrical properties of the track by a piezo-resistive effect, wherein the conductive track includes at least one linear segment which has a winding progression at the operating area.

Abstract: An aspect of the present invention relates to a method of manufacturing hexagonal strontium ferrite magnetic powder, which comprises melting a starting material mixture which has a composition, as a composition converted into an oxide, lying within a region enclosed by the following four points: (a) SrO=48.0 mol %, Fe2O3=17.2 mol %, B2O3=34.8 mol %; (b) SrO=55.9 mol %, Fe2O3=17.7 mol %, B2O3=26.4 mol %; (c) SrO=41.7 mol %, Fe2O3=40.9 mol %, B2O3=17.4 mol %; (d) SrO=36.7 mol %, Fe2O3=40.1 mol %, B2O3=23.2 mol %; in a ternary diagram with SrO, Fe2O3, which may include an Fe substitution element, and B2O3 as apexes, to provide a melt, and quenching the melt to obtain a solidified product; and heat treating the solidified product to precipitate hexagonal strontium ferrite magnetic particles within the solidified product.

Abstract: A method for producing a sintered R-T-B based magnet includes providing a sintered R-T-B based magnet body, of which the rare-earth-element mole fraction falls within the range of 31 mass % to 37 mass %; providing an RH diffusion source including a heavy rare-earth element RH (which is at least one of Dy and Tb) and 30 mass % to 80 mass % of Fe; loading the sintered magnet body and the RH diffusion source into a processing chamber so that the magnet body and the diffusion source are movable relative to each other and readily brought close to, or in contact with, each other; and performing an RH diffusion process by conducting a heat treatment on the sintered magnet body and the RH diffusion source at a process temperature of 700° C. to 1000° C. while moving the sintered magnet body and the RH diffusion source either continuously or discontinuously.

Abstract: The invention relates to a process of and apparatus for forming a magnetic structure on a substrate and a magnetic structure formed by such a process and apparatus. The magnetic structure comprises a matrix in which magnetic particles are embedded. The apparatus for forming the magnetic structure on the substrate comprises a source of matrix deposits the matrix material onto the substrate to form the matrix, and comprises a source of magnetic particles which deposit the magnetic particles onto the matrix as the matrix forms to embed the magnetic particles in the matrix. Each magnetic particle comprises a core covered with a layer of metal, at least one of the matrix material and the core is of ferromagnetic material and the core and the layer of metal are of different materials.

Abstract: There is provided a power inductor including: a main body; and first and second external electrodes formed on both end portions of the main body, wherein the main body includes: upper and lower cover layers; at least one coil support layer having a through hole formed in a center thereof, at least one first recess portion formed in both lateral surfaces thereof and a plurality of second recess portions formed in respective corners thereof, and disposed between the upper and lower cover layers; and first and second coil layers formed on both surfaces of the coil support layer and having respective one ends thereof connected to the first and second external electrodes.

Abstract: A coil device (1) comprising a coil winding (3) for an electromagnetic actuating device or an electromagnetic sensor, having a winding wire (11) which has an insulating element and which is ran to at least one contacting element (5, 15) that is designed as a metal part, in particular a stamped part, and a stripped section of the winding wire is received at the contacting element between the contacting element (5, 15) and a metal cover (6) and fused to the contacting element (5, 15). A recess (8) is impressed into the contacting element (5, 15), the recess receiving the winding wire (11) in some sections and being designed with a winding wire inlet geometry.

Abstract: An apparatus of the present disclosure has a first magnet coupled to a frame and a position of the first magnet vertically adjustable and a second magnet coupled to the frame and positioned and arranged in vertical alignment with the first magnet along a magnetic axis common to the first and second magnets, such that the first magnet is free to rotate about the magnetic axis. The spinning magnet apparatus demonstrates that the external magnetic field caused by the magnets is not fixed to the material matrix of the magnets.

Abstract: A magnet plate for manufacturing a display device is disclosed. In one aspect, the plate includes at least two magnet units formed in a first direction, each magnet unit including first and second linear motion (LM) guides. The plate also includes a support plate attached to the LM guides. The magnet unit also includes a magnet supporter comprising an upper portion including a magnet coupling part, a lower portion including a plurality of cam followers, and at least two first transfer plate coupling protrusions formed at a predetermined interval. The magnet unit further includes a magnet guide plate placed beneath the magnet supporter and including a guide cam hole into which the cam follower is inserted. The guide cam hole is oblique with respect to the first direction and has a predetermined width such that the cam follower moves within the guide cam hole.

Abstract: A circuit for driving an actuator including a closing coil and an opening coil, the circuit including a first electrical switch, a second electrical switch, a third electrical switch, a first diode, a second diode, a third diode, and a capacitor electrically connected to a second terminal of the third electrical switch. The circuit is structured such that controlling the state of the first, second, and third transistors causes current flowing through the circuit to flow through one of the closing coil and the opening coil and to not flow through the other of the closing coil and the opening coil.

Abstract: An actuator can include a housing, plunger, core assembly, biasing member, and first and second electromagnets. The housing can have two end poles, and a central pole therebetween. The plunger can be configured for axial translation relative to the housing. The core assembly can move between first and second positions and can be coupled to the plunger. The core assembly can include first and second cores spaced apart by a permanent magnet. The first and second electromagnets can be spaced apart by the central pole and can have opposite polarities. The biasing member can bias the plunger toward a first plunger position when the core assembly is in the first position, and can bias the plunger toward a second plunger position when the core assembly is in the second position.

Abstract: The invention relates to a solenoid housing fabricated by a method which allows a manufacturer to produce a high performing product while minimizing manufacturing complexity and time. The instant invention uses cold-forging techniques to reduce the need for fine machining processes.

Abstract: A solenoid assembly having a solenoid core, coil and flux plate. The flux plate has inner and outer ring members connected by connecting members. A stop member with a ledge is used to selectively prevent an armature member from coming into contact with the flux plate.

Abstract: An actuator for a switchgear is disclosed, which can include a core having a package of core element layers made of magnetic material, and permanent magnets between the core elements, fixed with screws with screwheads. A movable plate is configured to open or close a magnetic circuit to the core, and an electromagnetic coil is surrounded by the core elements. To avoid mechanical infringement of the environment of the actuator by prominent screwheads, without weakening the magnetic force, screws for mechanical connection of the core element layers and the permanent magnets can be oriented perpendicular to the plane of stacking of the core element layers, and screw-holes for the screws can be implemented through the core element layers and the permanent magnets, and the screw-holes can end in diameter extended openings, so that the screwheads and/or the screwnuts are recessed into the diameter extended openings.

Abstract: A printed wiring board includes a first core substrate having an opening portion, an inductor component accommodated in the opening portion of the first core substrate, a first buildup layer formed on a first surface of the first core substrate and the inductor component, and a second buildup layer formed on a second surface of the first core substrate and the inductor component on the opposite side with respect to the first surface of the first core substrate. The inductor component has a second core substrate, a buildup layer formed on a surface of the second core substrate and a coil layer formed on the buildup layer, and the second buildup layer has a coil layer and a via conductor connecting the coil layer in the second buildup layer and the coil layer formed on the buildup layer in the inductor component.

Abstract: A varainductor includes a spiral inductor over a substrate, the spiral inductor comprising a ring portion. The varainductor further includes a ground ring over the substrate, the ground ring surrounding at least the ring portion of the spiral inductor and a floating ring over the substrate, the floating ring disposed between the ground ring and the spiral inductor. The varainductor further includes an array of switches, the array of switches is configured to selectively connect the ground ring to the floating ring.

Abstract: A converter unit includes: a housing with a moulded-on hollow cylinder that extends into the housing; a non-magnetic toroidal core supporting a first secondary winding, contacting the housing bottom concentrically with the hollow cylinder and is embedded in a solid compound; a magnetic toroidal core supporting a second secondary winding, arranged concentrically with the hollow cylinder above the non-magnetic toroidal coil; and a casting compound with which the housing opening is closed. To achieve a compact converter unit, a first planar spacing element is arranged between the first and the second secondary windings, directly contacting the first secondary winding and the second secondary winding. In addition, electrically insulating particles fill out the space between the second secondary winding and the housing wall, and the casting compound extends at least up to the particles, which lie at the top towards the housing opening.