Patents Issued in November 17, 2016
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Publication number: 20160336199Abstract: A surface boundary is formed between a sealed surface of a thermosetting resin member and a thermoplastic resin member to seal the sealed surface. A newly formed surface is formed at the surface boundary by removing a surface layer in the sealed surface. A functional group in the newly formed surface is chemically bound to a functional group in a functional group-containing additive added to a constituent material of the thermoplastic resin member.Type: ApplicationFiled: February 23, 2015Publication date: November 17, 2016Applicant: DENSO CORPORATIONInventors: Tomoyuki HARADA, Ryosuke IZUMI, Hiroyuki YAMAKAWA
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Publication number: 20160336200Abstract: A method of processing a substrate in semiconductor fabrication is provided. The method includes supplying a mixture to a process module. The method further includes detecting the concentration of a substance in the mixture. The method also includes dispensing the mixture over a substrate in the process module. In addition, the method includes supplying a supply solution including the substance to the process module and dispensing the supply solution over the substrate if the concentration of the substance in the mixture is less than a desired value.Type: ApplicationFiled: May 29, 2015Publication date: November 17, 2016Inventors: Chun-Syuan JHUAN, Ming-Jung CHEN, Shao-Yen KU, Tsai-Pao SU
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Publication number: 20160336201Abstract: A substrate processing apparatus is provided including: a liquid processing unit that processes a substrate with a processing liquid; a carry-in port formed in the liquid processing unit and configured to carry-in the substrate in a dry-state before the substrate is processed with the processing liquid; a carry-out port formed in the liquid processing unit and configured to carry-out the substrate in a wet-state after completing the liquid processing; a supercritical dry processing unit that performs a dry processing for the substrate using a supercritical fluid; a first substrate transport unit that transports the substrate in a dry-state before the substrate is processed with the processing liquid to the carry-out port of the liquid processing unit; and a second substrate transport unit that transports the substrate in a wet-state after completing the liquid processing from the carry-out port of the liquid processing unit to the supercritical dry processing unit.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Inventor: Hiroaki INADOMI
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Publication number: 20160336202Abstract: Disclosed is a substrate liquid processing apparatus that includes: a liquid processing unit that performs a liquid processing on a film formed on a surface of a substrate with an etching liquid; an etching liquid supply unit that supplies an etching liquid to the liquid processing unit; and a controller that controls the etching liquid supply unit. The controller is configured to perform a control such that an etching liquid in a state of having a relatively low etching rate for the film is supplied from the etching liquid supply unit to the liquid processing unit so that the substrate is etched in the liquid processing unit, and then, an etching liquid in a state of having a relatively high etching rate for the film is supplied from the etching liquid supply unit to the liquid processing unit so that the substrate is etched in the liquid processing unit.Type: ApplicationFiled: May 12, 2016Publication date: November 17, 2016Inventors: Hideaki Sato, Takashi Nagai, Hiromi Hara
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Publication number: 20160336203Abstract: A method and corresponding device for bonding a first contact surface of a first substrate to a second contact surface of a second substrate. The method includes the steps of arranging a substrate stack, formed from the first substrate and the second substrate and aligned on the contact surfaces, between a first heating surface of a first heating system and a second heating surface of a second heating system.Type: ApplicationFiled: February 3, 2014Publication date: November 17, 2016Applicant: EV GROUP E. THALLNER GMBHInventor: Friedrich Paul Lindner
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Publication number: 20160336204Abstract: A heater or cooler chamber for a batch of more than one workpiece includes a heat storage block. In the block a multitude of pockets are provided, whereby each of the pockets may be closed or opened by a controllably operated door. A heater or cooler arrangement is applied. The pockets are tailored to surround a workpiece applied therein in a non-contact closely spaced manner.Type: ApplicationFiled: December 10, 2015Publication date: November 17, 2016Inventor: Jurgen Weichart
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Publication number: 20160336205Abstract: The embodiments described herein generally relate to a lamphead assembly with an absorbing upper surface in a thermal processing chamber. In one embodiment, a processing chamber includes an upper structure, a lower structure, a base ring connecting the upper structure to the lower structure, a substrate support disposed between the upper structure and the lower structure, a lower structure disposed below the substrate support, a lamphead positioned proximate to the lower structure with one or more fixed lamphead positions formed therein, the lamphead comprising a first surface proximate the lower structure and a second surface opposite the first surface, wherein the first surface comprises an absorptive coating and one or more lamp assemblies each comprising a radiation generating source and positioned in connection with the one or more fixed lamphead positions.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventors: Paul BRILLHART, Joseph M. RANISH, Satheesh KUPPURAO, Balasubramanian RAMACHANDRAN, Zuoming ZHU
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Publication number: 20160336206Abstract: Systems, machines, and methods for monitoring wafer handling are disclosed herein. A system for monitoring wafer handling includes a sensor and a controller. The sensor is capable of being secured to an assembled wafer handling machine. The controller is in electronic communication with the sensor and includes control logic. The control logic is configured to store a reference output of the sensor when the wafer handling machine is aligned and is configured to generate an indication signal when a difference between the reference output and a current output of the sensor exceeds a threshold.Type: ApplicationFiled: July 29, 2016Publication date: November 17, 2016Inventors: Stephen B. Miner, William John Fosnight, Ryan J. Gallagher
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Publication number: 20160336207Abstract: Embodiments of methods and system for transferring semiconductor devices from a wafer to a carrier structure are described. In one embodiment, a method for transferring semiconductor devices from a wafer to a carrier structure involves positioning a carrier structure with a bond surface extending in a first plane and transferring a semiconductor device from a wafer onto the bond surface of the carrier structure using a plurality of rotatable transfer assemblies. Centers of the rotatable transfer assemblies are positioned in parallel with the first plane.Type: ApplicationFiled: May 12, 2015Publication date: November 17, 2016Applicant: NXP B.V.Inventor: Jozef Petrus Wilhelmus Stokkermans
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Publication number: 20160336208Abstract: An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device.Type: ApplicationFiled: May 10, 2016Publication date: November 17, 2016Inventors: Hale Johnson, Gregory George
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Publication number: 20160336209Abstract: A support member includes a first positioning portion for properly positioning a small container, and a second positioning portion for properly positioning a large container. The first positioning portion includes one or more first support members for supporting the small container, and first engaging members for engaging first engaged portions. The second positioning portion includes one or more second support members for supporting the large container at a height at which the bottom surface of the large container is located at a higher position than the upper ends of the first engaging members, a second engaging member provided outside the first supporting area for engaging a second engaged portion, and one or more contact members provided outside the first supporting area for contacting the large container from one or more sides.Type: ApplicationFiled: May 11, 2016Publication date: November 17, 2016Inventors: Hideo Yoshioka, Takafumi Yamazaki
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Publication number: 20160336210Abstract: An electrostatic chuck includes a ceramic structural element, at least one electrode disposed on the ceramic structural element, and a surface dielectric layer disposed over the at least one electrode, the surface layer activated by a voltage in the electrode to form an electric charge to electrostatically clamp a substrate to the electrostatic chuck. The surface dielectric layer comprises: (i) an insulator layer of amorphous alumina, of a thickness of less than about 5 microns, disposed over the at least one electrode; and (ii) a stack of dielectric layers disposed over the insulator layer. The stack of dielectric layers includes: (a) at least one dielectric layer including aluminum oxynitride; and (b) at least one dielectric layer including at least one of silicon oxide and silicon oxynitride.Type: ApplicationFiled: February 6, 2015Publication date: November 17, 2016Inventors: Richard A. Cooke, Wolfram Neff, Carlo Waldfried, Jakub Rybczynski, Michael Hanagan, Wade Krull
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Publication number: 20160336211Abstract: A bonding structure including a first substrate, a second substrate, and an adhesive layer is provided. The first substrate has a plurality of first trenches. The adhesive layer is located between the first substrate and the second substrate, and the first trenches are filled with the adhesive layer.Type: ApplicationFiled: September 22, 2015Publication date: November 17, 2016Inventors: Kuan-Wei Chen, Pei-Jer Tzeng, Chien-Chou Chen, Po-Chih Chang
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Publication number: 20160336212Abstract: An industrial-scale apparatus, system, and method for handling precisely aligned and centered semiconductor wafer pairs for wafer-to-wafer aligning and bonding applications includes an end effector having a frame member and a floating carrier connected to the frame member with a gap formed therebetween, wherein the floating carrier has a semi-circular interior perimeter. The centered semiconductor wafer pairs are positionable within a processing system using the end effector under robotic control. The centered semiconductor wafer pairs are bonded together without the presence of the end effector in the bonding device.Type: ApplicationFiled: May 10, 2016Publication date: November 17, 2016Inventors: Hale Johnson, Gregory George
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Publication number: 20160336213Abstract: A semiconductor substrate processing apparatus comprises a vacuum chamber in which a semiconductor substrate may be processed, a showerhead module through which process gas from a process gas source is supplied to a processing zone of the vacuum chamber, and a substrate pedestal module. The substrate pedestal module includes a platen, a stem having a side wall defining a cylindrical interior region thereof, a lower surface, and an upper end that supports the platen, and an adapter having a side wall defining a cylindrical interior region thereof and an upper surface that supports the stem. The lower surface of the stem includes a gas inlet in fluid communication with a respective gas passage located in the side wall of the stem and a gas outlet located in an annular gas channel in the upper surface of the adapter. The upper surface of the adapter includes an inner groove located radially inward of the gas outlet and an outer groove located radially outward of the inner groove.Type: ApplicationFiled: May 12, 2015Publication date: November 17, 2016Applicant: LAM RESEARCH CORPORATIONInventors: Troy Alan Gomm, Timothy Thomas
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Publication number: 20160336214Abstract: Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET), forming one or more electrical connections to the FET, forming one or more dielectric layers over at least a portion of the electrical connections, and disposing an electrical element at least partially above the one or more dielectric layers, the electrical element being in electrical communication with the FET via the one or more electrical connections. RF device fabrication further involves applying an interface material over at least a portion of the one or more dielectric layers, removing at least a portion of the interface material to form a trench above at least a portion of the electrical element, and covering at least a portion of the interface material and the trench with a substrate layer to form a cavity, the electrical element being disposed at least partially within the cavity.Type: ApplicationFiled: May 13, 2016Publication date: November 17, 2016Inventors: David T. PETZOLD, David Scott WHITEFIELD
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Publication number: 20160336215Abstract: A calibration method for determining temperature set point corrections to be applied to the nominal temperature set points of each of the N heating zones of a heat treatment unit having L substrate locations, includes the following steps: establishing a sensitivity model linking variations of a substrate characteristic at each of M representative locations of the L locations to temperature set point variations applied in each of the N heating zones, the variations respectively reflecting differences with respect to a target characteristic and with respect to the nominal set points; executing the process in the heat treatment unit and on the basis of nominal set points; measuring the substrate characteristic at least at a representative measurement location of each heating zone of the unit to supply M measurements; and determining temperature set point corrections from the sensitivity model, the measurements and the target substrate characteristic.Type: ApplicationFiled: May 12, 2016Publication date: November 17, 2016Inventors: Sebastien Mougel, Didier Masselin
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Publication number: 20160336216Abstract: The present disclosure relates a back-end-of-the-line (BEOL) metallization stack having an air gap disposed between adjacent metal interconnect features, which provides for an inter-level dielectric material with a low dielectric constant. In some embodiments, the BEOL metallization stack has an inter-level dielectric (ILD) layer disposed over a substrate. A metal interconnect layer is disposed within the ILD layer, and an air gap is arranged disposed within the ILD layer at a position between a first feature and a second feature of the metal interconnect layer. The air gap has an upper surface with a first curve that meets a second curve at a peak arranged below a top of the metal interconnect layer. The first curve becomes steeper as a distance from the peak decreases and the second curve becomes steeper as a distance from the peak decreases.Type: ApplicationFiled: July 29, 2016Publication date: November 17, 2016Inventors: Ru-Shang Hsiao, Chih-Fu Chang, Jen-Pan Wang
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Publication number: 20160336217Abstract: A method for manufacturing a shallow trench isolation (STI) region with a high aspect ratio is provided. A semiconductor substrate is provided with a trench. A first dielectric layer is formed lining the trench. A second dielectric layer is formed filling the trench over the first dielectric layer. In some embodiments, before forming the second dielectric layer, ions are implanted into an implant region of the first dielectric layer that extends along and is limited to a lower region of the trench. In alternative embodiments, after forming the second dielectric layer, an ultraviolet curing process is performed to the second dielectric layer. With the second dielectric layer formed and, in some embodiments, the ultraviolet curing process completed, an annealing process is performed to the second dielectric layer. A semiconductor structure for a STI region is also provided.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Inventors: Yao-Wen Chang, Chia-Shiung Tsai, Cheng-Yuan Tsai
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Publication number: 20160336218Abstract: A method for manufacturing a semiconductor device includes etching a semiconductor substrate to form a fin-shaped semiconductor layer. After forming the fin-shaped semiconductor layer, a first insulating film is deposited around the fin-shaped semiconductor layer. The first insulating film is etched back to expose an upper portion of the fin-shaped semiconductor layer and a second resist is formed so as to be perpendicular to the fin-shaped semiconductor layer. The fin-shaped semiconductor layer is etched to form a pillar-shaped semiconductor layer, such that a portion where the fin-shaped semiconductor layer and the second resist intersect at right angles defines the pillar-shaped semiconductor layer.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventors: Fujio MASUOKA, Hiroki NAKAMURA
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Publication number: 20160336219Abstract: Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Harry Gomez
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Publication number: 20160336220Abstract: A semiconductor device includes a substrate including a memory cell region and a contact region, a string structure including conductive layers and first interlayer insulating layers alternately stacked over the substrate and protruded toward a lower layer from the memory cell region toward the contact region, barrier rib patterns spaced apart from one another over the conductive layers in the contact region and configured to open the layers of the conductive layers in the contact region through the spaced spaces, and first contact plugs filled into the space between barrier rib patterns adjacent to each other and coupled to the conductive layers in the contact region.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Inventor: Yong Hyun LIM
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Publication number: 20160336221Abstract: An integrated circuit structure includes a first dielectric layer, an etch stop layer over the first dielectric layer, and a second dielectric layer over the etch stop layer. A via is disposed in the first dielectric layer and the etch stop layer. A metal line is disposed in the second dielectric layer, wherein the metal line is connected to the via. The etch stop layer includes a first portion having an edge contacting an edge of the via, wherein the first portion has a first chemical composition, and a second portion in contact with the first portion. The second portion is spaced apart from the via by the first portion, and wherein the second portion has a second chemical composition different from the first composition.Type: ApplicationFiled: July 29, 2016Publication date: November 17, 2016Inventor: Chih-Yuan Ting
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Publication number: 20160336222Abstract: Processing methods comprising exposing a substrate to a nucleation promoter followed by sequential exposure of a first reactive gas comprising a metal-containing compound and a second reactive gas to form a metal-containing film on the substrate.Type: ApplicationFiled: May 11, 2016Publication date: November 17, 2016Inventors: David Knapp, Jeffrey W. Anthis, Xinyu Fu, Srinivas Gandikota
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Publication number: 20160336223Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Inventors: Harold Ryan Chase, Mihir K. Roy, Mathew J. Manusharow, Mark Hlad
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Publication number: 20160336224Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming on a front surface of a silicon carbide substrate of a first conductivity type, a silicon carbide layer of the first conductivity type of a lower concentration; selectively forming a region of a second conductivity type in a surface portion of the silicon carbide layer; selectively forming a source region of the first conductivity type in the region; forming a source electrode electrically connected to the source region; forming a gate insulating film on a surface of the region between the silicon carbide layer and the source region; forming a gate electrode on the gate insulating film; forming a drain electrode on a rear surface of the substrate; forming metal wiring comprising aluminum for the device, the metal wiring being connected to the source electrode; and performing low temperature nitrogen annealing after the metal wiring is formed.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Applicants: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Yoshiyuki SUGAHARA, Takashi TSUTSUMI, Youichi MAKIFUCHI, Tsuyoshi ARAOKA, Kenji FUKUDA, Shinsuke HARADA, Mitsuo OKAMOTO
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Publication number: 20160336225Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventors: Shyng-Tsong Chen, Cheng Chi, Chi-Chun Liu, Sylvie M. Mignot, Yann A. Mignot, Hosadurga K. Shobha, Terry A. Spooner, Wenhui Wang, Yongan Xu
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Publication number: 20160336226Abstract: Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.Type: ApplicationFiled: May 11, 2016Publication date: November 17, 2016Inventors: Edward FUERGUT, Irmgard ESCHER-POEPPEL, Stephanie FASSL, Paul GANITZER, Gerhard POEPPEL, Werner SCHUSTEREDER, Harald WIEDENHOFER
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Publication number: 20160336227Abstract: A method of forming a contact structure is provided. A silicon-containing substrate is provided with a composite dielectric layer formed thereon. An opening penetrates through the composite dielectric layer and exposes a portion of the source/drain region. A titanium nitride layer is formed in the opening, and the titanium nitride layer is in contact with the exposed portion of the source/drain region. The titanium nitride layer is annealed, so that the bottom portion of the titanium nitride layer is partially transformed into a titanium silicide layer. A conductive layer is formed to fill up the opening.Type: ApplicationFiled: May 11, 2015Publication date: November 17, 2016Inventors: Pin-Hong Chen, Kuo-Chih Lai, Chia-Chang Hsu, Chun-Chieh Chiu, Li-Han Chen, Shu-Min Huang, Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu
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Publication number: 20160336228Abstract: Fabrication of radio-frequency (RF) devices involves providing a field-effect transistor (FET) formed over an oxide layer formed on a semiconductor substrate, removing at least part of the semiconductor substrate to expose at least a portion of a backside of the oxide layer, applying an interface material to at least a portion of the backside of the oxide layer, removing at least a portion of the interface material to form a trench, and covering at least a portion of the interface material and the trench with a substrate layer to form a cavity.Type: ApplicationFiled: May 13, 2016Publication date: November 17, 2016Inventors: David T. PETZOLD, David Scott WHITEFIELD
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Publication number: 20160336229Abstract: Various embodiments provide semiconductor structures and methods for forming the same. In an exemplary structure, a substrate has a device region, a seal ring region surrounding the device region, and a dielectric layer disposed thereon. A first seal ring structure is located within the dielectric layer on the seal ring region, and includes a plurality of first connection layers overlappingly disposed and separated by the dielectric layer. At least one first connection layer is formed by a plurality of discrete sub-connection layers. The first seal ring structure further includes a plurality of first conductive plugs between vertically adjacent first connection layers. A top of each first conductive plug is connected to an upper first connection layer. A bottom of each first conductive plug between at least two vertically adjacent first connection layers extends into the dielectric layer between horizontally adjacent sub-connection layers of a lower first connection layer.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventor: XIANJIE NING
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Publication number: 20160336230Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Applicant: STATS ChipPAC Pte. Ltd.Inventors: Pandi C. Marimuthu, Shuangwu Huang, Nathapong Suthiwongsunthorn
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Publication number: 20160336231Abstract: A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Shih Pei Chou, U-Ting Chen, Chia-Chieh Lin
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Publication number: 20160336232Abstract: A chip package structure and the manufacturing method thereof are provided. Firstly, a conductive frame including a bottom plate and a plurality of partition plates is provided. The bottom plate has a supporting surface and a bottom surface opposite thereto, and the partition plates protrude from the supporting surface to define a plurality of the accommodating regions. Subsequently, a plurality of chips is provided, and each of the chips is correspondingly accommodated in each of the accommodating regions with a back surface facing to the supporting surface. Thereafter, the conductive frame is cut to form a plurality of separated chip package structures.Type: ApplicationFiled: April 21, 2016Publication date: November 17, 2016Inventors: CHIH-CHENG HSIEH, HSIU-WEN HSU
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Publication number: 20160336233Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.Type: ApplicationFiled: December 14, 2015Publication date: November 17, 2016Inventors: Takao Yonehara, Virendra V. Rana, Sean M. Seutter, Mehrdad M. Moslehi, Subramanian Tamilmani
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Publication number: 20160336234Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The methods may include forming a fin, forming a first device isolating layer on a side of the fin, forming a second device isolating layer extending through the first device isolating layer, forming first and second gates traversing the fin and forming a third device isolating layer between the first and second gates. The first device isolating layer may include a first material and a lowermost surface at a first depth. The second device isolating layer may include a second material and a lowermost surface at a second depth greater than the first depth. The third device isolating layer may extend into the fin, may include a lowermost surface at a third depth less than the first depth and a third material different from the first and the second materials.Type: ApplicationFiled: March 4, 2016Publication date: November 17, 2016Inventors: Sung-Min KIM, Sunhom Steve PAAK, Heon-Jong SHIN, Dong-Ho CHA
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Publication number: 20160336235Abstract: A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a fist work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type.Type: ApplicationFiled: May 9, 2016Publication date: November 17, 2016Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
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Publication number: 20160336236Abstract: A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Inventors: Chia-Yu Chen, Zuoguang Liu, Miaomiao Wang, Tenko Yamashita
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Publication number: 20160336237Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Inventors: Tsung-Lin Lee, Chih Chieh Yeh, Feng Yuan, Hung-Li Chiang, Wei-Jen Lai
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Publication number: 20160336238Abstract: A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over a buried oxide layer of a silicon-on-insulator substrate; forming a trench in the buried oxide layer; forming a polysilicon layer over the semiconductor fins and in the trench, the polysilicon layer having a depression corresponding to a location of the trench; forming an insulating layer over the polysilicon layer, and performing a planarizing operation to remove the insulating layer except for a portion of the insulating layer formed in the depression, thereby defining a protective island; patterning the polysilicon layer to define both a dummy gate structure over the fins and the polysilicon resistor; and etching the polysilicon layer to remove the dummy gate structure, wherein the protective island prevents the polysilicon resistor from being removed.Type: ApplicationFiled: May 11, 2015Publication date: November 17, 2016Inventors: Veeraraghavan S. Basker, Huiming Bu, Tenko Yamashita
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Publication number: 20160336239Abstract: A method of forming a polysilicon resistor in replacement metal gate (RMG) processing of finFET devices includes forming a plurality of semiconductor fins over a buried oxide layer of a silicon-on-insulator substrate; forming a trench in the buried oxide layer; forming a polysilicon layer over the semiconductor fins and in the trench, the polysilicon layer having a depression corresponding to a location of the trench; forming an insulating layer over the polysilicon layer, and performing a planarizing operation to remove the insulating layer except for a portion of the insulating layer formed in the depression, thereby defining a protective island; patterning the polysilicon layer to define both a dummy gate structure over the fins and the polysilicon resistor; and etching the polysilicon layer to remove the dummy gate structure, wherein the protective island prevents the polysilicon resistor from being removed.Type: ApplicationFiled: March 3, 2016Publication date: November 17, 2016Inventors: Veeraraghavan S. Basker, Huiming Bu, Tenko Yamashita
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Publication number: 20160336240Abstract: The present disclosure provides in various aspects an alignment monitoring structure and method for monitoring the alignment between a target gate conductor and the corresponding target contact in a semiconductor device, for example, in a CMOS. In accordance with some illustrative embodiments herein, a structure with a plurality of gate conductors disposed over the substrate so as to define a row of parallel gate conductors and a plurality of first contacts is provided, wherein each of the first contacts is disposed between two adjacent gate conductors so as to define a first lateral distance between a first gate conductor and the first contact and a second lateral distance between the first contact and a second gate conductor, and wherein the first lateral distance and the second lateral distance vary systematically along the row of parallel gate conductors.Type: ApplicationFiled: May 12, 2015Publication date: November 17, 2016Inventor: Dominik Olligs
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Publication number: 20160336241Abstract: A method of automated optical inspection (AOI) for a plurality of unique semiconductor packages can comprise providing a plurality of semiconductor die formed as a reconstituted wafer. A plurality of unit specific patterns can be formed by forming a unit specific pattern over each of the plurality of semiconductor die, wherein each of the unit specific patterns is customized to fit its respective semiconductor die. A plurality of images can be acquired by acquiring an image for each of the plurality of unit specific patterns. A plurality of unique reference standards can be created by creating a unique reference standard for each of the plurality of unit specific patterns. Defects can be detected in the plurality of unit specific patterns by comparing one of the plurality of unique reference standards to a corresponding one of the plurality of images for each of the plurality of unit specific patterns.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Craig Bishop, Vaibhav Joga Singh Bora, Christopher M. Scanlan, Timothy L. Olson
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Publication number: 20160336242Abstract: A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 ? on a semiconductor substrate; forming a PMOS element having a channel length of less than 0.13 ?m on the semiconductor substrate; and assessing hot carrier injection (HCl) for the PMOS element.Type: ApplicationFiled: July 28, 2016Publication date: November 17, 2016Applicant: Magnachip Semiconductor, Ltd.Inventors: KyeNam LEE, HyunHo JANG
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Publication number: 20160336243Abstract: A method is provided for testing a semiconductor wafer, including individual semiconductor devices located on the semiconductor wafer, using temporary counterpart sacrificial bond pads. The method includes arranging individual semiconductor devices on the semiconductor wafer in a configuration having horizontal rows of the individual semiconductor devices separated by functional horizontal scribe lanes, and having vertical columns of individual semiconductor devices separated by functional vertical scribe lanes. The method includes creating the temporary counterpart sacrificial bond pads, located in the functional horizontal scribe lanes and/or vertical scribe lanes, that are electrically connected to corresponding normal individual bond pads located on individual semiconductor devices.Type: ApplicationFiled: December 24, 2014Publication date: November 17, 2016Applicant: CELERINT, LLCInventor: Howard ROBERTS, JR.
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Publication number: 20160336244Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Toshihiko Akiba, Bunji Yasumura, Masanao Sato, Hiromi Abe
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Publication number: 20160336245Abstract: A power semiconductor device includes: an outer case; at least one press-fit terminal buried in a top surface of the outer case; and a plurality of supporting portions formed so as to protrude from the top surface of the outer case. A top end of the press-fit terminal protrudes more than top surfaces of the supporting portions from the top surface of the outer case.Type: ApplicationFiled: May 3, 2016Publication date: November 17, 2016Applicant: Mitsubishi Electric CorporationInventors: Minoru EGUSA, Hidetoshi ISHIBASHI, Yoshitaka OTSUBO, Hiroyuki MASUMOTO, Hiroshi KAWATA
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Publication number: 20160336246Abstract: Provided is a semiconductor encapsulation resin composition exhibiting an insignificant heat decomposition when left under a high temperature of 200 to 250° C. for a long period of time; and a superior reliability and adhesion to a Cu LF and Ag plating under a high-temperature and high-humidity environment. The composition comprises: (A) a cyanate ester compound having not less than two cyanato groups in one molecule; (B) a phenolic compound; (C) at least one epoxy resin; (D) a copolymer obtained by a hydrosilylation reaction of an alkenyl group-containing epoxy compound and an organopolysiloxane; and (E) at least one compound selected from a tetraphenylborate salt of a tetra-substituted phosphonium compound and a tetraphenylborate salt. A molar ratio of phenolic hydroxyl groups in (B) to cyanato groups in (A) is 0.08 to 0.25, and a molar ratio of epoxy groups in (C) and (D) to cyanato groups in (A) is 0.04 to 0.25.Type: ApplicationFiled: April 20, 2016Publication date: November 17, 2016Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Shoichi OSADA, Naoyuki KUSHIHARA, Ryuhei YOKOTA
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Publication number: 20160336247Abstract: Apparatus, and methods of manufacture thereof, in which a molding compound is formed between spaced apart microelectronic devices. The molding compound comprises micro-filler elements. No boundary of any of the micro-filler elements is substantially parallel to a substantially planar surface of the molding compound, or to a substantially planar surface of any of the microelectronic devices.Type: ApplicationFiled: July 25, 2016Publication date: November 17, 2016Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng
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Publication number: 20160336248Abstract: The present application relates to a cured product and the use thereof. When the cured product, for example, is applied to a semiconductor device such as an LED or the like, the decrease in brightness may be minimized even upon the long-term use of the device, and since the cured product has excellent cracking resistance, the device having high long-term reliability may be provided. The cured product has excellent processability, workability, and adhesive properties or the like, and does not cause whitening and surface stickiness, etc. Further, the cured product exhibits excellent heat resistance at high temperature, gas barrier properties, etc. The cured product may be, for example, applied as an encapsulant or an adhesive material of a semiconductor device.Type: ApplicationFiled: January 28, 2015Publication date: November 17, 2016Applicant: LG CHEM, Ltd.Inventors: Min Jin KO, Kyung Mi KIM, Jae Ho JUNG, Bum Gyu CHOI, Min Kyoun KIM