Patents Issued in November 17, 2016
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Publication number: 20160336149Abstract: A method and apparatus for monitoring wear of a chamber component is disclosed herein. In one embodiment, a chamber component is provided. The chamber component includes a body including a first material, a second material disposed on the first material, the second material having an exposed surface defining an interior surface of the chamber component, and a wear surface disposed at a wear depth below the exposed surface of the second material, the wear surface comprising a third material having a composition that is different than a composition of the first material and the second material.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Inventors: Mats LARSSON, Wai-Fan YAU
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Publication number: 20160336150Abstract: In one embodiment, an RF generator includes an RF amplifier comprising an RF input, a DC input, and an RF output, the RF amplifier configured to receive at the RF input an RF signal from an RF source; receive at the DC input a DC voltage from a DC source; and provide an output power at the RF output; and a control unit operably coupled to the DC source and the RF source, the control unit configured to receive a power setpoint indicative of a desired output power at the RF output; determine a power dissipation at the RF generator; alter the DC voltage to decrease the power dissipation at the RF generator; and alter the RF signal to enable the output power at the RF output to be substantially equal to the power setpoint.Type: ApplicationFiled: July 29, 2016Publication date: November 17, 2016Inventors: Imran Ahmed Bhutta, Tomislav Lozic
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Publication number: 20160336151Abstract: An AC power connector for connecting an AC power supply with a device is provided. The AC power connector includes at least one first element connectable with the AC power supply and at least one second element connectable with the device, the first element and the second elements being arranged at a first distance with respect to each other for defining a capacitance, wherein the at least one first element and the at least one second element are rotatable with respect to each other, wherein the first element and the second element are configured for a transfer of an AC power between the at least one first element and the at least one second element.Type: ApplicationFiled: December 18, 2013Publication date: November 17, 2016Inventors: Frank SCHNAPPENBERGER, Anke HELLMICH, Stefan KELLER, Marcus BENDER
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Publication number: 20160336152Abstract: Systems and methods for adjusting power and frequency based on three or more states are described. One of the methods includes receiving a pulsed signal having multiple states. The pulsed signal is received by multiple radio frequency (RF) generators. When the pulsed signal having a first state is received, an RF signal having a pre-set power level is generated by a first RF generator and an RF signal having a pre-set power level is generated by a second RF generator. Moreover, when the pulsed signal having a second state is received, RF signals having pre-set power levels are generated by the first and second RF generators. Furthermore, when the pulsed signal having a third state is received, RF signals having pre-set power levels are generated by the first and second RF generators.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Inventors: John C. Valcore, JR., Bradford J. Lyndaker
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Publication number: 20160336153Abstract: The provision of blunt protrusions on a grounded screen of a plasma reactor in combination with a working gas diluted with a predominant quantity of an inert gas provides enhanced back corona discharge and greatly increased quantities of neutral radicals near and below the grounded screen of a plasma reactor vessel operated at near atmospheric pressure. Use of helium as the inert gas allow production of reactive species of oxygen, nitrogen or both.Type: ApplicationFiled: May 13, 2016Publication date: November 17, 2016Applicant: Washington State UniversityInventors: Patrick Dennis Pedrow, Rokibul Islam, Karl Richard Englund, Shuzheng Xie
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Publication number: 20160336154Abstract: According to an embodiment of the present invention, a plasma processing apparatus includes: a processing chamber in which plasma processing is performed to a sample; a radio frequency power source that supplies radio frequency power for generating plasma in the processing chamber; and a data processing apparatus that performs processing to light emission data of the plasma. The data processing apparatus performs the processing to the light emission by using an adaptive double exponential smoothing method for varying a smoothing parameter based on an error between input data and a predicted value of smoothed data. A response coefficient of the smoothing parameter is derived by a probability density function including the error as a parameter.Type: ApplicationFiled: March 1, 2016Publication date: November 17, 2016Inventors: Seiichi WATANABE, Satomi INOUE, Shigeru NAKAMOTO, Kousuke FUKUCHI
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Publication number: 20160336155Abstract: Methods for making a high purity (>99.99%) and low oxygen (<40 ppm) sputtering target containing Co, CoFe, CoNi, CoMn, CoFeX (X?B, C, Al), Fe, FeNi, or Ni alloys with a column microstructure framed by boron intermetallics are disclosed. The sputtering target is made by directional casting a molten mixture of the metal alloy, annealing to remove residual stresses, slicing, and optional annealing and finishing to obtain the sputtering target.Type: ApplicationFiled: May 13, 2016Publication date: November 17, 2016Inventors: Xingbo Yang, Dejan Stojakovic, Matthew J. Komertz, Arthur V. Testanero
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Publication number: 20160336156Abstract: There is provided a method of introducing ions into a mass spectrometer, comprising ionising a sample using a continuous ionisation source to form a plurality of ions, transporting said plurality of ions in a first, primary gas through a passageway and into an inlet of a mass spectrometer, introducing a second, auxiliary gas into said inlet, and controlling a flow rate of said second gas into said inlet so as to control a flow rate of said first gas through said passageway.Type: ApplicationFiled: May 16, 2016Publication date: November 17, 2016Inventor: Jeffery Mark Brown
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Publication number: 20160336157Abstract: There is provided a method of introducing ions into a mass spectrometer, comprising ionising a sample using a Matrix Assisted Laser Desorption Ionisation (“MALDI”) ion source to form a plurality of ions, transporting said plurality of ions in a first, primary gas through a passageway and into an inlet of a mass spectrometer, introducing a second, auxiliary gas into said inlet, and controlling a flow rate of said second gas into said inlet so as to control a flow rate of said first gas through said passageway.Type: ApplicationFiled: May 16, 2016Publication date: November 17, 2016Inventors: Jeffery Mark Brown, Rainer Cramer
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Publication number: 20160336158Abstract: Methods and systems for delivering a liquid sample to an ion source are provided herein: In various aspects, the methods and systems described herein can utilize the flow provided by an LC pump(s) to drive a calibration fluid to an ion source of a mass spectrometer system. In various aspects, methods and systems described herein can additionally or alternatively be placed upstream of an LC column for providing an elution gradient of a plurality of solvents, without requiring a plurality of pumps and/or separate mixing elements.Type: ApplicationFiled: November 18, 2014Publication date: November 17, 2016Inventor: Peter Kovarik
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Publication number: 20160336159Abstract: Ion filter for FAIMS fabricated using the LIGA technique. The ion filter is manufactured using a metal layer to form the ion channels and an insulating support layer to hold the structure rigidly together after separation of the metal layer into two electrodes.Type: ApplicationFiled: May 11, 2016Publication date: November 17, 2016Applicant: Owlstone LimitedInventors: Danielle Toutoungi, Matthew Hart, John Somerville, Jon Pearson, Max Allsworth, Richard Orrell, Antoni Negri, Jeremy Spinks, Martin Holden, Andrew H. Koehl, Alastair Taylor
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Publication number: 20160336160Abstract: Methods and systems for transmitting ions in an ion guide are provided herein. In accordance with various aspects of the applicant's teachings, the methods and systems can cause at least a portion of ions entrained in a gas flow entering an ion guide to be extracted from the gas jet and be guided downstream along one or more path of gas flow, where the gas lacking the ions can be removed from the ion guide. In some embodiments, the ions extracted from the gas stream can be guided into a focusing region in which the ions can be focused, e.g., via RF focusing, to enter into subsequence processing stages, such as a mass analyzer.Type: ApplicationFiled: November 18, 2014Publication date: November 17, 2016Inventor: Takashi Baba
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Publication number: 20160336161Abstract: Systems and methods are provided for time-of-flight analysis of a continuous beam of ions by a detector array. A sample is ionized using an ion source to produce a continuous beam of ions. An electric field is applied to the continuous beam of ions using an accelerator to produce an accelerated beam of ions. A rotating magnetic and/or electric field is applied to the accelerated beam to separate ions with different mass-to-charge ratios over an area of a two-dimensional detector using a deflector located between the accelerator and the two-dimensional detector. An arrival time and a two-dimensional arrival position of each ion of the accelerated beam are recorded using the two-dimensional detector. Alternatively, an electric field that is periodic with time is applied in order to sweep the accelerated beam over a periodically repeating path on the two-dimensional rectangular detector.Type: ApplicationFiled: December 6, 2014Publication date: November 17, 2016Inventor: Robert Alois Grothe, JR.
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Publication number: 20160336162Abstract: A technique for time interval measurement is provided. First and second signal components are received, sampled and digitized. The first signal component is derived from a trigger signal that causes or indicates generation 5 of the second signal component. A time interval between the first and second signal components is determined based on a reference time defined by the sampled and digitized first signal component and based on a reference time defined by the sampled and digitized second signal component.Type: ApplicationFiled: May 10, 2016Publication date: November 17, 2016Inventors: Matthias BIEL, Richard HEMING, Anastassios GIANNAKOPULOS
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Publication number: 20160336163Abstract: A mass spectrometer includes a radio frequency ion trap; and a controller. The controller is configured to cause an ion population to be injected into the radio frequency ion trap; supply a first isolation waveform to the radio frequency ion trap for a first duration, and supply a second isolation waveform to the radio frequency ion trap for a second duration. The first isolation waveform has at least a first wide notch at a first mass-to-charge ratio, and the second isolation waveform has at least a first narrow notch at the first mass-to-charge ratio. The first and second isolation waveforms are effective to isolate one or more precursor ions from the ion population.Type: ApplicationFiled: May 11, 2015Publication date: November 17, 2016Inventors: Philip M. REMES, Michael W. SENKO, Jae C. SCHWARTZ
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Publication number: 20160336164Abstract: A mass spectrometer includes a radio frequency ion trap and a controller. The controller is configured to cause an ion population to be injected into the radio frequency ion trap and supply an isolation waveform to the radio frequency ion trap. The isolation waveform has at least one notch at a target mass-to-charge ratio and a frequency profile determined to eject unwanted ions at a plurality of frequencies in a substantially similar amount of time.Type: ApplicationFiled: May 11, 2015Publication date: November 17, 2016Inventors: Philip M. REMES, Jae C. SCHWARTZ
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Publication number: 20160336165Abstract: Systems and methods are provided for performing multiplex electrostatic linear ion trap mass spectrometry. A first beam of ions is received and the first beam is split into N beams of ions using a beam splitter. N is two or more. Ions are received from only one of the N beams of ions at each entrance aperture of N entrance apertures of an electrostatic linear ion trap (ELIT). Ions from each entrance aperture of the N entrance apertures are trapped in separate linear flight paths using the ELIT, producing N seperate linear flight paths. Ion oscillations in the N separate linear flight paths are measured at substantially the same time using the ELIT. The ELIT uses two concentric mirrors with N apertures to trap ions in the N separate linear flight paths. The ELIT uses an image current detector with N apertures to the measure the ion oscillations.Type: ApplicationFiled: December 6, 2014Publication date: November 17, 2016Inventor: Mircea GUNA
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Publication number: 20160336166Abstract: The present invention relates to a method for determining at least one parameter related to charged particles emitted from a particle emitting sample, e.g. a parameter related to the energies, the start directions, the start positions or the spin of the particles. The method comprises the steps of guiding a beam of charged particles into an entrance of a measurement region by means of a lens system, and detecting positions of the particles indicative of said at least one parameter within the measurement region. Furthermore, the method comprises the steps of deflecting the particle beam at least twice in the same coordinate direction before entrance of the particle beam into the measurement region. Thereby, both the position and the direction of the particle beam at the entrance of the measurement region can be controlled in a way that to some extent eliminates the need for physical manipulation of the sample.Type: ApplicationFiled: July 27, 2016Publication date: November 17, 2016Applicant: SCIENTA OMICRON ABInventor: Björn WANNBERG
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Publication number: 20160336167Abstract: An ignition facilitated electrodeless sealed high intensity illumination device is disclosed. The device is configured to receive a laser beam from a continuous wave (CW) laser light source. A sealed chamber is configured to contain an ionizable medium. The chamber has an ingress window disposed within a wall of a chamber interior surface configured to admit the laser beam into the chamber, a plasma sustaining region, and a high intensity light egress window configured to emit high intensity light from the chamber. A path of the CW laser beam from the laser light source through the ingress window to a focal region within the chamber is direct. The ingress window is configured to focus the laser beam to within a predetermined volume, and the plasma is configured to be ignited by the CW laser beam, optionally by heating of a non-electrode ignition agent located entirely within the chamber.Type: ApplicationFiled: May 14, 2015Publication date: November 17, 2016Inventor: Rudi Blondia
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Publication number: 20160336168Abstract: A sealed high intensity illumination device configured to receive a laser beam from a laser light source and method for making the same are disclosed. The device includes a sealed cylindrical chamber configured to contain an ionizable medium. The chamber has a cylindrical wall, with an ingress and an egress window disposed opposite the ingress window. A tube insert is disposed within the chamber formed of an insulating material. The insert is configured to receive the laser beam within the insert inner diameter.Type: ApplicationFiled: March 14, 2016Publication date: November 17, 2016Inventor: Rudi Blondia
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Publication number: 20160336169Abstract: A large number of pattern elements stands upright on an upper surface of a substrate. After the upper surface of the substrate has been processed using a processing liquid, liquid filling processing for filling the upper surface with a filler solution is performed, in which the filler solution having a viscosity of three centipoises or more is applied to a central part of the upper surface. Then, by rotating the substrate at 1000 revolutions per minute or less, the processing solution adhering to the entire upper surface is replaced by the filler solution, and a solution layer of a predetermined thickness is formed. In this way, making the viscosity of the filler solution relatively high and making the centrifugal force acting at the time of rotating the substrate relatively low suppresses deformation of the pattern elements at the time of filling with a filler that uses the filler solution.Type: ApplicationFiled: May 6, 2016Publication date: November 17, 2016Inventors: Naozumi FUJIWARA, Naoko YAMAGUCHI
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Publication number: 20160336170Abstract: Disclosed is a substrate processing apparatus. The substrate processing apparatus includes a first nozzle that ejects droplets of a chemical liquid toward a front surface of a substrate, the droplets being formed by mixing a gas supplied by a gas supply mechanism and a heated chemical liquid supplied by a heated chemical liquid supply mechanism with each other, and a second nozzle that ejects the heated deionized water supplied by the heated deionized water supply mechanism toward the rear surface of the substrate. The first nozzle supplies the droplets to the front surface of the substrate heated from the rear surface thereof by the heated deionized water supplied from the second nozzle.Type: ApplicationFiled: May 9, 2016Publication date: November 17, 2016Inventors: Seiki Ishida, Shogo Fukui, Hidetaka Shinohara
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Publication number: 20160336171Abstract: Disclosed herein is a method of: depositing a patterned mask layer on an N-polar GaN epitaxial layer of a sapphire, silicon, or silicon carbide substrate; depositing an AlN inversion layer on the open areas; removing any remaining mask; and depositing a III-N epitaxial layer to simultaneously produce N-polar material and III-polar material. Also disclosed herein is: depositing an AlN inversion layer on an N-polar bulk III-N substrate and depositing a III-N epitaxial layer to produce III-polar material. Also disclosed herein is: depositing an inversion layer on a III-polar bulk III-N substrate and depositing a III-N epitaxial layer to produce N-polar material. Also disclosed herein is a composition having: a bulk III-N substrate; an inversion layer on portions of the substrate; and a III-N epitaxial layer on the inversion layer. The III-N epitaxial layer is of the opposite polarity of the surface of the substrate.Type: ApplicationFiled: May 20, 2016Publication date: November 17, 2016Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Jennifer K. Hite, Francis J. Kub, Charles R. Eddy, JR., Nelson Garces
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Publication number: 20160336172Abstract: Lithography stack, intermediate semiconductor devices, and methods of fabrication are provided. The method includes obtaining an intermediate semiconductor device with a substrate, applying a spin on carbon layer over the substrate, and applying a hardmask layer over the spin on carbon layer. The intermediate semiconductor device includes a substrate, a spin on carbon layer over the substrate, and a hardmask layer over the spin on carbon layer. The lithography stack includes a spin on carbon layer, an invisible hardmask layer over the spin on carbon layer, and a photoresist layer over the invisible hardmask layer.Type: ApplicationFiled: May 14, 2015Publication date: November 17, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Linus JANG, Sanggil BAE, Daeyoup LEE
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Publication number: 20160336173Abstract: The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.Type: ApplicationFiled: April 25, 2016Publication date: November 17, 2016Inventor: Takuya HAGIWARA
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Publication number: 20160336174Abstract: A silicon and oxygen-containing film, such as a silicon dioxide film, is deposited in the absence of an oxidizer by introducing siloxane precursors into a plasma processing chamber and dissociating at least some of the Si—H bonds of the siloxane precursors by, for example, exposing the siloxane precursors to a low energy plasma. The silicon and oxygen-containing film may be formed on an oxidation-prone surface without oxidizing the oxidation-prone surface. The deposited silicon and oxygen-containing film may serve as an initiation layer for a silicon dioxide bulk layer that is formed on top of the initiation layer using conventional silicon oxide deposition techniques, such as exposing the siloxane precursors to an oxygen-containing plasma. The initiation layer may be post-treated or cured to reduce the concentration of Si—H bonds prior to or after the deposition of the bulk layer.Type: ApplicationFiled: January 5, 2015Publication date: November 17, 2016Applicant: Applied Materials, Inc.Inventors: Brian Saxton UNDERWOOD, Abhijit Basu MALLICK
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Publication number: 20160336175Abstract: Disclosed is a method for forming an oxide thin film on a solid substrate, the method including the steps of placing a solid substrate s a in a reaction container 1, maintaining the solid substrate at a temperature of higher than 0° C. and 150° C. or lower, and filling the reaction container with an organometallic gas containing tetrakis(ethylmethylamino)hafnium or tetrakis(ethylmethylamino)zirconium; discharging the organometallic gas from the reaction container or filling the reaction container with an inert gas; treating a gas containing oxygen and water vapor with plasma, to thereby generate a plasma gas containing excited oxygen and water vapor, and feeding the plasma gas into the reaction container; and discharging the plasma gas from the reaction container or filling the reaction container with an inert gas; and repeating the series of steps.Type: ApplicationFiled: December 11, 2014Publication date: November 17, 2016Inventors: Fumihiko HIROSE, Kensaku KANOMATA
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Publication number: 20160336176Abstract: A dense array of semiconductor single crystalline semiconductor nanocrystals is provided in the present application by forming an amorphous semiconductor material layer surrounding a plurality of patterned nanostructures comprised of a single crystalline semiconductor material portion. A thermal anneal, i.e., (solid phase epitaxy), is then performed to crystallize a portion of the amorphous semiconductor material layer that is in contact with each single crystalline semiconductor material portion and to provide a plurality of spaced apart single crystalline nanocrystals on a surface of an insulator. A remaining portion of the amorphous semiconductor material layer that was not crystallized is thereafter removed.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Inventors: Kangguo Cheng, Hong He, Juntao Li
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Publication number: 20160336177Abstract: A method of manufacturing a semiconductor device may include: forming an opening in an insulating layer to expose a portion of a major surface of a substrate, the substrate comprising a first semiconductor material; forming a protrusion in the opening using a first epitaxial growth process, the protrusion comprising a first portion disposed in the opening and a second portion extending out of the opening, the protrusion comprising a second semiconductor material different from the first semiconductor material; and forming the second semiconductor material on sidewalls of the second portion of the protrusion using a second epitaxial growth process different from the first epitaxial growth process.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Inventors: Martin Christopher Holland, Georgios Vellianitis
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Publication number: 20160336178Abstract: Methods and apparatus for depositing nanolaminate films are provided. In various embodiments, the nanolaminate film may be deposited over a core layer, which may be patterned. The nanolaminate film may act as a spacer while performing a double or quadruple patterning process. The nanolaminate film may include at least two different types of film. In some cases, the two different types of film have different compositions. In some cases, the two different types of film may be deposited under different deposition conditions, and may or may not have the same composition. After the nanolaminate film is deposited, the substrate may be etched to expose the core layer. Some portions of the nanolaminate film (e.g., portions that form on sidewalls of features patterned in the core layer) may remain after etching, and may serve as a mask during later processing steps in a double or quadruple patterning process.Type: ApplicationFiled: July 29, 2016Publication date: November 17, 2016Inventors: Shankar Swaminathan, Frank L. Pasquale, Adrien LaVoie
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Publication number: 20160336179Abstract: An electroless plating process is performed on an Al layer, which is made of aluminum or an aluminum alloy, with an electroless plating liquid which is alkaline and contains a complexing agent. A plating method includes preparing a substrate 10 having a surface (for example, bottom surface of TSV 12) at which an Al layer 22 made of aluminum or an aluminum alloy is exposed; forming a zincate film 30 on a surface of the Al layer by performing a zincate treatment on the substrate; and forming a first electroless plating layer (for example, Co barrier layer 14a) on the surface of the Al layer with an electroless plating liquid (for example, Co-based plating liquid) which is alkaline and contains a complexing agent.Type: ApplicationFiled: May 10, 2016Publication date: November 17, 2016Inventors: Nobutaka Mizutani, Mitsuaki Iwashita, Takashi Tanaka
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Publication number: 20160336180Abstract: A method for etching a gate includes forming a high-k material layer over a substrate; forming an overlying layer over the high-k material layer; performing a first etching process for etching the overlying layer to form an overlying layer pattern; forming a spacer on a sidewall of the overlying layer pattern; and performing a second etching process using plasma including a etch gas and an additive gas, to etch the high-k material layer, wherein an amount of the additive gas is substantially the same as the main etch gas to increase an etch selectivity with respect to the substrate.Type: ApplicationFiled: July 26, 2016Publication date: November 17, 2016Inventors: Su-Bum SHIN, Hae-Jung LEE
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Publication number: 20160336181Abstract: The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S1) providing a substrate having a metal gate structure on a side of the substrate, (S2) forming a titanium nitride (TiN) layer on the side of the substrate, and (S3) performing a gate annealing to tune work function of the metal gate structure.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventors: KUO-CHIH LAI, YANG-JU LU, CHING-YUN CHANG, YEN-CHEN CHEN, SHIH-MIN CHOU, YUN TZU CHANG, FANG-YI LIU, HSIANG-CHIEH YEN, NIEN-TING HO
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Publication number: 20160336182Abstract: A method of forming a NAND flash memory includes anisotropically etching trenches of a gate stack down to an intermediate level in a floating gate polysilicon layer, leaving remaining portions of the floating gate polysilicon over the gate dielectric layer. Subsequently, forming a protective layer along exposed sides of the trenches. Then, electrically separating individual floating gates by a selective process that is directed to the remaining portions of the floating gate polysilicon layer exposed by trenches.Type: ApplicationFiled: May 14, 2015Publication date: November 17, 2016Inventors: Toshiya Yokota, Atsushi Shimoda, Takuya Sakurai
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Publication number: 20160336183Abstract: At least one method, apparatus and system disclosed herein for processing a semiconductor wafer using a continuous active area design for manufacturing a finFET device. A first gate structure of a continuous active area design is formed in a first layer of the wafer. A first hard mask layer is deposited. A portion of the first hard mask layer is removed based upon a first trench silicide (TS) pattern and a second TS pattern. A full stripe first trench silicide (TS) structure and a second TS structure are formed. A first TS capping layer is deposited above the first TS structure and a second TS capping. The first TS capping layer is removed and a source/drain contact structure (CA) is formed above the first TS structure in a second layer of the semiconductor wafer. A gate contact structure (CB) is formed above the gate structure in the second layer.Type: ApplicationFiled: May 14, 2015Publication date: November 17, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Lei Yuan, Jongwook Kye, Mahbub Rashed
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Publication number: 20160336184Abstract: An electronic device can include one or more trenches that include a material that defines one or more voids. In an embodiment, the substrate defines a first trench having a first portion and a second portion laterally adjacent to the first portion, wherein the first portion has with a first width, the second portion has a second width, and the first width is wider than the second width. The material defines a first void at a predetermined location within the first portion of the first trench and has a seam within the second portion of the first trench. In another embodiment, the substrate defining a trench, and the material that defines spaced-apart voids at predetermined locations within the trench. A process of forming the electronic device can include patterning a substrate to define a trench, and depositing a material within the trench, wherein the deposited material defines a void.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Gordon M. Grivna, Michael Thomason, Stevan Gaurdello Hunter
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Publication number: 20160336185Abstract: A plasma processing apparatus includes a plasma processing chamber processing a sample using plasma, a radio frequency power supply supplying radio frequency power for generating the plasma, a sample stage including an electrode electrostatically chucking the sample, mounting the sample thereon, a DC power supply applying DC voltage to the electrode, and a control device shifting the DC voltage previously set, in a negative direction by a first shift amount during discharge of the plasma, shifting the DC voltage having been shifted in the negative direction by the first shift amount, in a positive direction by a second shift amount after the discharge of the plasma. The first shift amount has a value changing potential over a surface of the sample to 0 V, upon shifting the DC voltage in the positive direction. The second shift amount has a value obtained based on a floating potential of the plasma.Type: ApplicationFiled: March 1, 2016Publication date: November 17, 2016Inventors: Masaki ISHIGURO, Masahiro SUMIYA, Shigeru SHIRAYONE, Kazuyuki IKENAGA, Tomoyuki TAMURA
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Publication number: 20160336186Abstract: Disclosed is a method of forming a target pattern for a semiconductor device using multiple directed self-assembly (DSA) patterning processes. The method includes receiving a substrate and forming a guide pattern over the substrate by performing a process that includes a first DSA process. The method further includes performing a second DSA process over the substrate using the guide pattern. In an embodiment, the first DSA process controls the first pitch of a dense pattern in a first direction and the second DSA process controls the second pitch of the dense pattern in a second direction.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Inventors: Chin-Yuan Tseng, Chi-Cheng Hung, Chun-Kuang Chen, Kuan-Hsin Lo, Ru-Gun Liu, Tsai-Sheng Gau, Wei-Liang Lin
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Publication number: 20160336187Abstract: A method of forming a semiconductor structure includes following steps. First of all, a plurality of mandrels is formed on a target layer. Next, a plurality of first liner is formed adjacent to two sides of the mandrels. Then, a plurality of second liners is formed adjacent to two sides of the first liners. After these, a plurality of third liners is formed adjacent to two sides of the second liners. Finally, the mandrels and the second liners are simultaneously removed.Type: ApplicationFiled: June 12, 2015Publication date: November 17, 2016Inventors: En-Chiuan Liou, Yu-Cheng Tung
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Publication number: 20160336188Abstract: The present invention is a semi conductor-wafer cleaning tank in which semiconductor wafers are immersed in a cleaning solution and cleaned, including a tank body, composed of quartz, for storing the cleaning solution to immerse the semiconductor wafers in the cleaning solution, an overflow-receiving part, composed of quarts and provided around an opening of the tank body, for receiving the cleaning solution overflowing from an upper end of the opening of the tank body, and a heat-insulating wall-provided around the tank body, in which the heat-insulating wall forms an unbroken enclosure around the tank body with a hollow layer formed between the heat-insulating wall and a side wall of the tank body. As a result, there is provided a cleaning tank for use in an etching step that allows bonded wafers keeping film-thickness uniformity even after the etching step for adjusting the film thickness to be manufactured in high yield.Type: ApplicationFiled: January 13, 2015Publication date: November 17, 2016Applicant: Shin-Etsu Handotai Co., Ltd.Inventor: Yasuo NAGAOKA
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Publication number: 20160336189Abstract: An organic film composition including a compound represented by the following general formula (1), wherein n1 and n2 each independently represent 0 or 1; “W” represents a single bond or any of structures represented by the following formula (2); R1 represents any of structures represented by the following general formula (3); m1 and m2 each independently represent an integer of 0 to 7, with the proviso that m1+m2 is 1 to 14. There can be provided an organic film composition for forming an organic film having dry etching resistance as well as advanced filling/planarizing characteristics.Type: ApplicationFiled: April 5, 2016Publication date: November 17, 2016Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventors: Daisuke KORI, Kazumi NODA, Kazunori MAEDA, Rie KIKUCHI, Tsutomu OGIHARA
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Publication number: 20160336190Abstract: Provided is a method for forming a low dielectric constant film on a substrate placed in a processing chamber inside a processing container. The method includes: generating plasma using microwaves by supplying at least a noble gas to a plasma generation chamber, which is formed above the processing chamber inside the processing container; forming a low dielectric constant film on the substrate by supplying particles from the plasma generation chamber to the processing chamber and supplying a precursor gas to the processing chamber through a shield unit provided between the plasma generation chamber and the processing chamber, the shield unit having a plurality of openings configured to communicate the plasma generation chamber with the processing chamber, and having a shielding property against ultraviolet light; and then, performing a heat treatment on the substrate.Type: ApplicationFiled: January 14, 2015Publication date: November 17, 2016Applicants: TOKYO ELECTRON LIMITED, TOHOKU TECHNO ARCH CO., LTD.Inventors: Yoshiyuki KIKUCHI, Yasuaki SAKAKIBARA, Seiji SAMUKAWA
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Publication number: 20160336191Abstract: The etching method of one embodiment includes a first step of generating a plasma of a first processing gas containing a fluorocarbon gas and a hydrofluorocarbon gas in a processing container of a plasma processing apparatus, and a second step of generating a plasma of a second processing gas containing a hydrofluorocarbon gas and a nitrogen gas in the processing container. In the method, sequences each including the first step and the second step are performed. The plasma is continuously generated over the execution period for the first step and the execution period for the second step. In the second step, a ratio of the flow rate of a hydrogen gas to the flow rate of the second processing gas is set to be small in a period immediately before the execution period for the first step and a period immediately after the execution period for the first step.Type: ApplicationFiled: May 10, 2016Publication date: November 17, 2016Applicant: TOKYO ELECTRON LIMITEDInventors: Yusuke SAITOH, Hironobu ICHIKAWA, Isao TAFUSA
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Publication number: 20160336192Abstract: A method of forming a pattern including forming a feature layer on a substrate having first and second regions; forming a first guide pattern on the first region, the first guide pattern having openings therein, the openings exposing the feature layer; forming a second guide pattern covering the feature layer exposed through the first guide pattern on the first region and covering the second region; forming a block copolymer layer covering the first guide pattern and the second guide pattern on the first and second regions; phase-separating the block copolymer layer to form first vertical domains and a second vertical domain; removing the first vertical domains on the first region; and etching the first guide pattern and the feature layer using the second vertical domain as an etch mask on the first region to form a feature pattern having holes therein.Type: ApplicationFiled: March 29, 2016Publication date: November 17, 2016Inventor: Seok-han PARK
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Publication number: 20160336193Abstract: A method of forming a pattern, the method including forming a mask layer on a feature layer on a substrate; forming guides regularly arranged with a first pitch on the mask layer in a first region and dummy guides regularly arranged with the first pitch on the mask layer in a second region spaced apart from the first region with a separation region therebetween, the separation region having a width greater than the first pitch; forming a block copolymer layer on the mask layer; phase-separating the block copolymer layer to form a self-assembled layer; forming a mask pattern by etching the mask layer using the self-assembled layer; and patterning the feature layer by transferring a shape of the mask pattern to the feature layer in the first region while blocking the shape of the mask pattern from being transferred to the feature layer in the second region.Type: ApplicationFiled: May 11, 2016Publication date: November 17, 2016Inventor: Seok-han PARK
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Publication number: 20160336194Abstract: A method of forming a semiconductor device includes following steps. First of all, a first work function layer is formed on a substrate. Next, a first patterned photoresist layer is formed on the first work function layer. Then, the first work function layer is partially removed by using the first patterned photoresist layer as a mask to form a patterned first work function layer. Subsequently, the first patterned photoresist layer is removed by providing radical oxygen.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventors: Chiu-Hsien Yeh, Zhen Wu, Yen-Cheng Chang, Yu-Ting Tseng
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Publication number: 20160336195Abstract: A plurality of flash lamps that irradiate a semiconductor wafer with flash light are arrayed in a plane. The array of the plurality of flash lamps is divided into two zones: a central zone including a region opposed to a central portion of the semiconductor wafer to be treated, and a peripheral zone outside the central zone. During flash light irradiation, an emission time of a flash lamp belonging to the peripheral zone is set to be longer than an emission time of a flash lamp belonging to the central zone. Thus, a greater amount of flash light is applied to the peripheral portion of the semiconductor wafer, where a temperature drop is relatively likely to occur, than to the central portion thereof, thus preventing a relative temperature drop in the peripheral portion of the semiconductor wafer during flash heating.Type: ApplicationFiled: May 5, 2016Publication date: November 17, 2016Inventor: Kazuhiko FUSE
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Publication number: 20160336196Abstract: A wafer processing apparatus includes a particle charger for charging particles adsorbed onto a wafer with photoelectrons emitted from an emitter metal layer and a particle remover for applying an electric field to the wafer, which removes the charged particles from the wafer.Type: ApplicationFiled: October 29, 2015Publication date: November 17, 2016Inventors: Jae Hee SIM, Si Hyun KIM
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Publication number: 20160336197Abstract: A method according to an embodiment includes (i) a step of preparing a workpiece in a processing container of a plasma processing apparatus, (ii) a first plasma processing step of generating a plasma of a first processing gas, which contains chlorine, in the processing container, (iii) a second plasma processing step of generating a plasma of a second processing gas, which contains fluorine, in the processing container, and (iv) a third plasma processing step of generating a plasma of a third processing gas, which contains oxygen, in the processing container. A plurality of sequences, each of which includes the first plasma processing step, the second plasma processing step, and the third plasma processing step, are performed.Type: ApplicationFiled: May 9, 2016Publication date: November 17, 2016Applicant: TOKYO ELECTRON LIMITEDInventors: Fumiya KOBAYASHI, Masahiro OGASAWARA
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Publication number: 20160336198Abstract: This invention relates generally to ID frequency identification (RFID) transponders and receivers. More specifically to the methods, apparatus and systems of the fabrication of the transponders and receivers. In one example embodiment, to methods, apparatus, and systems to form effective barriers for devices having a layer structure, including encapsulating at least a portion of the side of the devices from being degraded due to impurity penetration into a laminate structure of the devices, which can cause corrosion or malfunction of the devices.Type: ApplicationFiled: May 11, 2016Publication date: November 17, 2016Inventors: Laurence Singleton, Ray Freeman