Patents Issued in January 3, 2017
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Patent number: 9537024Abstract: An optoelectronic device has a hybrid metal-dielectric optoelectronic interface including an array of nanoscale dielectric resonant elements (e.g., nanopillars), and a metal film disposed between the dielectric resonant elements and below a top surface of the resonant elements such that the dielectric resonant elements protrude through the metal film. The device may also include an anti-reflection coating. The device may further include a metal film layer on each of the dielectric resonant elements.Type: GrantFiled: April 29, 2016Date of Patent: January 3, 2017Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Vijay K. Narasimhan, Thomas M. Hymel, Ruby A. Lai, Yi Cui
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Patent number: 9537025Abstract: Embodiments generally relate to optoelectronic devices and more specifically, to textured layers in optoelectronic devices. In one embodiment, a method for providing a textured layer in an optoelectronic device includes depositing a first layer of a first material and depositing an island layer of a second material on the first layer. Depositing the island layer includes forming one or more islands of the second material to provide at least one textured surface of the island layer, where the textured surface is operative to cause scattering of light.Type: GrantFiled: April 24, 2015Date of Patent: January 3, 2017Assignee: ALTA DEVICES, INC.Inventors: Brendan M. Kayes, Gregg S. Higashi, Frank Reinhardt, Sylvia Spruytte
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Patent number: 9537026Abstract: A method for manufacturing a solar-power-generator substrate by cutting out a semiconductor substrate by slicing a semiconductor ingot and then by forming a texture structure on a surface of the semiconductor substrate by performing a surface treatment on the surface of the semiconductor substrate, includes: cleaning including cleaning and removing an organic impurity and a metal impurity adhering to the surface of the semiconductor substrate with a cleaning fluid containing an oxidizing chemical; and etching including removing a damaged layer on a substrate surface generated by the slicing and forming the texture structure on the surface of the semiconductor substrate by performing anisotropic etching on the surface of the semiconductor substrate with an alkaline aqueous solution, the etching being performed subsequent to the cleaning.Type: GrantFiled: June 12, 2014Date of Patent: January 3, 2017Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Hajime Tsugeno, Mitsuhiro Nonogaki, Junji Kobayashi, Yusuke Oshiro, Takahiro Kawasaki, Shoichi Karakida
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Patent number: 9537027Abstract: The invention relates to quantum dot and photodetector technology, and more particularly, to quantum dot infrared photodetectors (QDIPs) and focal plane array. The invention further relates to devices and methods for the enhancement of the photocurrent of quantum dot infrared photodetectors in focal plane arrays.Type: GrantFiled: March 27, 2014Date of Patent: January 3, 2017Assignee: University of MassachusettsInventors: Xuejun Lu, Guiru Gu, Puminun Vasinajindakaw
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Patent number: 9537028Abstract: Described herein is a pinned photodiode pixel architecture having a p-type substrate that is independently biased with respect to a pixel area to provide an avalanche region between an n-type region and a p-type region formed on the substrate. Such a pinned photodiode pixel can be used in imaging sensors that are used in low light level conditions.Type: GrantFiled: June 19, 2014Date of Patent: January 3, 2017Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU Leuven R&DInventors: Koen De Munck, Tomislav Resetar
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Patent number: 9537029Abstract: A semiconductor device includes a first semiconductor layer including a recess region and protrusions defined by the recessed region, first insulating patterns provided on the protrusions and extending to sidewalls of the protrusions, and a second semiconductor layer to fill the recess region and cover the first insulating patterns. The protrusions includes a first group of protrusions spaced apart from each other in a first direction to constitute a row and a second group of protrusions spaced from the first group of protrusions in a second direction intersecting the first direction and spaced from each other in the first direction to constitute a row. The second group of protrusions are shifted from the first group of protrusions in the first direction.Type: GrantFiled: December 24, 2014Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTDInventors: Beom Seok Kim, Bongjin Kuh, Jongsung Lim, Hanmei Choi
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Patent number: 9537030Abstract: Methods of fabricating solar cells with tunnel dielectric layers are described. Solar cells with tunnel dielectric layers are also described.Type: GrantFiled: May 29, 2015Date of Patent: January 3, 2017Assignee: SunPower CorporationInventors: Tim Dennis, Scott Harrington, Jane Manning, David D. Smith, Ann Waldhauer
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Patent number: 9537031Abstract: A method for fabricating a solar cell using a nozzle assembly that includes a base portion, a scriber coupled to the base portion, and a nozzle coupled to the base portion such that the nozzle is positioned a predefined distance from a tip of the scriber is provided. The method generally comprises positioning a substructure that includes a buffer layer and an absorber layer proximate to the base portion. A P2 line is scribed through the buffer and absorber layers of the substructure using the scriber tip. A nanoparticle solution is sprayed, using the nozzle, onto at least one portion of the buffer layer at a predefined pressure when the P2 line is being scribed through the buffer and absorber layers such that a transparent conductive oxide (TCO) layer is inhibited from forming over the portion of the buffer layer that is being sprayed with the nanoparticle solution.Type: GrantFiled: June 28, 2013Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Shih-Wei Chen
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Patent number: 9537032Abstract: One embodiment of the present invention provides a double-sided heterojunction solar cell module. The solar cell includes a frontside glass cover, a backside glass cover situated below the frontside glass cover, and a number of solar cells situated between the frontside glass cover and the backside glass cover. Each solar cell includes a semiconductor multilayer structure situated below the frontside glass cover, including: a frontside electrode grid, a first layer of heavily doped amorphous Si (a-Si) situated below the frontside electrode, a layer of lightly doped crystalline-Si (c-Si) situated below the first layer of heavily doped a-Si, and a layer of heavily doped c-Si situated below the lightly doped c-Si layer. The solar cell also includes a second layer of heavily doped a-Si situated below the multilayer structure; and a backside electrode situated below the second layer of heavily doped a-Si.Type: GrantFiled: June 2, 2009Date of Patent: January 3, 2017Assignee: SolarCity CorporationInventors: Jiunn Benjamin Heng, Chentao Yu, Zheng Xu, Jianming Fu, Peijun Ding
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Patent number: 9537033Abstract: The present invention is premised upon a system and method for an improved photovoltaic cladding device array with an interface member (500) for use on a building structure with other non-solar cladding materials (600). The interface member is disposed under a portion of the photovoltaic cladding elements (P) and includes a photovoltaic cladding element nesting portion and a building sheatin nesting portion.Type: GrantFiled: July 27, 2012Date of Patent: January 3, 2017Assignee: DOW GLOBAL TECHNOLOGIES LLCInventors: Joseph A Langmaid, James R Kennihan, Leonardo C Lopez
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Patent number: 9537034Abstract: The invention is to facilitate the attachment of an installation system in the production of a solar module. This is achieved via a process which comprises the following steps: a) mutual superposition of the layers that the structure of the solar module requires, where at least one heat-activatable double-sided adhesive tape is placed on the external side of the reverse-side layer and at least one retention plate is placed on said adhesive tape; b) mutual lamination of the layers mutually superposed in step a), at least with exposure to heat.Type: GrantFiled: August 13, 2013Date of Patent: January 3, 2017Assignee: TESA SEInventors: Michael Schwertfeger, Andreas Stein
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Patent number: 9537035Abstract: A back-face protection sheet for a solar cell module exhibits excellent adhesion strength and tensile strength even under a high-temperature and high-humidity environment, by using a plastic film that has excellent characteristics such as electrical insulation characteristic, heat resistance, dimension stability, mechanical strength, weatherability, and water resistance, and using a two-part type lamination adhesive having excellent weatherability. The back-face protection sheet is made to have excellent adhesion strength and tensile strength for a long period of time, even under a high-temperature and high-humidity environment, by improving weatherability (hydrolysis resistance) as base material films, and giving weatherability (hydrolysis resistance) to the two-part type lamination adhesive to be used in pasting together the base material films.Type: GrantFiled: May 18, 2015Date of Patent: January 3, 2017Assignee: Toray Advanced Film Co., Ltd.Inventors: Futoshi Okuyama, Kouhei Katou, Yuuka Ashida, Masahiro Mikawa, Masayoshi Teranishi
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Patent number: 9537036Abstract: Interconnects for optoelectronic devices are described. For example, an interconnect for an optoelectronic device includes an interconnect body having an inner surface, an outer surface, a first end, and a second end. A plurality of bond pads is coupled to the inner surface of the interconnect body, between the first and second ends. A stress relief feature is disposed in the interconnect body. The stress relief feature includes a slot disposed entirely within the interconnect body without extending through to the inner surface, without extending through to the outer surface, without extending through to the first end, and without extending through to the second end of the interconnect body.Type: GrantFiled: June 13, 2014Date of Patent: January 3, 2017Assignee: SunPower CorporationInventors: Ryan Linderman, Keith Johnston, Thomas Phu, Matthew Dawson
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Patent number: 9537037Abstract: A wet etching method for an N-type bifacial cell including: (1) providing an N-type silicon wafer, proceeding with surface structuralization on the N-type silicon wafer, and producing a PN junction on a surface of the N-type silicon wafer by using a boron diffusion technique; (2) proceeding with a first mixed acid washing, etching the PN junction on an edge and a back surface of the N-type silicon wafer; (3) proceeding with a first pure water washing and a first alkaline washing, removing residual acid solution from the surface of the N-type silicon wafer; (4) proceeding with a second pure water washing and a second mixed acid washing, removing residual impurities from the surface of the N-type silicon wafer; (5) proceeding with a third pure water washing and air drying; and (6) after air drying, completing etching on the N-type bifacial cell.Type: GrantFiled: May 14, 2015Date of Patent: January 3, 2017Assignee: Shanghai Shenzhou New Energy Development Co., Ltd.Inventors: Fei Zheng, Zhongwei Zhang, Lei Shi, Zhongli Ruan, Chen Zhao, Yuxue Zhao
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Patent number: 9537038Abstract: A method for forming a photovoltaic device includes depositing a p-type layer on a substrate. A barrier layer is formed on the p-type layer by exposing the p-type layer to an oxidizing agent. An intrinsic layer is formed on the barrier layer, and an n-type layer is formed on the intrinsic layer.Type: GrantFiled: November 13, 2015Date of Patent: January 3, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, BAY ZU PRECISION CO., LTDInventors: Tze-Chiang Chen, Augustin J. Hong, Chien-Chih Huang, Yu-Wei Huang, Jeehwan Kim, Devendra K. Sadana, Chih-Fu Tseng
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Patent number: 9537039Abstract: A photovoltaic cell can include a dopant in contact with a semiconductor layer. The photovoltaic cell can include a transparent conductive layer and a first semiconductor layer in contact with the transparent conductive layer, the first semiconductor layer including magnesium. In certain circumstances, a substrate can be a glass substrate. In other circumstances, a substrate can be a metal layer. The first semiconductor layer can include CdS. The first semiconductor layer can have a thickness of between about 200 or 3000 Angstroms. The first semiconductor layer can include 1-20% magnesium. A method of manufacturing a photovoltaic cell can include providing a transparent conductive layer and depositing a first semiconductor layer in contact with the transparent conductive layer, the first semiconductor layer treated with magnesium.Type: GrantFiled: November 26, 2012Date of Patent: January 3, 2017Assignee: First Solar, Inc.Inventors: Akhlesh Gupta, Ricky C. Powell, David Eaglesham
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Patent number: 9537040Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate having a pixel region and a periphery region defined thereon is provided, and at least a transistor is formed in the pixel region. A blocking layer is formed on the substrate, and the blocking layer includes a first opening exposing a portion of the substrate in the pixel region and a second opening exposing a portion of the transistor. A first conductive body is formed in the first opening and a second conductive body is formed in the second opening, respectively. The first conductive body protrudes from the substrate and the second conductive body protrudes from the transistor. A portion of the blocking layer is removed. A first salicide layer is formed on the first conductive body and a second salicide layer is formed on the second conductive body, respectively.Type: GrantFiled: May 9, 2013Date of Patent: January 3, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventor: Ching-Hung Kao
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Patent number: 9537041Abstract: A system and method of patterning dopants of opposite polarity to form a solar cell is described. Two dopant films are deposited on a substrate. A laser is used to pattern the N-type dopant, by mixing the two dopant films into a single film with an exposure to the laser and/or drive the N-type dopant into the substrate to form an N-type emitter. A thermal process drives the P-type dopant from the P-type dopant film to form P-type emitters and further drives the N-type dopant from the single film to either form or further drive the N-type emitter.Type: GrantFiled: June 27, 2014Date of Patent: January 3, 2017Assignee: SunPower CorporationInventors: Paul Loscutoff, Gabriel Harley
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Patent number: 9537042Abstract: A method for processing a transparent substrate includes generating at least one laser pulse having laser parameters selected for non-ablatively changing a conductive layer disposed on the transparent substrate into a non-conductive feature, and directing the pulse to said conductive layer. A protective film may be affixed to a surface of the transparent substrate and need not be removed during the processing of the substrate. After processing, processed areas can be visually indistinguishable from unprocessed areas.Type: GrantFiled: September 18, 2013Date of Patent: January 3, 2017Assignee: nLIGHT, Inc.Inventors: Adam Dittli, Robert J. Martinsen, Ken Gross
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Patent number: 9537043Abstract: It is an object to reduce the region of a photoelectric conversion element which light does not reach, to suppress deterioration of power generation efficiency, and to suppress manufacturing cost of a voltage conversion element. The present invention relates to a transmissive photoelectric conversion device which includes a photoelectric conversion element including an n-type semiconductor layer, an intrinsic semiconductor layer, and a p-type semiconductor layer; a voltage conversion element which is overlapped with the photoelectric conversion element and which includes an oxide semiconductor film for a channel formation region; and a conductive element which electrically connects the photoelectric conversion element and the voltage conversion element. The photoelectric conversion element is a solar cell. The voltage conversion element includes a transistor having a channel formation region including an oxide semiconductor film. The voltage conversion element is a DC-DC converter.Type: GrantFiled: April 15, 2011Date of Patent: January 3, 2017Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Hajime Kimura, Yoshiaki Ito, Takuro Ohmaru
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Patent number: 9537044Abstract: A method for manufacturing an optoelectric device comprising a semiconductor substrate, pads on a surface of the substrate; semiconductor elements, each element being in contact with a pad; and a dielectric region extending in the substrate from the surface and connecting, for each pair of pads, one of the pads in the pair to the other pad in the pair, the method successively comprising the forming of the pads and the forming of the region, wherein the region is formed by nitriding of the substrate, the method comprising the successive steps of: depositing a layer on the substrate; forming portions on the layer; etching the parts of the layer which are not covered with the portions to form the pads; removing the portions; and nitriding the pads and the parts of the substrate which are not covered with the pads, wherein the nitriding step successively comprises: a first step of nitriding of the pads at a first temperature; and a second step of nitriding of the parts of the substrate which are not covered withType: GrantFiled: October 23, 2013Date of Patent: January 3, 2017Assignees: ALEDIA, Commissariat A L'Energie Atomique Et Aux EnergiesInventors: Philippe Gilet, Xavier Hugon, David Vaufrey, Hubert Bono, Bérangère Hyot
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Patent number: 9537045Abstract: A method of fabricating a semiconductor device includes forming an insulation pattern including a mask region and an open region on a gallium nitride substrate, growing gallium nitride semiconductor layers to cover the insulation pattern, and patterning the semiconductor layers to form a plurality of semiconductor stacks separated from each other, the plurality of semiconductor stacks being electrically isolated from the gallium nitride substrate by the insulation pattern.Type: GrantFiled: July 10, 2015Date of Patent: January 3, 2017Assignee: Seoul Viosys Co., Ltd.Inventors: Jeong Hun Heo, Yeo Jin Yoon, Joo Won Choi, Joon Hee Lee, Chang Yeon Kim, Su Young Lee
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Patent number: 9537046Abstract: In an optical device wafer processing method, a light emitting layer on the front side of a wafer is removed by applying a pulsed laser beam to the wafer along division lines from the back side of a substrate with the focal point of the beam set near the light emitting layer, thereby partially removing the light emitting layer along the division lines. A shield tunnel is formed by applying the beam to the wafer along the division lines from the back of the substrate with the focal point of the beam set near the front of the substrate. This forms a plurality of shield tunnels arranged along each division line, each shield tunnel extending from the front side of the substrate to the back side thereof. Each shield tunnel has a fine hole and an amorphous region formed around the fine hole for shielding the fine hole.Type: GrantFiled: August 6, 2014Date of Patent: January 3, 2017Assignee: Disco CorporationInventors: Noboru Takeda, Hiroshi Morikazu
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Patent number: 9537047Abstract: A method for fabricating an LED/phosphor structure is described where an array of blue light emitting diode (LED) dies are mounted on a submount wafer. A phosphor powder is mixed with an organic polymer binder, such as an acrylate or nitrocellulose. The liquid or paste mixture is then deposited over the LED dies or other substrate as a substantially uniform layer. The organic binder is then removed by being burned away in air, or being subject to an O2 plasma process, or dissolved, leaving a porous layer of phosphor grains sintered together. The porous phosphor layer is impregnated with a sol-gel (e.g., a sol-gel of TEOS or MTMS) or liquid glass (e.g., sodium silicate or potassium silicate), also known as water glass, which saturates the porous structure. The structure is then heated to cure the inorganic glass binder, leaving a robust glass binder that resists yellowing, among other desirable properties.Type: GrantFiled: April 18, 2016Date of Patent: January 3, 2017Assignee: Koninklijke Philips N.V.Inventors: Grigoriy Basin, Stein Kuiper, Paul Scott Martin
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Patent number: 9537048Abstract: The present invention discloses a vertical AC LED element and fabrication method thereof, wherein the vertical AC LED element comprises a conductive substrate (102); a light-emitting module on the conductive substrate (102), including two horizontally arranged in parallel and mutually-isolated LEDs; wherein the first and second LEDs include a first semiconductor layer (111), a light-emitting layer (112) and a second semiconductor layer (113) from top down; a first insulating layer (131) is arranged between the second semiconductor layer (113) of the first LED and the conductive substrate (102) for mutual isolation; an ohmic contact is formed between the second semiconductor layer (113) of the second LED and the conductive substrate (102); a first conductive structure that connects the first semiconductor layer (111) of the first LED, the second semiconductor layer (113) of the second LED and the conductive substrate (102); and a second conductive structure that connects the second semiconductor layer (113) ofType: GrantFiled: March 21, 2013Date of Patent: January 3, 2017Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Shunping Chen, Xiaoqiang Zeng, Shaohua Huang, Qunfeng Pan, Jyh-Chiarng Wu
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Patent number: 9537049Abstract: There is provided a nanostructure semiconductor light emitting device may including: a base layer formed of a first conductivity-type semiconductor, an insulating layer formed on an upper surface of the base layer and including a first region having a plurality of openings and a plurality of second regions positioned in the plurality of openings and spaced apart from the first region, dielectric nanocores disposed in the plurality of second regions, and a plurality of light emitting nanostructures each including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially disposed on the dielectric nanocores.Type: GrantFiled: November 2, 2015Date of Patent: January 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventor: Kyung Wook Hwang
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Patent number: 9537050Abstract: The invention relates to an optoelectronic device and to the method for manufacturing same. The optoelectronic device (45), according to the invention includes, in particular: a semiconductor substrate (46) doped with a first type of conductivity; semiconductor contact pads (18) or a semiconductor layer on a surface (16) of the substrate which are/is respectively doped with a second type of conductivity that is the opposite of the first type; and semiconductor elements (24), each semiconductor element being in contact with a contact pad or with the layer.Type: GrantFiled: May 13, 2014Date of Patent: January 3, 2017Assignees: Commissariat a l'energie atomique et aux energies alternatives, AlediaInventors: Philippe Gilet, Alexei Tchelnokov, Ivan Christophe Robin
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Patent number: 9537051Abstract: A nanostructure semiconductor light emitting device may include a base layer having first and second regions and formed of a first conductivity-type semiconductor material; a plurality of light emitting nanostructures disposed on the base layer, each of which including a nanocore formed of a first conductivity-type semiconductor material, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on the nanocore; a contact electrode disposed on the light emitting nanostructures to be connected to the second conductivity-type semiconductor layer; a first electrode connected to the base layer; and a second electrode covering a portion of the contact electrode disposed on at least one of light emitting nanostructures disposed in the second region among the plurality of light emitting nanostructures, wherein light emitting nanostructures disposed in the second region and light emitting nanostructures disposed in the first region among the plurality of light emitting nanostructureType: GrantFiled: August 28, 2015Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam Goo Cha, Jin Bock Lee, Dong Kuk Lee, Dong Hyun Cho, Min Wook Choi
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Patent number: 9537052Abstract: Provided according to embodiments of the invention are method of coating a phosphor that include contacting the phosphor with a sol comprising at least one of silica, alumina, borate and a precursor thereof, to form a coating on the phosphor; and heating the phosphor. Also provided are phosphors that are coated with alumina, silica and/or borate, and light emitting devices that include such phosphors.Type: GrantFiled: April 7, 2014Date of Patent: January 3, 2017Assignee: Cree, Inc.Inventors: Harry A. Seibel, II, Brian Thomas Collins
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Patent number: 9537053Abstract: Provided is a high quality III nitride semiconductor device in which, not only X-shaped cracks extending from the vicinity of the corners of semiconductor structures to the center portion thereof, but also crack spots at the center portion can be prevented from being formed and can provide a method of efficiently manufacturing the III nitride semiconductor device. The III nitride semiconductor device of the present invention includes a support and two semiconductor structures having a nearly quadrangular transverse cross-sectional shape that are provided on the support. The two semiconductor structures are situated such that one side surface of one of the two semiconductor structures is placed to face one side surface of the other of them. The support covers the other three side surfaces and of the four sides of the semiconductor structures.Type: GrantFiled: September 28, 2012Date of Patent: January 3, 2017Assignees: BBSA LIMITED, DOWA ELECTRONICS MATERIALS CO., LTD.Inventors: Meoung Whan Cho, Seog Woo Lee, Ryuichi Toba, Yoshitaka Kadowaki
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Patent number: 9537054Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.Type: GrantFiled: April 15, 2015Date of Patent: January 3, 2017Assignee: Sensor Electronic Technology, Inc.Inventors: Daniel D. Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
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Patent number: 9537055Abstract: A semiconductor LED package includes a package body having first and second electrode structures and an LED chip connected to at least one of the first and second electrode structures using a wire. The LED chip includes a light emitting structure and first and second electrode parts. At least one of the first and second electrode parts includes a bonding electrode layer made of a material having the same composition as a material of the wire and bonded to the wire, and an uneven electrode layer disposed on the bonding electrode layer and having at least one through hole filled with the wire. The at least one through hole allows a top surface of the bonding electrode layer to be exposed therebelow.Type: GrantFiled: September 18, 2014Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Myoung Bo Park, Kyung Seok Oh, Ho Young Song
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Patent number: 9537056Abstract: Provided is a light emitting device. In one embodiment, a light emitting device including: a support member; a light emitting structure on the support member, the light emitting structure comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a protective member at a peripheral region of an upper surface of the support member; an electrode including an upper portion being on the first conductive type semiconductor layer, a side portion extended from the upper portion and being on a side surface of the light emitting structure, and an extended portion extended from the side portion and being on the protective member; and an insulation layer between the side surface of the light emitting structure and the electrode.Type: GrantFiled: April 10, 2014Date of Patent: January 3, 2017Assignee: LG INNOTEK CO., LTD.Inventors: Jung Hyeok Bae, Young Kyu Jeong, Kyung Wook Park, Duk Hyun Park
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Patent number: 9537057Abstract: A surface-mounted light-emitting device includes: a LED epitaxial structure having two opposite surfaces, wherein the first surface is a light-emitting surface; P and N electrode pads over the second surface of the epitaxial structure, which have sufficient thickness to support the LED epitaxial structure, and the P and N electrode pads have two opposite surfaces respectively, in which, the first surface is approximate to the LED epitaxial structure; an insulator between the P and N pads to prevent the P and N electrode pads from short circuit; and the P and N electrode pads are directly applied in the SMT package. Some embodiments allow structural changes compared with conventional SMT package type by directly mounting the chip over the supporting substrate through an electrode pad. In addition, soldering is followed after the chip process without package step, which is mainly applicable to flip-chip LED device.Type: GrantFiled: June 24, 2015Date of Patent: January 3, 2017Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Shaohua Huang, Xiaoqiang Zeng, Chih-Wei Chao
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Patent number: 9537058Abstract: The present invention discloses an embedded white light LED package structure based on a solid-state fluorescence material. In the present invention, the high power blue light chip is directly embedded into and bonded with a groove of the solid-state fluorescence material, and blue light emitted by the chip and yellow and green light obtained by conversion and emitted by the solid-state fluorescence material are blended by using the principle of lenses, to obtain white light. The embedded white light LED package structure based on a solid-state fluorescence material has a simple process, low cost, and high fluorescence efficiency; and blue light does not leak. Heat dissipation can be directly performed by using the solid-state fluorescence material, and heat dissipation performance is desirable. Energy conservation and environmental protection is achieved, and a service life of an LED lighting device is greatly improved.Type: GrantFiled: June 5, 2014Date of Patent: January 3, 2017Assignee: SHANGHAI FUDI LIGHTING ELECTRONIC CO., LTD.Inventors: Yueshan Liang, Dunhua Cao, Kejun Ma
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Patent number: 9537059Abstract: The invention provides a luminescent nano particles based luminescent material comprising a matrix of interconnected coated luminescent nano particles, wherein for instance wherein the luminescent nano particles comprise CdSe, wherein the luminescent nano particles comprise a coating of CdS and wherein the matrix comprises a coating comprising ZnS. The luminescent material according may have a quantum efficiency of at least 80% at 25° C., and having a quench of quantum efficiency of at maximum 20% at 100° C. compared to the quantum efficiency at 25° C.Type: GrantFiled: May 24, 2016Date of Patent: January 3, 2017Assignee: Koninklijke Philips N.V.Inventors: Shu Xu, Rifat Ata Mustafa Hikmet
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Patent number: 9537060Abstract: A semiconductor light emitting device package includes: a light emitting device; a wavelength conversion unit formed in a path of light emitted from the light emitting device and including a mixture of a wavelength conversion material and a glass material; and a reflective film disposed on an upper surface of the wavelength conversion unit and reflecting a partial amount of light emitted from the light emitting device and allowing a partial amount of light emitted from the light emitting device to be transmitted therethrough.Type: GrantFiled: January 14, 2014Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang Bun Yoon, Sang Hyun Kim, Min Jung Park, Jeong Rok Oh, Chul Soo Yoon
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Patent number: 9537061Abstract: A phosphor composition is disclosed. A phosphor composition, comprises at least 10 atomic % bromine; silicon, germanium or combination thereof; oxygen; a metal M, wherein M comprises zinc (Zn), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), or combinations thereof; and an activator comprising europium. The phosphor composition is formed from combining carbonate or oxides of metal M, silicon oxide, and europium oxide; and then firing the combination. A lighting apparatus including the phosphor composition is also provided. The phosphor composition may be combined with an additional phosphor to generate white light.Type: GrantFiled: December 12, 2014Date of Patent: January 3, 2017Assignee: General Electric CompanyInventors: Alok Mani Srivastava, Holly Ann Comanzo, William Winder Beers, Samuel Joseph Camardello, Fangming Du, William Erwin Cohen
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Patent number: 9537062Abstract: A solid state light emitter package (200), a light emitting device, a flexible LED strip and a luminaire are provided. The solid state light emitter package comprising: i) at least three solid state light emitter dies (132, 142, 152) which emit violet/blue light, red light and further light, respectively, ii) a luminescent converter (120) with luminescent material, iii) an optical element (102, 105) for mixing at least portion of the light of the different colors of light and iv) a light exit window (114). The luminescent material at least partially converts the further light towards greenish light having a peak wavelength in the green or cyan spectral range and has a color emission distribution that is wide enough such that the solid state light emitter package is capable of emitting light with a high enough Color Rendering Index. The Color Rendering Index relates to light that has a color point close to the black body line.Type: GrantFiled: December 11, 2014Date of Patent: January 3, 2017Assignee: PHILIPS LIGHTING HOLDING B.V.Inventors: Joris Hubertus Antonius Hagelaar, Grigory Alexandrovich Onushkin, Marcellus Jacobus Johannes Van Der Lubbe, René Theodorus Wegh, Rémy Cyrille Broersma
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Patent number: 9537063Abstract: A method for producing a plurality of optoelectronic components (100) comprises the steps: providing a semiconductor body (101) that is arranged on a carrier (114); and applying a converter material (105) to the semiconductor body (101) by means of a photoconductive transfer element (120).Type: GrantFiled: July 9, 2013Date of Patent: January 3, 2017Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Siegfried Herrmann, Wolfgang Moench
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Patent number: 9537064Abstract: Disclosed is a method for producing a wavelength conversion element (10) wherein a wavelength conversion layer (100) is provided, the surface thereof is treated with a plasma (50), and the wavelength conversion layer is punched. Also disclosed are a wavelength conversion layer and an optoelectronic component comprising a wavelength conversion layer.Type: GrantFiled: May 6, 2014Date of Patent: January 3, 2017Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Britta Goeoetz, Martin Brandl, Markus Burger, Norwin Von Malm
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Patent number: 9537065Abstract: Improves light extraction efficiency. A light emitting device 1 using a white resin molding package 5 integrally molded with lead frames 3, 4 constituting an electrode corresponding to one or a plurality of light emitting element 2 and white resin, wherein an area in a plane view of a white resin surface on a reflective surface that is level with amounting surface of the light emitting element 2 is configured to be larger than total area in a plane view occupied by surfaces of the lead frames 3, 4 and the light emitting element. Further, a step section is formed on the surfaces of lead frames 3, 4, white resin is filled in the step section, and the area of white resin surface on a reflective surface where the light emitting element 2 is mounted is increased.Type: GrantFiled: May 31, 2012Date of Patent: January 3, 2017Assignee: Sharp Kabushiki KaishaInventors: Yoshiki Sota, Masayuki Ohta, Kazuo Tamaki, Shinji Yamaguchi, Shin Itoh, Tomoshi Kimura, Masaki Tatsumi
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Method of manufacturing semiconductor light emitting device, and semiconductor light emitting device
Patent number: 9537066Abstract: When an uneven pattern is formed on a light extraction surface composed of a semiconductor crystal by wet-etching using an alkaline solution, a plurality of convex portions cannot be formed in a desired arrangement. A method of manufacturing a semiconductor light emitting device includes a light extraction surface composed of a semiconductor crystal, wherein when the uneven pattern is formed by a plurality of convex portions on the light extraction surface, first, a plurality of impressions are formed on the light extraction surface of a semiconductor layer composed of a semiconductor crystal using a processing substrate, and next, by applying wet-etching to the light extraction surface using an alkaline solution, to thereby form convex portions with a portion where each impression is formed as a top portion, and a plurality of facets of the semiconductor crystal as a side face thereof.Type: GrantFiled: July 30, 2014Date of Patent: January 3, 2017Assignee: DOWA ELECTRONICS MATERIALS CO., LTD.Inventor: Yoshitaka Kadowaki -
Patent number: 9537067Abstract: An embodiment of the present invention relates to a radiation emitting device comprising: a radiation emitter for generating radiation; a waveguide; a lens placed between the radiation emitter and the waveguide and directing a first portion of the radiation towards the waveguide; a sleeve that comprises a reflective inner surface and is placed between the radiation emitter and the waveguide, said inner reflective surface coupling a second portion of the radiation into the waveguide; wherein the lens and the sleeve are separate components that can be positioned relative to each other during fabrication of the radiation emitting device.Type: GrantFiled: May 3, 2012Date of Patent: January 3, 2017Assignee: Technische Universität BerlinInventors: Christoph Brosche, Daniel Brüggemann
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Patent number: 9537068Abstract: A light emitting device package includes a substrate, a light emitting device disposed on the substrate, a reflector surrounding the light emitting device, and an encapsulant encapsulating the light emitting device. The reflector includes a silicon-based polymer which is a main body portion, and a silicon oxide layer disposed at least on a portion of a surface of the silicon-based polymer.Type: GrantFiled: December 19, 2013Date of Patent: January 3, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-kwan Yang, Jin-mo Kim, Kyu-jin Lee, Hyung-jin An
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Patent number: 9537069Abstract: An inorganic light-emitting diode structure includes a transparent substrate and an inorganic semiconductor having a conduction layer and a light-emitting layer over and in contact with only a portion of the conduction layer. A first metal contact is in electrical contact with the conduction layer and a second metal contact is in electrical contact with a second contact portion of the light-emitting layer so that a current supplied between the first metal contact and the second metal contact through the inorganic semiconductor causes the light-emitting layer to emit light. A dielectric layer is located over at least a portion of the light-emitting layer and a reflective layer is located over at least a portion of the dielectric layer. The reflective layer encapsulates the light-emitting layer exclusive of the portion of the conduction layer in contact with the light-emitting layer.Type: GrantFiled: June 30, 2015Date of Patent: January 3, 2017Assignee: X-Celeprint LimitedInventors: Christopher Bower, Matthew Meitl
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Patent number: 9537070Abstract: An optoelectronic component contains a semiconductor chip (1) and a carrier body (10), which are provided with a transparent, electrically insulating encapsulation layer (3), the encapsulation layer (3) having two cutouts (11, 12) for uncovering a contact area (6) and a connection region (8) of the carrier body, and an electrically conductive layer (14) being led from the contact area (6) over a partial region of the encapsulation layer (3) to the electrical connection region (8) of the carrier body (10) in order to electrically connect the contact area (6) and the electrical connection region (8) to one another. The radiation emitted in a main radiation direction (13) by the semiconductor chip (1) is coupled out through the encapsulation layer (3), which advantageously contains luminescence conversion substances for the wavelength conversion of the emitted radiation.Type: GrantFiled: September 13, 2005Date of Patent: January 3, 2017Assignee: OSRAM Opto Semiconductors GmbHInventors: Ewald Karl Michael Guenther, Jörg Erich Sorg, Norbert Stath
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Patent number: 9537071Abstract: A method of manufacturing a light emitting device having a resin package which provides an optical reflectivity equal to or more than 70% at a wavelength between 350 nm and 800 nm after thermal curing, and in which a resin part and a lead are formed in a substantially same plane in an outer side surface, includes a step of sandwiching a lead frame provided with a notch part, by means of an upper mold and a lower mold, a step of transfer-molding a thermosetting resin containing a light reflecting material in a mold sandwiched by the upper mold and the lower mold to form a resin-molded body in the lead frame and a step of cutting the resin-molded body and the lead frame along the notch part.Type: GrantFiled: October 30, 2015Date of Patent: January 3, 2017Assignee: NICHIA CORPORATIONInventors: Hirofumi Ichikawa, Masaki Hayashi, Shimpei Sasaoka, Tomohide Miki
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Patent number: 9537072Abstract: Pkg resin crack is suppressed after dicing. A light emitting device 1 where a light emitting device 2 that emits light is mounted on a lead frame 3 and that uses a resin cavity molding package 5 having an integrally molded lead frames 3, 4 constituting electrodes that correspond to the light emitting element 2 and resin, wherein roundness is given to a part or all of a cutting plane corner part of a retention section (hanger lead 3a, 4a) that become a cause of crack generation due to the retention sections (hanger leads 3a, 4a) of the lead frames giving stress concentration to resin at the time of cutting by a blade 7.Type: GrantFiled: March 30, 2016Date of Patent: January 3, 2017Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshiki Sota, Kazuo Tamaki
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Patent number: 9537073Abstract: A method for fabricating a light emitting diode (LED) die includes the steps of forming an epitaxial stack on a substrate having an n-type semiconductor layer, multiple quantum well (MQW) layers, and a p-type semiconductor layer. The method also includes the steps of forming a plurality of trenches in the n-type semiconductor layer, and forming a strap layer having conductive straps and contact areas in the trenches, forming an electrical insulator layer on the strap layer, forming an n-pad on the n-type semiconductor layer, and forming a p-pad on the p-type semiconductor layer.Type: GrantFiled: April 14, 2016Date of Patent: January 3, 2017Assignee: SemiLEDS Optoelectronics Co., Ltd.Inventor: Yi-Feng Shih