Abstract: A method includes depositing a first metal layer on a native SiO2 layer that is disposed on at least one of a source and a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET). A metal oxide layer is formed from the native SiO2 layer and the first metal layer, wherein the remaining first metal layer, the metal oxide layer, and the at least one of the source and the drain form a metal-insulator-semiconductor (MIS) contact.

Abstract: A method of forming a semiconductor device is provided including forming a gate structure comprising a metal-containing layer over a semiconductor layer and doping the metal-containing layer by tilted ion implantation.

Abstract: Ferroelectric semiconductor devices are provided by including a ferroelectric layer in the device that is made of a material that is not ferroelectric in bulk. Such layers can be disposed at interfaces to promote ferroelectric switching in a semiconductor device. Switching of conduction in the semiconductor is effected by the polarization of a mechanically bi-stable material. This material is not ferroelectric in bulk but can be considered to be when the thickness is sufficiently reduced down to a few atomic layers. Devices including such ferroelectric layers are suitable for various applications, such as transistors and memory cells (both volatile and non-volatile).

Abstract: A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as poly-silicon structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode.

Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over a substrate and protruding out of the plane of substrate. A source region is disposed as a top portion of the frustoconical protrusion structure. A sidewall spacer is disposed along sidewall of the source region. A source contact with a critical dimension (CD), which is substantially larger than a width of the source region, is formed on the source region and the sidewall spacer together.

Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.

Abstract: A structure including a plurality of fins etched from a semiconductor substrate, a gate electrode above and perpendicular to the plurality of fins, a pair of sidewall spacers disposed on opposing sides of the gate electrode, a gap fill material above the semiconductor substrate and between the plurality of fins, the gap fill material is directly below the gate electrode and directly below the pair of sidewall spacers, wherein the gate electrode separates the gap fill material from each of the plurality of fins, and an epitaxially grown region above a portion of the plurality of fins not covered by the gate electrode, the EPI region separates the gap fill material from each of the plurality of fins.

Abstract: An embodiment device includes a gate stack extending over a semiconductor substrate, a hard mask disposed on a top surface of the gate stack, and a low-k dielectric spacer on a side of the gate stack. A top of the low-k dielectric spacer is lower than an upper surface of the hard mask. The device further includes a contact electrically connected to a source/drain region adjacent the gate stack. The contact extends laterally over the low-k dielectric spacer, and a dielectric material is disposed between the contact and the low-k dielectric spacer. The dielectric material has a higher selectivity to etching than the low-k dielectric spacer.

Abstract: A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

Abstract: A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.

Abstract: A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer, a band-offset layer having a wider bandgap than the channel layer, a spacer layer having a narrower bandgap than the band-offset layer, and a cap layer comprising at least two sublayers. Each sublayer is selectively etchable with respect to sublayers immediately below and above, each sublayer comprises a III-N material AlxInyGazN in which 0?x?1, 0?y?1, and 0?z?1, at least one sublayer has a non-zero Ga content, and a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer. Also described are methods for fabricating such semiconductor structures, with gate and/or ohmic recesses formed by selectively removing adjacent layers or sublayers. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.

Abstract: A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.

Abstract: Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method further includes forming under a first set of conditions an enriched upper portion of the at least one fin. The method further includes forming under a second set of conditions an electrically isolated region from a lower portion of the at least one fin, wherein forming under the first set of conditions is spaced in time from forming under the second set of conditions. The method further includes controlling the first set of conditions separately from the second set of conditions.

Abstract: A line-end cutting method for fin structures of FinFETs formed by double patterning technology firstly utilizes the SiN hard mask lines to form fin structures and then performs lithography and etching processes to form line-end cuts. Since the depth of the line-end cuts is large, there is enough time and space to regulate the etching recipe so as to balance the etching rate of multiple layers including the spin-on-carbon layer, the SiN layer, the SiO2 layer and the silicon substrate, thereby forming the fin structures with line-end cuts having flatter bottom topography, preventing the formation of silicon protrusions or silicon cones during the etching process and improving the device electrical performance.

Abstract: A method of making a semiconductor device includes forming a gate on a substrate; removing an end portion of the gate to form a recess at an end of the gate; depositing a low-k material in the recess such that an air gap is formed in the low-k material; removing a portion of the low-k material; depositing an insulating material on the low-k material that was recessed to form a bilayer insulating stack; and forming a source/drain contact on an active area positioned on the substrate and alongside the gate.

Abstract: Device structures and fabrication methods for a fin-type field-effect transistor. A first fin and a second fin are formed that are comprised of a semiconductor material that is single crystal. The first fin has a sidewall facing a sidewall of the second fin. A portion of a source/drain region of the first fin is damaged to form a damage region in the portion of the first fin. After the damage region is formed, a section of a semiconductor layer is epitaxially grown from the sidewall of the first fin in the source/drain region. The semiconductor material in the damage region has a level of crystalline disorder that is greater than a level of crystalline disorder of the semiconductor material in a portion of the first fin that is not damaged.

Abstract: One method disclosed herein includes, among other things, forming a patterned fin having a thickness that is equal to or greater than a target final fin height for a replacement fin, performing an etching process through the patterned fin etch mask to form a plurality of trenches in a semiconductor substrate to define a substrate fin and forming a recessed layer of insulating material in the trenches so as to expose the patterned fin etch. The method also includes forming a layer of CTE-matching material around the exposed patterned fin etch mask, removing the patterned fin etch mask to thereby define a replacement fin cavity and expose a surface of the substrate fin, forming the replacement fin on the substrate fin and in the replacement fin cavity, removing the layer of CTE-matching material and forming a gate structure around at least a portion of the replacement fin.

Abstract: A method of forming a single diffusion break includes patterning a fin hardmask disposed over a substrate. First and second fin arrays separated by an isolation region are etched into the substrate from the patterned fin hardmask. Any remaining fin hardmask being self-aligned with the fins. A first dielectric fill material is disposed and planarized over the arrays to expose top surfaces of the remaining fin hardmask. A second dielectric strip is formed over the first dielectric fill material to cover the isolation region and end portions of the remaining fin hardmask. Any exposed portions of the remaining fin hardmask are anisotropically etched away. The end portions of the remaining fin hardmask form base extensions of a base for a single diffusion break (SDB) in the isolation region. The first dielectric fill material and second dielectric strip are etched to complete formation of the base for the single diffusion break.

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

Abstract: A thin film transistor 100 according to the invention includes a gate electrode 20, a channel 44, and a gate insulating layer 34 provided between the gate electrode 20 and the channel 44 and made of oxide (possibly containing inevitable impurities; this applies to oxide hereinafter) containing lanthanum and zirconium. The channel 44 is made of channel oxide including first oxide containing indium, zinc, and zirconium (Zr) having an atomic ratio of 0.015 or more and 0.075 or less relative to indium assumed to be 1 in atomic ratio, second oxide containing indium and zirconium (Zr) having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio, or third oxide containing indium and lanthanum having an atomic ratio of 0.055 or more and 0.16 or less relative to the indium (In) assumed to be 1 in atomic ratio.

Abstract: A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a corresponding opening formed in an insulating layer covering a semiconductor layer. The opening of the source electrode layer and the opening of the drain electrode layer are formed separately in two distinct steps. The source electrode layer and the drain electrode layer are formed by depositing a conductive layer over the insulating layer and in the openings, and subsequently removing the part located over the insulating layer by polishing. This manufacturing method allows for the source electrode later and the drain electrode layer to be formed close to each other and close to a channel forming region of the semiconductor layer. Such a structure leads to a transistor having high electrical characteristics and a high manufacturing yield even in the case of a minute structure.

Abstract: Teaching disclosed herein is an apparatus comprising a support layer. The support layer may be adapted for supporting a heat generator, wherein the support layer includes a flow passage. The flow passage may seal working fluid therein. The flow passage may extend along a thickness direction of the support layer.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, a plurality of first regions that are spaced apart from each other along a first direction by portions of the semiconductor layer, each of the first regions including a first semiconductor region of a second conductivity type, a second region between the first regions in the first direction, the second region including a second semiconductor region of the first conductivity type and a first insulator between the second semiconductor region and the semiconductor layer, and a third region between the first region and the second region, the third region including a third semiconductor region of the first conductivity type and a second insulator.

Abstract: [Problem] To provide a semiconductor device wherein withstand voltage of a gate insulating film at the upper edge of a trench is improved, and a method for manufacturing the semiconductor device. [Solution] A semiconductor device (1) includes: an n-type SiC substrate (2) having a gate trench (9) formed therein; a gate insulating film (16), which integrally includes a side-surface insulating film (18) and a bottom-surface insulating film (19); and a gate electrode (15) which is embedded in the gate trench (9), and which selectively has an overlap portion (17) that overlaps, at the upper edge (26), the surface (21) of the SiC substrate (2). In the side-surface insulating film (18), an overhung portion (27) that is selectively thick compared with other portions of the side-surface insulating film (18) is formed such that the overhung portion protrudes, at the upper end edge (26), toward the inside of the gate trench (9).

Abstract: A semiconductor device includes transistor cells with source zones of a first conductivity type and body zones of a second conductivity type. The source and body zones are formed in a semiconductor mesa formed from a portion of a semiconductor body. Control structures include first portions extending into the semiconductor body on at least two opposing sides of the semiconductor mesa, second portions in a distance to the first surface between the first portions, and third portions in a distance to the first surface and connecting the first and the second portions, wherein constricted sections of the semiconductor mesa are formed between neighboring third portions.

Abstract: A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well.

Abstract: In a general aspect, a high-voltage metal-oxide-semiconductor (HVMOS) device can include comprising a first gate dielectric layer disposed on a channel region of the HVMOS device and a second gate dielectric layer disposed on at least a portion of a drift region of the HVMOS device. The drift region can be disposed laterally adjacent to the channel region. The second gate dielectric layer can have a thickness that is greater than a thickness of the first gate dielectric layer.

Abstract: A base layer is used that has an N-type SiC layer formed in a surface layer on the front surface side of an N-type SiC substrate, and a P-type region is formed on a surface of the N-type SiC layer with an N-type source region selectively formed in a surface layer of the P-type region. A source electrode is formed on a surface of the N-type source region and a drain electrode is formed on the back surface side of the N-type SiC substrate. Additionally, the gate electrode is formed via a gate insulation film only on a surface of the P-type region. In this way, high electric field is no longer applied to the gate insulation film on the surface of the N-type SiC layer due to stoppage of voltage application to the gate electrode.

Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.

Abstract: A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.

Abstract: Disclosed is a semiconductor device having a radio frequency switch. Also disclosed are an antenna switch module and a method of manufacturing the semiconductor device. The semiconductor device includes a metal wiring insulating film bonded to a silicon substrate. In the semiconductor device, a crystal defect layer extends into the silicon substrate from a surface of the silicon substrate. Crystal defects are throughout the crystal defect layer. The semiconductor device and an integrated circuit are in the antenna switch module. The integrated circuit in the antenna switch module is mounted with the radio-frequency switch device and the silicon substrate. The method of manufacturing the semiconductor device includes a step of forming crystal defects throughout a silicon substrate. Radiation or a diffusion is used to form the crystal defects. After the step of forming the crystal defects, the method includes a step of implanting ions into a surface of the silicon substrate to form a crystal defect layer.

Abstract: An integrated circuit includes a first transistor having a first source region, a first drain region, a first channel region, a first gate electrode, and a first layer of a first stress-creating material, the first stress-creating material providing a stress that is variable in response to a signal acting on the first stress-creating material, wherein the first layer of the first stress-creating material is arranged to provide a first variable stress in the first channel region of the first transistor, the first variable stress being variable in response to a first signal acting on the first stress-creating material. The integrated circuit also includes a second transistor having a second source region, a second drain region, a second channel region, and a second gate electrode.

Abstract: A semiconductor fin includes a channel region. A gate-stressor member, formed of a metal, extends transverse to the fin and includes gate surfaces that straddle the fin in the channel region. The gate-stressor member has a configuration that includes a partial cut spaced from the fin by a cut distance. The configuration causes, through the gate surfaces, a transverse stress in the fin, having a magnitude that corresponds to the cut distance. Transverse stressor members, formed of a metal, straddle the fin at regions outside of the channel region and cause, at the regions outside of the channel region, additional transverse stresses in the fin. The magnitude that corresponds to the cut distance, in combination with the additional transverse stresses, induces a longitudinal compressive strain in the channel region.

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises an isolation structure comprising a top surface over a substrate major surface; a cavity having a convex bottom surface below the top surface; a strained material in the cavity and extending above the top surface, wherein the strained material comprises an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface.

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a doped region in an upper portion of the substrate. The doped region is doped with first dopants of a first conduction type. The semiconductor device structure includes one fin structure over the substrate. A first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure. The semiconductor device structure includes an isolation layer over the substrate and at two opposite sides of the fin structure. The semiconductor device structure includes a gate over the isolation layer and the fin structure.

Abstract: One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.

Abstract: It is an object to manufacture a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. An insulating layer which covers an oxide semiconductor layer of the thin film transistor contains a boron element or an aluminum element. The insulating layer containing a boron element or an aluminum element is formed by a sputtering method using a silicon target or a silicon oxide target containing a boron element or an aluminum element. Alternatively, an insulating layer containing an antimony (Sb) element or a phosphorus (P) element instead of a boron element covers the oxide semiconductor layer of the thin film transistor.

Abstract: A display device is provided including a first substrate comprising a resin material provided with a plurality region provided with a plurality of pixels including a display device, and a second substrate provided facing the first substrate and installed with the pixel region, wherein an outer periphery side surface of the first substrate having a taper shape and including a barrier layer covering an upper layer, lower layer and the outer periphery side surface of the first substrate.

Abstract: Threshold voltage adjustment method of a semiconductor device is provided. In a semiconductor device in which at least one of transistors included in an inverter includes a semiconductor, a source electrode or a drain electrode electrically connected to the semiconductor, a gate electrode, and a charge trap layer provided between the gate electrode and the semiconductor, the potential of the gate electrode of the transistor that is higher than those of the source electrode and the drain electrode is held for a short time of 5 s or shorter, whereby electrons are trapped in the charge trap layer and the threshold voltage is increased. At this time, when the potential differences between the gate electrode and the source electrode, and the gate electrode and the drain electrode are different from each other, the threshold voltage of the transistor of the semiconductor device becomes appropriate.

Abstract: Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners formed by an anneal in a gaseous environment. A gate dielectric layer is on the channel region of the one or more semiconductor fins, conforming to the contours of the one or more semiconductor fins. A gate structure is on the gate dielectric layer.

Abstract: A memory device is disclosed. The memory device includes a substrate, including a substrate, including a source region and a drain region; and a gate stack, formed over a surface of the substrate, wherein the gate stack includes: a tunneling layer; a first layer; a second layer; a third layer; and a blocking layer; wherein each of the tunneling layer and the blocking layer has an oxygen proportion higher than the first, the second and the third layers; the first layer has a highest silicon proportion among the first, the second and the third layers; the second layer has a highest oxygen proportion among the first, the second and the third layers; and the first layer has a highest nitrogen proportion among the first, the second and the third layers. An associated gate stack and a manufacturing method are also disclosed.

Abstract: A planar diode and method of making the same employing only one mask. The diode is formed by coating a substrate with an oxide, removing a central portion of the oxide to define a window through which dopants are diffused. The substrate is given a Ni/Au plating to provide ohmic contact surfaces, and the oxide on the periphery of the window is coated with a polyimide passivating agent overlying the P/N junction.

Abstract: A photo-voltaic cell has a first and second two-dimensional array of contact points on the first surface, each coupled to a respective one of base and emitter areas in or on the semi-conductor body. Electrically separate first and second conductor structures on the first surface emanate from each contact point, coupled to contact points of the first and second two-dimensional array respectively. The first conductor structure comprises sets of first conductor line branches, the first conductor line branches of each set branching out from a respective one of the contact points of the first two-dimensional array in at least three successive different directions at less than a hundred and eighty degrees to each other.

Abstract: A semiconductor device includes a base, a semiconductor element disposed on the base, a resist layer formed on the base, and a resin-sealed portion covering the semiconductor element and the resist layer. A plurality of concave portions is formed in the resist layer, and each of the plurality of concave portions is filled with a part of the resin-sealed portion.

Abstract: A method of manufacturing a solar cell electrode comprising steps of: preparing a semiconductor substrate, applying a conductive paste onto the light receiving side of the semiconductor substrate, wherein the conductive paste comprises (i) a conductive powder, (ii) a glass frit, (iii) an organic polymer comprising an elastomer and (iv) an organic solvent; and firing the applied conductive paste.

Abstract: A concentrated photovoltaic cell comprises a semiconductor stack comprising an upper surface and a lower surface opposite to the upper surface, wherein the upper surface is operable to absorb a light which comprises a light intensity distribution on the upper surface; and an upper electrode formed on the upper surface of the semiconductor stack and comprising an electrode pattern approximately corresponding to the light intensity distribution, wherein the light intensity distribution comprises a high light-concentrated area having a first light intensity and a low light-concentrated area having a second light intensity, wherein the second light intensity is lower than the first light intensity.

Abstract: A wavelength converting material comprising a phosphate compound have a chemical formula of AB1-m-nPO4:Mm, Nn, wherein A comprises an alkali metal element, B comprises an alkaline earth metal element, M is a sensitizer comprising a rare-earth element, and N is an acceptor comprising a rare-earth element, wherein 0<m?0.3 and 0<n?0.3.

Abstract: An image pickup apparatus includes: an image pickup device disposed in a first principal surface of a silicon substrate, the image pickup device sensing infrared light; an electrode pad disposed on the first principal surface; a front-face wiring connecting the image pickup device and the electrode pad; an external connection terminal disposed on a second principal surface of the silicon substrate; a back-face wiring connecting the electrode pad and the external connection terminal via a substrate through-hole extending from the second principal surface side through the silicon substrate to a back face of the electrode pad; and a light blocking layer disposed on the second principal surface, the light blocking layer covering a trench portion surrounding the image pickup device and a region surrounded by the trench portion.