Abstract: A semiconductor chip includes a substrate including a surface, an active transistor region and a substrate contact region formed on the substrate, a shallow trench isolation (STI) area formed in the surface and disposed at least partially between the active transistor region and the substrate contact region, and at least one capacitor at least partially buried in the STI area.

Abstract: Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode.

Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.

Abstract: An IGBT is disposed in an IGBT portion, and an FWD is disposed in an FWD portion. A p-type base region and an n?-type drift region are alternately exposed in a trench longitudinal direction in a substrate front surface in a mesa portion between neighboring trenches in the IGBT portion. A p-type anode region and the n?-type drift region are alternately exposed in the trench longitudinal direction in the substrate front surface in a mesa portion in the FWD portion, and a repetitive structure is formed with a portion of the n?-type drift region sandwiched between p-type anode regions and one p-type anode region in contact with the portion as one unit region. The proportion occupied by the p-type anode region in one unit region (an anode ratio) (?) is 50% to 100%.

Abstract: A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close proximity to the first FET. A gate of the second FET is separated from the first FET, and a source and drain of the second FET are shorted together. A resistance of the gate of the second FET between two terminals on the gate of the second FET varies with a temperature local to the first FET.

Abstract: One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure.

Abstract: Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed the trench to be disposed on the deposition insulating layer, and a metal gate formed the trench on the gate insulating layer.

Abstract: A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the plurality of fins remaining exposed. Spacers are formed on opposite sidewalls of the second portion of the plurality of fins. The second portion of the plurality fins is removed to form a trench between the spacers. An epitaxial layer is formed in the trench. The spacers on opposite sides of the epitaxial layer constrain lateral growth of the epitaxial layer.

Abstract: Methods of fabricating devices (e.g., FDSOI devices) having multiple threshold voltages are described. One method includes providing a first fixed charge region proximate to an interface of an insulating (e.g., buried oxide (BOX) layer) and a semiconductor substrate for a first device. The first charge region has a first configuration of fixed charges. The method also includes providing a second fixed charge region proximate to the interface of the insulating layer and the semiconductor substrate for the second device. The second charge region has a second configuration of fixed charges that is different than the first configuration.

Abstract: Semiconductor devices are provided. The semiconductor devices include a first fin; a first gate electrode intersecting the first fin; a first elevated source and/or drain on respective sides of the first gate electrode on the first fin; and a first field dielectric film adjacent the first fin. The first field dielectric film includes a first part below a top surface of the first fin and a second part protruding from the first part and above a top surface of the first fin that makes contact with the first elevated source and/or drain.

Abstract: Disclosed are isolation techniques for bulk FinFETs. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor substrate. The fin structure is perpendicular to the semiconductor substrate and has an upper portion and a lower portion. Source and drain regions are adjacent to the fin structure. A gate structure surrounds the upper portion of the fin structure. A well contact point is provided in the semiconductor substrate. The lower portion of the fin structure includes a sub-fin between the region surrounded by the gate structure and the semiconductor substrate. The sub-fin directly contacts the semiconductor substrate. The upper portion of the fin structure and an upper portion of the sub-fin are undoped. A lower portion of the sub-fin may be doped. Electrical potential applied from the well contact point to the lower portion of the sub-fin reduces leakage currents from the upper portion of the fin structure.

Abstract: According to one exemplary implementation, a dual anti-fuse structure includes a first channel in a common semiconductor fin adjacent to a first programmable gate. The dual anti-fuse structure further includes a second channel in said common semiconductor fin adjacent to a second programmable gate. A first anti-fuse is formed between the first channel and the first programmable gate. Furthermore, a second anti-fuse is formed between the second channel and the second programmable gate. The first programmable gate can be on a first sidewall of the common semiconductor fin and can comprise a first gate dielectric and a first electrode. The second programmable gate can be on a second sidewall of the common semiconductor fin and can comprise a second gate dielectric and a second electrode.

Abstract: A semiconductor device can include a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second direction, the plurality of active regions being repeatedly and separately positioned along the first and second directions, an isolation film defining the plurality of active regions, a plurality of word lines extending across the plurality of active regions and the isolation film, and a positive fixed charge containing layer covering at least a portion of the plurality of word lines, respectively.

Abstract: A semiconductor device including a pFET and an nFET where: (i) the gate and conductor channel of the pFET are electrically insulated from a buried oxide layer; and (ii) the conductor channel of the nFET is in the form of a fin extending upwards from, and in electrical contact with, the buried oxide layer. Also, a method of making the pFET by adding a fin structure extending from the top surface of the buried oxide layer, then condensing germanium locally into the lattice structure of the lower portion of the fin structure, and then etching away the lower portion of the fin structure so that it becomes a carrier channel suspended above, and electrically insulated from the buried oxide layer.

Abstract: A semiconductor device includes a first diode connected transistor of a first conductivity type and a second diode connected transistor of a second conductivity type connected in series, each of the first and second diode connected transistors being configured to exhibit negative differential resistance in response to an applied voltage. The first drain and first source regions of the first diode connected transistor include dopants of the first conductivity type at degenerate dopant concentration levels and a gate of the first diode connected transistor has a work function that corresponds to that of the semiconductor containing dopants of the second conductivity type. The second drain and second source regions of the second diode connected transistor include dopants of the second conductivity type at degenerate dopant concentration levels and a gate of the second diode connected transistor has a work function that corresponds to that of the semiconductor containing dopants of the first conductivity type.

Abstract: A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided.

Abstract: The present disclosure relates a method of forming an integrated circuit. In some embodiments, the method is performed by patterning a first masking layer over a substrate to have a first plurality of openings at a memory cell region and a second plurality of openings at a boundary region. A first plurality of dielectric bodies are formed within the first plurality of openings and a second plurality of dielectric bodies are formed within the second plurality of openings. A second masking layer is formed over the first masking layer and the first and second plurality of dielectric bodies. The first and second masking layers are removed at the memory cell region, and a first conductive layer is formed to fill recesses between the first plurality of dielectric bodies. A planarization process reduces a height of the first conductive layer and removes the first conductive layer from over the boundary region.

Abstract: A split gate memory device, a semiconductor device and a manufacturing method thereof are provided. In the split gate memory device, an erasing gate is further disposed, wherein the easing gate and a control gate are respectively disposed on two sides of a floating gate. Thus, an erase operation is implemented by the erasing gate instead of the control gate. Accordingly, electric potential applied to the control gate is reduced. Therefore, hot-electron effect in channel region may be avoided, and performance degradation of the memory caused by the hot-electron effect may be avoided as well. Furthermore, as electric potential applied to the control gate is reduced, a gate oxide layer underneath the control gate may be thinner. Accordingly, manufacturing processes of the control gate and the gate oxide layer and that of the gate and the gate oxide layer of a logic transistor in a periphery circuit may be compatible.

Abstract: A flash memory disposed on a substrate is provided. The flash memory includes a semiconductor transistor including stacked gate structures, lightly doped regions and spacers. The stacked gate structures include a gate dielectric layer, a first conductive layer, a dielectric layer and a second conductive layer sequentially disposed on the substrate. The dielectric layer has an opening there around such that the first conductive layer electrically connects with the second conductive layer. The lightly doped regions are disposed in the substrate under the opening at sides of the stacked gate structures. The spacers are disposed on sidewalls of the stacked gate structures. A width of spacers is adjusted by controlling a height of the first conductive layer under the opening. The lightly doped regions are disposed by using the dielectric layer as a mask layer, so as to gain margins of the lightly doped regions for good electrical properties.

Abstract: A nonvolatile memory device having a plurality of unit cells, each of the plurality of unit cells includes a first transistor suitable for having a fixed threshold voltage, and a second transistor suitable for coupling to the first transistor in parallel and having a variable threshold voltage.

Abstract: A pillar-shaped semiconductor memory device includes an i-layer substrate, a silicon pillar, a tunnel insulating layer, a data charge storage insulating layer, a first interlayer insulating layer, a second interlayer insulating layer, and word-line conductor layers separated by third interlayer insulating layers. The tunnel insulating layer, the data charge storage insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer are formed so as to surround an outer peripheral portion of a side surface of the silicon pillar. The word-line conductor layers and the third interlayer insulating layers are formed so as to surround an outer peripheral portion of a side surface of the second interlayer insulating layer in a direction perpendicular to a surface of the i-layer substrate.

Abstract: A three-dimensional (3D) memory and a method for manufacturing the same are disclosed. According to one embodiment, the 3D memory comprises a thin-film transistor. The thin-film transistor has a source region and a drain region disposed separately. The source region comprises a first source region and a second source region disposed between the first source region and the drain region. The first source region is p-type of doping, the second source region is n-type of doping, and the drain region is n-type of doping.

Abstract: According to an embodiment, a non-volatile memory device includes first electrodes arranged in a first direction, a second electrode disposed on a side of the first electrodes in the first direction, a semiconductor layer extending in the first direction through the first electrodes and the second electrode, and a memory film provided between the semiconductor layer and each of the first electrodes. The semiconductor layer includes crystal grains and has a first portion and a second portion, the first portion being adjacent to the first electrodes, and the second portion being adjacent to at least a part of the second electrode, wherein the first portion includes a larger crystal grain than a crystal grain in the second portion.

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.

Abstract: A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.

Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film.

Abstract: A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

Abstract: A method of manufacturing a semiconductor device, by etching a region of an SOI substrate so that only a portion of the original semiconductor is present above the insulator layer. After etching has occurred, a different semiconductor material is grown in the etched region, and fins are formed. An isolation layer is deposited to a height above that the base semiconductor of the etched region.

Abstract: The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Abstract: A thin film transistor array substrate includes a pixel electrode layout area, a data electrode layout area, a transparent pixel electrode layer formed in the pixel electrode layout area, a first metal layer, a first dielectric layer, an amorphous silicon layer, a second metal layer, a second dielectric layer formed in the pixel electrode layout area and the data electrode layout area. The first dielectric layer covers the first metal layer. The amorphous silicon layer, the second metal layer and the second dielectric layer are sequentially formed on the first dielectric layer. The transparent pixel electrode layer is connected to the second metal layer through a via hole formed in the pixel electrode area of the second dielectric layer. Moreover, a method for manufacturing the thin film transistor array and a liquid crystal display including the thin film transistor array substrate also are provided.

Abstract: To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

Abstract: A light-emitting device capable of suppressing variation in luminance among pixels is provided. A light-emitting device includes a pixel and first and second circuits. The first circuit has a function of generating a signal including a value of current extracted from the pixel. The second circuit has a function of correcting an image signal by the signal. The pixel includes at least a light-emitting element and first and second transistors. The first transistor has a function of controlling supply of the current to the light-emitting element by the image signal. The second transistor has a function of controlling extraction of the current from the pixel. A semiconductor film of each of the first and second transistors includes a first semiconductor region overlapping with a gate, a second semiconductor region in contact with a source or a drain, and a third semiconductor region between the first and second semiconductor regions.

Abstract: An active matrix substrate (5) includes mounting terminals (DT) for supplying a signal from a driver, draw-out lines (22) connecting the mounting terminals (DT) and gate bus lines (G) or data bus lines (D), first common wires (24) connected in common to the plurality of gate bus lines (G) or the plurality of data bus lines (D), and second switching elements (23) connected between the draw-out lines (22) and the first common wires (24). The draw-out lines (22) include a fan-out portion (FA) that is arranged at an angle with respect to a direction of arrangement of the gate bus lines (G) or the data bus lines (D). At least a portion of the first common wires (24) and at least a portion of the second switching elements (23) are arranged between the fan-out portion (FA) and the mounting terminals (DT).

Abstract: A pixel structure is disclosed. The pixel structure includes a plurality of data lines arranged in a first direction, and a plurality of gate lines arranged in a second direction. The plurality of data lines intersect with the plurality of gate lines near a plurality of sub-pixels. In addition, each of the plurality of sub-pixels includes a thin film transistor, and a pixel electrode. The plurality of sub-pixels includes a plurality of first rows of sub-pixels, and a plurality of second rows of sub-pixels, where the first rows of sub-pixels and the second rows of sub-pixels are interleaved, each sub-pixel in the first rows of sub-pixels is provided with a signal over a second-closest data line, and each sub-pixel in the second rows of sub-pixels is provided with a signal over a first-closest data line.

Abstract: According to one embodiment, provided is a thin film transistor with which it is possible to reduce the leakage current and thereby, for a liquid crystal display device, to ensure a good display quality. The thin film transistor includes a semiconductor layer, gate electrodes, first light-blocking electrodes, and second light-blocking electrodes. The first light-blocking electrodes are disposed opposite to the gate electrodes with respect to the semiconductor layer and opposed to channel regions to block light incident into the channel regions. The second light-blocking electrodes are disposed opposite to the semiconductor layer with respect to the gate electrodes, arranged to block light incident into the channel regions, and electrically connected with one of a signal line and a pixel electrode.

Abstract: A thin-film transistor array panel includes an insulation substrate, a gate line disposed on the insulation substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line disposed on the semiconductor layer and including a source electrode, a drain electrode disposed on the semiconductor layer and facing the source electrode, a first electrode disposed on the gate insulating layer, a first passivation layer disposed on the first electrode and including silicon nitride, a second passivation layer disposed on the first passivation and including silicon nitride, and a second electrode disposed on the passivation layer, in which a first ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the first passivation layer is different from a second ratio of nitrogen-hydrogen bonds to silicon-hydrogen bonds in the second passivation layer.

Abstract: A display panel is provided. A display panel includes a plurality of pixels and a plurality of gate lines. The pixels include a first pixel, a second pixel and a third pixel. The gate lines include a first gate line, a second gate line and a third gate line. The first gate line drives the first pixel. The second gate line drives the second pixel. The third gate line drives the third pixel. The first gate line, the second gate line and the third gate line are disposed sequentially and driven at different time. The first pixel and the second pixel are arranged respectively at two opposite sides of the first gate line and the second gate line. The second pixel and the third pixel are arrange between the second gate line and the third gate line.

Abstract: In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.

Abstract: The present invention discloses an assembling method for array substrate and color filter substrate of liquid crystal display, which comprises: coating a seal on a color filter substrate; forming multiple sealing points at the predetermined position between an array substrate with liquid crystal and the color filter substrate; rotating the color filter substrate to fit the array substrate; irradiating the sealing points using a light source to cure the sealing points, so that the array substrate and the color filter substrate are bonded. According to the embodiment of the present invention, it can be aligned precisely during assembling process of the array substrate and the color filter substrate, which avoids the poor substrate alignment caused by handling or flip and then improves the product yield.

Abstract: A method of transferring a thin film is a method of transferring a thin film formed on a first substrate to a second substrate, the method including: allowing the first substrate to come into contact with a liquid to swell the first substrate; allowing the second substrate and the thin film to come into contact with each other via the liquid; and drying the liquid to allow the thin film to adhere to the second substrate.

Abstract: Disclosed is a display device integrated with a touch screen panel and a method for fabricating the same. The display includes: a TFT positioned at each pixel region; a first electrode spaced from one of a source electrode or a drain electrode of the TFT; a second electrode facing the first electrode; a TFT protective layer positioned on the TFT and has a first contact hole; a touch signal line positioned between a first touch connection pattern, which is made of the same material as the first electrode, and a second touch connection pattern made of the same material as the second electrode, and transfers a touch driving signal to the second touch connection pattern; a first connection pattern made of the same material as the second electrode; and a first electrode protective layer positioned on the first electrode and the touch signal line.

Abstract: There is provided a front side illuminated (FSI) semiconductor structure with improved light absorption efficiency which is configured to provide a reflecting layer on a bottom of the FSI semiconductor structure to enhance the light absorption efficiency, wherein the reflecting layer is manufactured in the packaging process or the semiconductor process.

Abstract: An image sensor includes a substrate, photosensitive devices, a color filter layer, a micro-lens layer and an infrared filter layer. The photosensitive devices are disposed in the substrate. The color filter layer is disposed to cover the photosensitive devices. The micro-lens layer is disposed on the color filter layer. The infrared filter layer directly covers the micro-lens layer.

Abstract: A stacked type image sensor including color separation elements, and an image pickup apparatus including the stacked type image sensor, are provided. The stacked type image sensor includes a first light sensing layer including first pixels configured to absorb and detect light of a first wavelength band and transmit light of a second wavelength band and a third wavelength band, and a second light sensing layer disposed to face the first light sensing layer, the second light sensing layer including second pixels configured to detect light of the second wavelength band and third pixels configured to detect light of the third wavelength band. The color separation elements are disposed between the first light sensing layer and the second light sensing layer, and are configured to direct the light of the second wavelength band toward the second pixels, and direct the light of the third wavelength band toward the third pixels.

Abstract: Methods and structures for providing single-color or multi-color photo-detectors leveraging cavity resonance for performance benefits. In one example, a radiation detector (110) includes a semiconductor absorber layer (210, 410A, 410B, 610, 810, 1010, 1030, 1210, 1230) having a first electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region, a semiconductor collector layer (220, 630, 830, 1020, 1040) coupled to the absorber layer (210, 410A, 41013, 610, 810, 1010, 1030, 1210, 1230) and having a second electrical conductivity type, and a resonant cavity coupled to the collector layer (220, 630, 830, 1020, 1040) and having a first mirror (240) and a second mirror (245).

Abstract: An integrated circuit includes a semiconductor substrate, at least one photodiode, which is formed on a surface of the semiconductor substrate, at least one trench, which extends from the surface of the semiconductor substrate into the semiconductor substrate and surrounds a region of the semiconductor substrate on which the photodiode Is arranged, and at least one cavity in the semiconductor substrate, which is located below the surface of the semiconductor substrate. The at least one trench and the at least one cavity form an electrical insulation structure between the region of the semiconductor substrate on which the photodiode is arranged and one or more adjacent regions of the semiconductor substrate.

Abstract: A solid-state imaging device includes: a semiconductor substrate provided with an effective pixel region including a light receiving section that photoelectrically converts incident light; an interconnection layer that is provided at a plane side opposite to the light receiving plane of the semiconductor substrate; a first groove portion that is provided between adjacent light receiving sections and is formed at a predetermined depth from the light receiving plane side of the semiconductor substrate; and an insulating material that is embedded in at least a part of the first groove portion.

Abstract: An image sensor includes a sensor portion and an ASIC portion bonded to the sensor portion. The sensor portion includes a first substrate having radiation-sensing pixels, a first interconnect structure, a first isolation layer, and a first dielectric layer. The ASIC portion includes a second substrate, a second isolation layer, and a second dielectric layer. The material compositions of the first and second isolation layers and the first and second dielectric layers are configured such that the first and second isolation layers may serve as barrier layers to prevent copper diffusion into oxide. The first and second isolation layers may also serve as etching-stop layers in the formation of the image sensor.

Abstract: A radiation image-pickup device includes: a plurality of pixels each configured to generate signal charge based on radiation; and a field effect transistor used to read the signal charge from each of the plurality of pixels, wherein the field effect transistor includes a semiconductor layer including an active layer and a low concentration impurity layer formed to be adjacent to the active layer, and a first and a second gate electrode disposed to face each other with the active layer interposed therebetween, and one or both of the first and the second gate electrodes are provided in a region not facing the low concentration impurity layer.