Abstract: A fabricating method of a recess with asymmetric walls includes the steps of providing a substrate comprising a top surface. A recess is formed in the substrate, wherein the recess comprises a first wall, a second wall and a bottom. A patterned mask is formed to cover the substrate. Part of the top surface adjacent to the second wall is exposed through the patterned mask. Finally, the substrate is removed to form a sloping wall, wherein the sloping wall, the first wall and the bottom form a recess with asymmetric walls.

Abstract: A solid-state image pickup device has an image pickup pixel including a first photoelectric conversion portion and a first transistor and a focus detection pixel including a second photoelectric conversion portion, a second transistor, and a light shielding portion, in which a reflection preventing portion is provided on the underface side of the light shielding portion.

Abstract: A light-emitting diode is provided to include: a transparent substrate having a first surface, a second surface, and a side surface; a first conductive semiconductor layer positioned on the first surface of the transparent substrate; a second conductive semiconductor layer positioned on the first conductive semiconductor layer; an active layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer; a first pad electrically connected to the first conductive semiconductor layer; and a second pad electrically connected to the second conductive semiconductor layer, wherein the transparent substrate is configured to discharge light generated by the active layer through the second surface of the transparent substrate, and the light-emitting diode has a beam angle of at least 140 degrees or more. Accordingly, a light-emitting diode suitable for a backlight unit or a surface lighting apparatus can be provided.

Abstract: A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns.

Abstract: Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junction serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage.

Abstract: A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a semiconductor substrate and a first pillar-shaped semiconductor layer, a first dummy gate layer and a second pillar-shaped semiconductor layer, and a second dummy gate layer. Third and fourth dummy gate layers are formed on sidewalls of the first dummy layer gate, the first pillar-shaped semiconductor layer, the second dummy gate layer and the second pillar-shaped semiconductor layer. An interlayer insulating film is deposited, the dummy gate layers are removed, and a gate insulator is formed film around the first and second pillar-shaped semiconductor layers. A first metal is deposited and a gate electrode and a gate line are formed around the first pillar-shaped semiconductor layer. Second and third metals are deposited and a first contact and a pillar-shaped resistance-changing layer, a lower electrode, and a reset gate are formed.

Abstract: An organic light-emitting display device comprising a substrate; an insulating layer disposed on the substrate; a plurality of bottom electrodes arranged on the insulating layer in a matrix pattern defining a plurality of intersecting rows and columns; an organic layer disposed on each of the bottom electrodes; a top electrode disposed on the organic layer; and a plurality of wiring lines adjacent to the first bottom electrode, the wiring lines being formed on the insulating layer placed between the rows of the bottom electrodes.

Abstract: According to one embodiment, a method of manufacturing a display device, includes preparing a first substrate formed such that a first resin layer is formed on a first support substrate, preparing a second substrate formed such that a second resin layer is formed on a second support substrate, attaching the first substrate and the second substrate, peeling the second support substrate from the second resin layer by radiating a first laser beam toward the second substrate, mounting a signal supply source on a first mounting portion in a state in which the second resin layer, which is opposed to the first mounting portion, is warped in a direction away from the first mounting portion, and adhering the first resin layer and the second resin layer.

Abstract: In a display device including an device substrate arranged with a plurality of pixels arranged with a light emitting device, a color filter layer with different transmission bands corresponding to each of the pixels, and a color filter substrate arranged with an overcoat layer above the color filter layer, by arranging a first light shielding layer arranged corresponding to a matrix of pixels and a second light shielding layer wider than the first light shielding layer and separated from the first light shielding layer and on a side close to a pixel, light emitted in a diagonal direction leaking to an adjacent pixel enters the second light shielding layer and by increasing the length of a light path of the incident light, the light is absorbed and attenuated by the second light shielding layer and improvements in viewing angle characteristics are achieved without decreasing the aperture ratio of a pixel.

Abstract: An organic light emitting diode (OLED) display with an improved light efficiency and a method of manufacturing the OLED display are disclosed. The OLED display includes a substrate, an insulation layer on the substrate and having concave portions, first electrodes on the insulation layer, pixel defining layers (PDLs) on the insulation layer and configured to define the first electrodes into pixels, organic light emitting layers on the first electrodes as defined by the pixels, and a second electrode on the organic light emitting layers. Each of the concave portions includes a bottom surface and inclined parts. Each of the first electrodes is on the bottom surface and the inclined parts of one of the concave portions. Embossings are on a part of a surface of the PDLs.

Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.

Abstract: A display device, in which self-luminous elements are arranged, prevents a leakage current through a common layer, provided for the self-luminous elements and disposed throughout its image display area, from causing adjacent pixels to emit unintended light. A light-emitting element layer 102 includes a lower layer 102d and a light-emitting layer. The lower layer 102d has carrier mobility and includes a carrier transport layer or a carrier injection layer. The lower layer 102d is stacked on lower electrodes 100 and banks 106. The light-emitting layer is stacked on the lower layer 102d. An upper electrode 62 is disposed on the light-emitting element layer 102 and supplies carriers to the light-emitting element layer 102 together with each lower electrode. A lower layer 102d has a dividing area 112 on the bank. The dividing area 112 prevents carriers from traveling between adjacent pixels through the lower layer 102d.

Abstract: The present invention provides an OLED array substrate, a manufacturing method of the same, a display panel, and a display device, and relates to the field of active matrix organic light-emitting diode (AMOLED) display technology. The present invention can solve the problem that turn-on and turn-off of a switching thin film transistor and grayscale control cannot be performed effectively because the switching thin film transistor and a driving thin film transistor are manufactured as thin film transistors having same performance parameters in an existing OLED array substrate. The OLED array substrate according to the present invention includes a switching thin film transistor and a driving thin film transistor, wherein, an S factor of the switching thin film transistor is less than that of the driving thin film transistor.

Abstract: A novel light-emitting device includes an organic thin-film structure that is merged with an organic light-emitting diode structure by utilizing a part of the electron accumulation layer in the organic thin-film transistor as a common electrode for each structure. The organic thin-film structure and the organic light-emitting diode structure each include an organic semiconductor that comprises a material in which hole mobility is greater in a bulk region of the material than electron mobility in the bulk region. The advantages of such a light-emitting device include less complex processing and a simpler pixel circuit structure in comparison to separately fabricating OTFT and OLED structures and subsequently interconnecting them to form a pixel. Furthermore, relative to a light-emitting transistor, some embodiments offer the advantage of a broader light emission area more suitable for use in display devices.

Abstract: An organic light emitting diode display includes a display substrate, a sealing member disposed to face the display substrate, a sealant disposed between the display substrate and the sealing member, the sealant being configured to attach the display substrate and the sealing member to each other, a plurality of conductive wires on the display substrate, the conductive wires overlapping the sealant, and at least one short-circuit blocking layer between the conductive wires.

Abstract: When writing a signal current from a current source to a current source circuit, noise occurs in some cases in a wiring through which a current flows, which may cause a potential of the wiring to be outside the normal range. As the potential does not turn back within the normal range easily at this time, writing to the current source circuit is delayed. According to the invention, when the potential becomes outside the normal range due to noise occurring in a wiring through which a current flows when writing a signal current from a current source to a current source circuit, a current is supplied from other than the current source, thereby the potential of the wiring can turn back within the normal range rapidly.

Abstract: A semiconductor device including a resistor metallic layer and method forming the same. In one embodiment, the semiconductor device includes a source region and a drain region of a semiconductor switch on a substrate. The semiconductor device also includes the resistor metallic layer over the source region and the drain region of the semiconductor switch. The resistor metallic layer includes a first resistor with a first resistor metallic strip coupled between a first cross member and a second cross member of the resistor metallic layer.

Abstract: A metal-insulator-metal (MIM) capacitor is provided on a surface of an insulator layer that is located on a handle substrate. The MIM capacitor includes a first metal structure extending upwards from a first portion of the insulator layer, a second metal structure extending upwards from a second portion of the insulator layer, and an oxide fin located between the first and second metal structures, wherein the oxide fin directly contacts an entirety of a sidewall surface of the first metal structure and an entirety of a sidewall surface of the second metal structure, the oxide fin having a topmost surface that is coplanar with a topmost surface of both the first and second metal structures.

Abstract: A method of forming a semiconductor structure. The method comprises forming a high-k dielectric material, forming a continuous interfacial material over the high-k dielectric material, and forming a conductive material over the continuous interfacial material. Additional methods and semiconductor structures are also disclosed.

Abstract: A semiconductor chip includes a semiconductor layer having first and second opposing main surfaces. A plurality of MOSFET cells are at least partially formed in the semiconductor layer. A gate pad region is at least partially formed in the semiconductor layer and includes a gate pad contact and a first plurality of trenches extending from the first main surface. The first plurality of trenches are spaced apart from one another in a direction parallel to the first main surface by about 45 micrometers to about 60 micrometers. At least one gate feed region is at least partially formed in the semiconductor layer and includes a gate feed contact and a second plurality of trenches extending from the first main surface. The second plurality of trenches are spaced apart from one another in the direction parallel to the first main surface by about 45 micrometers to about 60 micrometers.

Abstract: A semiconductor device includes an active region formed in an upper layer portion of a semiconductor layer of a first conductivity type, and a plurality of electric field relaxation layers disposed from an edge of the active region toward the outside so as to surround the active region. The plurality of electric field relaxation layers include a plurality of first electric field relaxation layers and a plurality of second electric field relaxation layers alternately disposed adjacent to each other, the first electric field relaxation layer and the second electric field relaxation layer adjacent to each other forming a set. Impurities of a second conductivity type are implanted to the first electric field relaxation layers at a first surface density, widths of which becoming smaller as apart from the active region.

Abstract: Vertical power MOSFETs having a super junction are devices capable of having a lower on resistance than other vertical power MOSFETs. Although they have the advantage of high-speed switching due to rapid depletion of an N type drift region at the time of turn off in switching operation, they are likely to cause ringing. A vertical power MOSFET having a super junction structure provided by the present invention has, in the surface region of a first conductivity type drift region under a gate electrode, an undergate heavily doped N type region having a depth shallower than that of a second conductivity type body region and having a concentration higher than that of the first conductivity type drift region.

Abstract: A semiconductor device has a deep layer with a higher impurity concentration than that of a super junction structure. The deep layer is formed from a position deeper from a surface of a semiconductor layer by a predetermined depth, and comes in contact with a high impurity layer and also comes in contact with the super junction structure. The deep layer overlaps with a portion between a first end which is an outermost peripheral side of a portion that comes in contact with the high impurity layer in a front surface electrode and an end on an outer peripheral side in the high impurity layer when viewed from a substrate normal direction.

Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region and extending in a first direction parallel to a top surface of the substrate, a first source/drain region and a second source/drain region disposed in the active region at both sides of the gate structure, respectively, and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively. The distance between the gate structure and the first modified contact is smaller than the distance between the gate structure and the second modified contact.

Abstract: There is provided an electronic device and a method for its manufacture. The device comprises an elongate silicon nanowire less than 0.5 ?m in cross-sectional dimensions and having a hexagonal cross-sectional shape due to annealing-induced energy relaxation.

Abstract: A semiconductor device includes an n-type drain layer, an n-type base layer provided on the n-type drain layer, a p-type base layer and an n-type source layer partially formed in surface layer portions of the n-type base layer and the p-type base layer, respectively, a gate insulation film formed on a surface of the p-type base layer between the n-type source layer and the n-type base layer, a gate electrode formed on the gate insulation film facing the p-type base layer across the gate insulation film, a p-type column layer formed within the n-type base layer to extend from the p-type base layer toward the n-type drain layer, a depletion layer alleviation region arranged between the p-type column layer and the n-type drain layer and including first baryons converted to donors, a source electrode connected to the n-type source layer, and a drain electrode connected to the n-type drain layer.

Abstract: A nitride semiconductor device according to one embodiment of the present disclosure includes: a substrate; a first nitride semiconductor layer supported by the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a source-side nitride semiconductor regrowth layer which is located on a source-side recess region; a drain-side nitride semiconductor regrowth layer which is located on a drain-side recess region located apart from the source-side recess region; a first diffusion layer which is disposed in the first nitride semiconductor layer and contains Ge diffused from the source-side nitride semiconductor regrowth layer; and a second diffusion layer which is disposed in the first nitride semiconductor layer and contains Ge diffused from the drain-side nitride semiconductor regrowth layer.

Abstract: A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.

Abstract: FinFET transistor comprising at least: one fin that forms a channel, a source and a drain, comprising an alternating stack of first portions of silicon-rich SiGe and of second portions of a dielectric or semiconductor material, and third portions of germanium-rich SiGe arranged at least against lateral faces of the first portions, one gate that covers the channel, and wherein each one of the third portions comprises faces with a crystal orientation [111] covered by the gate.

Abstract: Body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a semiconductor structure comprises: a plurality of gates disposed on a semiconductor layer, each gate extending parallel to a y-axis in a coordinate space; a source region disposed between two of the plurality of gates; a plurality of body contacts disposed in each source region; and wherein a portion of each source region, adjacent to the gate, has a width extending parallel to the y-axis that is greater than the width of the source region parallel to the y-axis at a distance on an x-axis from the gate.

Abstract: A graphene layer is generated on a substrate. A plastic material is deposited on the graphene layer to at least partially cover the graphene layer. The substrate is separated into at least two substrate pieces.

Abstract: A substrate with a silicon carbide film includes a silicon substrate, a SiC film, and a mask 4. The SiC film has a film 31 including openings 35 on the silicon substrate and a film 32 provided on the upper side of the film 31. The mask 4 has a mask 41 provided on the upper side of the silicon substrate and including openings 45 and a mask 42 covering at least part of the mask 41 located in the openings 35 and the side surfaces of the openings 35 and including openings 46. The width W1 of the opening 45, the thickness T1 (?m) of the mask 41, and the thickness D (?m) of the film 31 at a position corresponding to the opening 45 satisfy the following relationships: T1<tan(54.6°)×W1, and D?tan(54.6°)×W1.

Abstract: A nitride semiconductor substrate is provided which is suitable for a high withstand voltage power device and prevents a warp and a crack from generating in a Si substrate when forming a thick nitride semiconductor layer on the substrate. A nitride semiconductor substrate 1 is prepared in such a manner that a buffer layer 3 and a semiconductor active layer 4 each comprising a group 13 nitride are stacked one by one on one principal plane of a Si single crystal substrate, the one principal plane has an offset angle of 0.1° to 1° or ?1° to ?0.1° with respect to a (111) plane, an average dopant concentration in a bulk is 1×1018 to 1×1021 cm?3, the Si single crystal substrate 2 has a SiO2 film on the back, and the total thickness of the buffer layer 3 and the semiconductor active layer 4 is 4 to 10 ?m.

Abstract: To provide is a p-type oxide, including an oxide, wherein the oxide includes: Cu; and an element M, which is selected from p-block elements, and which can be in an equilibrium state, as being present as an ion, wherein the equilibrium state is a state in which there are both a state where all of electrons of p-orbital of an outermost shell are lost, and a state where all of electrons of an outermost shell are lost, and wherein the p-type oxide is amorphous.

Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.

Abstract: A semiconductor device includes first to third semiconductor regions, first to fourth electrodes and a first insulating film. The first insulating film is provided between the third electrode and the first semiconductor region, between the third electrode and the second semiconductor region, between the third electrode and the third semiconductor region, and between the fourth electrode and the first semiconductor region. The first insulating film has a first insulating region, a second insulating region and a third insulating region. A first width in the first insulating region is different from a second width in the second insulating region. The first insulating region and the second insulating region are arranged in the direction. A third width of the third insulating region is constant along the second direction.

Abstract: A semiconductor device includes a gate electrode adjacent to a body region in a semiconductor substrate. The semiconductor device further includes a field electrode in a field plate trench in the main surface, the field plate trench having an extension length in a first direction parallel to a main surface. The extension length is less than the double of an extension length in a second direction that is perpendicular to the first direction parallel to the main surface. The extension length in the first direction is more than half of the extension length in the second direction. The field electrode is insulated from an adjacent drift zone by means of a field dielectric layer. A field plate material of the field electrode has a resistivity in a range from 105 to 10?1 Ohm·cm.

Abstract: A semiconductor layer of a reverse conducting insulated gate bipolar transistor is provided with a drift region of a first conductive type, a body region of a second conductive type that is disposed above the drift region, and a barrier region of the first conductive type that is disposed in the body region and electrically connects to the emitter electrode via a pillar member which extends from the one of main surfaces of the semiconductor layer. The barrier region is not contact with a side surface of the insulated trench gate.

Abstract: An embodiment high electron mobility transistor (HEMT) includes a gate electrode over a semiconductor substrate and a multi-layer semiconductor cap over the semiconductor substrate and adjacent the gate electrode. The multi-layer semiconductor cap includes a first semiconductor layer and a second semiconductor layer comprising a different material than the first semiconductor layer. The first semiconductor layer is laterally spaced apart from the gate electrode by a first spacing, and the second semiconductor layer is spaced apart from the gate electrode by a second spacing greater than the first spacing.

Abstract: An electrode structure of a transistor, and a pixel structure and a display apparatus comprising the electrode structure of the transistor are disclosed. The electrode structure of the transistor comprises a first electrode and a second electrode. The first electrode has at least two first portions and at least one second portion. The first portions are substantially parallel with each other and each has a first width. The second portion has a second width, and connects the substantially parallel first portions to define a space with an opening. The first width is substantially greater than the second width.

Abstract: A method for forming the semiconductor device structure is provided. The method includes forming a first metal layer over a substrate and forming a dielectric layer over the first metal layer. The method includes forming an antireflection layer over the dielectric layer, forming a hard mask layer over the antireflection layer and forming a patterned photoresist layer over the hard mask layer. The method includes etching a portion of the antireflection layer by performing a first etching process and etching through the antireflection layer and etching a portion of the dielectric layer by performing a second etching process. The method includes etching through the dielectric layer by performing a third etching process to form a via portion on the first metal layer. The via portion includes a first sidewall and a second sidewall, and the slope of the first sidewall is different from that of the second sidewall.

Abstract: A semiconductor device comprises: a substrate; a multilayer semiconductor layer located on the substrate; a source located on the multilayer semiconductor layer, the source including a first source portion inside an active region and a second source portion inside a passive region; a drain located on the multilayer semiconductor layer, the drain including a first drain portion inside the active region and a second drain region inside the passive region; a gate located on the multilayer semiconductor layer, the gate including a first gate portion inside the active region and a second gate portion inside the passive region, and the first gate portion being in a form of interdigital among the first source portion and the first drain portion; and a heat dissipating layer disposed at one or more of the first source portion, the first drain portion, the first gate portion, the second source portion, the second drain portion and the second gate portion.

Abstract: A semiconductor device includes a III-N layer, a plurality of parallel conductive fingers on the III-N layer, an insulator layer over the III-N layer, and a gate. The plurality of parallel conductive fingers includes a source and drain bus, a plurality of source fingers coupled to the source bus and extending from the source bus towards the drain bus to respective source finger ends, and a plurality of drain fingers coupled to the drain bus and extending from the drain bus towards the source bus to respective drain finger ends, the drain fingers being interdigitated between the source fingers. The gate comprises a plurality of straight and a plurality of connecting sections, each straight section between a source finger and adjacent drain finger, and the connecting sections each joining two adjacent straight sections and curving around a respective source or drain finger end.

Abstract: A device includes a III-N layer having an upper side and a lower side, the lower side being opposite the upper side, and at least one conductive contact on the upper side of the III-N layer, the conductive contact extending into the III-N layer. The conductive contact comprises a top side facing away from the lower side of the III-N layer, and a bottom side facing towards the lower side of the III-N layer. The bottom side includes a first end and a second end opposite the first end, a first side rising from the first end to an intermediate point closer to the top side than the first end, and a second side falling from the intermediate point to the second end further from the top side than the intermediate point.

Abstract: Semiconductor devices may include a gate pattern and a contact pattern disposed on an active region. The contact pattern may include a recessed portion near the gate pattern, and a rising portion away from the gate pattern. The gate pattern may include a gate insulating layer and a gate electrode disposed on the gate insulating layer. An upper surface of the recessed portion may be lower than an upper surface of the rising portion.

Abstract: The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has cuboid shaped memory gate and select gate covered upper surfaces by some spacers. Thus the memory gate and select gate are protected from silicide. The memory gate and select gate are defined self-aligned by the said spacers. The memory gate and select gate are formed by etching back corresponding conductive materials not covered by the spacers instead of recess processes. Thus the memory gate and select gate have planar upper surfaces and are well defined. The disclosed device and method is also capable of further scaling since photolithography processes are reduced.

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Abstract: A method used in fabrication of a recessed access device transistor gate has increased tolerance for mask misalignment. One embodiment of the invention comprises forming a vertical spacing layer over a semiconductor wafer, then etching the vertical spacing layer and the semiconductor wafer to form a recess in the wafer. A conductive transistor gate layer is then formed within the trench and over the vertical spacing layer. The transistor gate layer is etched, which exposes the vertical spacing layer. A spacer layer is formed over the etched conductive gate layer and over the vertical spacing layer, then the spacer layer and the vertical spacing layer are anisotropically etched. Subsequent to anisotropically etching the vertical spacing layer, a portion of the vertical spacing layer is interposed between the semiconductor wafer and the etched conductive transistor gate layer in a direction perpendicular to the plane of a major surface of the semiconductor wafer.

Abstract: A trench power MOSFET and a manufacturing method thereof are provided. The gate of the trench power MOSFET includes an upper doped region, a lower doped region and a middle region interposed therebetween. The upper has a conductive type reverse to that of the lower doped region, and the middle region is an intrinsic or lightly-doped region to form a PIN, P+/N? or N+/P? junction. As such, when the trench power MOSFET is in operation, a junction capacitance formed at the PIN, P+/N? or N+/P? junction is in series with the parasitic capacitance. Accordingly, the gate-to-drain effective capacitance may be reduced.