Abstract: A multi-sensor reader that includes a first sensor that has a sensing layer with a magnetization that changes according to an external magnetic field. The first sensor also includes first and second side biasing magnets having a magnetization substantially along a first direction. The first and second side biasing magnets align the magnetization of the sensing layer substantially along the first direction when the sensing layer is not substantially influenced by the external magnetic field. The multi-sensor reader further includes a second sensor that is stacked over the first sensor. The second sensor includes a reference layer that has a magnetization that is set substantially along a second direction.

Abstract: Systems and methods may include a motor and an output shaft apparatus. The output shaft apparatus may be configured to position a manufacturing component using the motor. The output shaft apparatus may move linearly along a longitudinal axis and/or rotationally about the longitudinal axis. The system may also include an engagement apparatus coupling the motor to the output shaft apparatus. The engagement apparatus may be configured in a linear configuration for linearly moving the output shaft apparatus or a rotational configuration for rotationally moving the output shaft apparatus.

Abstract: A tolerance ring includes: a base formed of a strip-like member substantially wound around into a shape; a plurality of projections provided along a winding direction of the base so as to protrude from an outer peripheral surface of the base in a radial direction of the base orthogonal to the outer peripheral surface; at least one extended portion extending from at least one of edge end portions in a width direction of the base, the width direction extending orthogonally to the winding direction and the radial direction. The extended portion extends from a region that includes at least one of a plurality of straight lines passing through respective contact points disposed between a section of the base and a circumscribed circle that circumscribes the section and extend in parallel with the width direction.

Abstract: Magnetic tape media according to one embodiment includes a plurality of servo tracks having physical characteristics of being written by an apparatus that monitors a lateral position of the magnetic tape media passing over a servo writing head during a servo track writing operation and writes servo marks to the magnetic tape media. A timing of the writing of each servo mark is based on the monitored position of the magnetic tape media.

Abstract: A data storage device includes a disk, a head, a microactuator, a coarse actuator, and a servo controller. The microactuator is configured to position the head relative to the disk. The coarse actuator is configured to position the microactuator relative to the disk. The servo controller is configured to generate an adjusted position error signal based on a position error signal and an estimated microactuator position signal. The servo controller is also configured to filter the adjusted position error signal with a shaping filter to generate a filtered position error signal, and to provide sliding mode control of the coarse actuator based at least partially on the filtered position error signal.

Abstract: According to one embodiment, there is provided a disk apparatus including a disk medium and a controller. The disk medium has a data area and a servo area. The controller obtains offset amount of a head from a target position along an cross-track direction based on a signal read from the data area by the head and performs first control to cause the head to approach the target position based on the offset amount.

Abstract: A magnetic recording medium 11 in which the outermost surface of a protective layer 3 on a lubricant layer 4 side contains carbon and nitrogen of 10 atomic % to 90 atomic %, the lubricant layer 4 is formed by being in contact with the outermost surface, and contains a compound A of Formula (1) and a compound B of Formula (2), a mass ratio (A/B) of the compound A with respect to the compound B is 0.2 to 0.3, the average molecular weights of the compounds A and B are 1,500 to 2,000 and 1,300 to 2,400, respectively, and the average film thickness is 0.5 nm to 2 nm. R1-C6H4OCH2CH(OH)CH2OCH2—R2-CH2OCH2CH(OH)CH2OH ??(1) (R1 is an alkoxy group having 1 to 4 carbon atoms. R2 is —CF2O(CF2CF2O)x(CF2O)yCF2—.

Abstract: A recording medium is a disc-shaped recording medium having a plurality of recording layers, in which a video stream is recorded on the plurality of recording layers. Part of the video stream is recorded up to a first recording position on a first recording layer of the plurality of recording layers. A remaining part of the video stream is recorded from a second recording position of a second recording layer adjacent to the first recording layer. The video stream is seamlessly connected between the first recording position and the second recording position, and a first distance between the first recording position and the second recording position in the radial direction of the recording medium is smaller than a second distance in the radial direction regarding which a jump is permitted in seamless connection within a same recording layer.

Abstract: An optical recording medium includes a plurality of information signal layers on which information signals are to be optically recorded. Among the plurality of information signal layers, the information signal layer closest to the light-receiving surface has a reflectance of more than 4%.

Abstract: Provided is a method of playing content stored in a storage device including requesting a conversion of the content to a content service server, receiving content key information and additional information for the conversion of the content from the content service server, and performing the conversion of the content based on the content key information and the additional information.

Abstract: According to one embodiment, first data is written into a first storage area with a shingled write recording scheme. A verification process is performed. The verification process includes reading second data and checking whether or not a read error has occurred. The second data is partial data of the first data written into the first storage area and is data written into a sector of the first track that is adjacent to a sector of the second track for which writing has completed.

Abstract: A recording medium records data including a digital stream where video information has been encoded. A recording region of the recording medium has a first recording region where reading is performed at a first read rate, and a second recording region where reading is performed at a second read rate that is faster than the first read rate. The data is classified into digital stream data having a real-time attribute and a data file having a non-real-time attribute in a file system of the data. The digital stream is not continuously recorded spanning a boundary between the first recording region and the second recording region. The data file is permitted to be continuously recorded spanning the boundary.

Abstract: A method for creating a content in an electronic device is provided. The method includes acquiring first media data acquired by at least one external electronic device, acquiring second media data on a basis of at least a part of the first media data, recognizing a feature of the second media data acquired by the at least one external electronic device, and creating the content on a basis of at least a part of the feature of the second media data.

Abstract: Intelligent synchronization of media or other material output from multiple media devices is contemplated. The intelligence synchronization may include instructing the media devices to coordinate playback in concert with a conductor whereby the conductor acts a focal point or reference for the non-conducting media devices. The non-conductor may transmit sync messaging having data or other information sufficient to facilitate coordinating operation of the non-conductors in a manner sufficient to synchronize output of the media.

Abstract: Disclosed is a control method of a display device including displaying a playback screen of video images, the playback screen of the video images showing one video image and a progress bar to visualize the progression of the video images, acquiring time information regarding respective bookmark images associated with the video images, the bookmark images respectively including the time information in the sequence of the video images and/or frame information regarding one video image corresponding to the time information, and displaying the bookmark images close to the progress bar at positions corresponding to the time information regarding the respective bookmark images. When a difference between first time information regarding a first bookmark image and second time information regarding a second bookmark image is a time threshold or less, the first and second bookmark images among the bookmark images are displayed as overlapping each other.

Abstract: The present disclosure relates to a method for intuitively reproducing video contents through data structuring and the apparatus thereof, more specifically, which searches section by section the video contents edited and provided based on section with free search, hash tag, and/or bookmark, produces a new video contents from the searched sections of the video contents, and therefore promotes consumption of the video contents by providing reproduced video contents. The video contents can be edited and played by using a user interface intuitively figuring out the structure of video contents.

Abstract: An storage carrier, having a body, the body having a substrate, a first frame board and a second frame board, with the first and second frame boards disposed at two opposite ends of the substrate, respectively, allowing a receiving space to be formed between the first frame board and the second frame board and adapted to receive and position an storage device. First positioning portions and second positioning portions are disposed on opposing inner sides of the first frame board and the second frame board and engaged with fixing holes of the storage device, respectively, with the first positioning portions being of higher structural rigidity than the second positioning portions, where a panel is coupled to another end of the substrate and positioned proximate to the first frame board and the second frame board, with a lid movably pivotally connected to the panel.

Abstract: A high-density storage assembly having a casing, an engaging mechanism, and a recording medium machine; the casing has a receiving space, with a plurality of fixing portions disposed on a substrate at a bottom of the casing, the engaging mechanism has at least two supporting portions arranged in a side by side in a transverse width direction, each having a coupling portion and a supporting plate, with the coupling portions connected to the fixing portions of the substrate of the casing, respectively, and extended upward and obliquely to form the supporting plates. A containing space for movably placing and positioning the recording medium machine is formed between an abutting leaf spring and a limit plate which are disposed on a lower surface of the supporting plate of one of two adjacent said supporting portions and an upper surface of the supporting plate of another said supporting portion, respectively.

Abstract: A system according to one embodiment includes a magnetic structure having a tunnel junction, and a controller and logic integrated with and/or executable by the controller. The logic is configured to reduce a local relative humidity in a vicinity of the tunnel junction by passing a current through the tunnel junction for at least a period of time that the tunnel junction would otherwise not have a current passing therethrough. A method according to one embodiment includes determining a relative humidity in an environment of a tunnel junction that is part of a magnetic structure and selecting an operating current from a range of allowable operating currents based on the determined relative humidity. The selected level of the current is high enough to heat the tunnel junction to a temperature which reduces a local relative humidity in a vicinity of the tunnel junction.

Abstract: Mitigating organic contaminants within a hard disk drive (HDD) may include introducing an organic solvent into the HDD to dissolve organic contaminants and, therefore, to inhibit such contaminants from fouling operation of the HDD device. Organic solvents such as toluene and/or hexane may be used to dissolve organic contaminants such as hydrocarbons and siloxanes.

Abstract: An apparatus such as heterogeneous device includes at least a first die and a second die. The apparatus further includes a first inductive element, a second inductive element, and switch control circuitry. The switch control circuitry is disposed in the first die. The switch control circuitry controls current through the first inductive element to produce a first voltage. The first voltage powers the first die. The second inductive element is coupled to the first inductive element. The second inductive element produces a second voltage to power the second die. The first die and second die can be fabricated in accordance with different technologies and in which the first die and second die withstand different maximum voltages. A magnitude of the first voltage can be greater than a magnitude of the second voltage.

Abstract: Provided herein is a power on reset circuit including a voltage dividing unit suitable for dividing an external power supply voltage according to a resistance ratio to output a divided voltage, a signal generating unit suitable for outputting a power on reset signal when the divided voltage has a set level or higher, and a resistance adjusting unit suitable for adjusting the resistance ratio of the voltage dividing unit in response to the power on reset signal.

Abstract: A circuit arrangement and method of reading the logic state of a memory cell in an array of semiconductor memory cells. A data memory cell selected from the array drives a current on a first data bit line in a read operation. A reference memory cell corresponding to the memory cell is activated after the memory cell is selected, the reference memory cell driving a current through the reference data line at a greater rate than that of the corresponding memory cell regardless of the logic state of the memory cell. A sense amplifier connected to the data line and a reference data line determines the logic state of the selected memory cell. A delay circuit activates the reference memory cell after the memory cell is selected and enables the sense amplifier after the reference memory cell has been activated.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: A system comprising a memory controller coupled to a memory device is described. The memory device is coupled to, and is external to, the memory controller. The memory device includes a storage array having dual configurability to support both synchronous and asynchronous modes of operation.

Abstract: A data input circuit may include a data latch unit suitable for latching input data as latch data in response to first and second latch signals; a data signal generation unit suitable for outputting first and second data signals corresponding to the latch data; a first drive unit suitable for pulling up or down a first input/output data line of an input/output data line pair in response to the first and second data signals; and a second drive unit suitable for pulling up or down a second input/output data line of the input/output data line pair in response to the first and second data signals, wherein the first and second drive units adjust pull-up levels of the first and second input/output data lines in response to a data input control signal.

Abstract: Various implementations described herein are directed to an integrated circuit for address decoding. The integrated circuit may include an input circuit configured to provide an encoded address via multiple address lines. The integrated circuit may include an address decoding circuit configured to directly translate the encoded address provided via the multiple address lines. The address decoding circuit may include multiple decoding blocks with each block having a first stage coupled to a second stage. The first stage of each block may include a first number of decoding transistors configured to decode first address bit values from the multiple address lines. The second stage of each block may include a second number of decoding transistors configured to decode second address data bit values from the multiple address lines. The integrated circuit may include an output circuit configured to provide a decoded address to a wordline driver circuit in memory.

Abstract: A memory cell and memories constructed from that memory cell are disclosed. A memory according to the present invention includes a ferroelectric capacitor, a charge source and a read circuit. The charge source receives a data value to be stored in the ferroelectric capacitor. The charge source converts the data value to a remanent charge to be stored in the ferroelectric capacitor and causes that remanent charge to be stored in the ferroelectric capacitor. The read circuit determines a charge stored in the ferroelectric capacitor. The data value has more than three distinct possible states, and the determined charge has more than three determined values. The memory also includes a reset circuit that causes the ferroelectric capacitor to enter a predetermined known reference state of polarization.

Abstract: Read-only (“RO”) data consisting of a physically unclonable function (“PUF”) pattern is written to a ferroelectric random-access memory (“FRAM”) memory array. The FRAM array is baked to imprint the PUF pattern with a selected average depth of imprint and a corresponding average read reliability. The average depth of imprint and corresponding average read reliability are determined during testing after baking The PUF pattern as read after baking is compared to the PUF pattern as written prior to baking Additional PUF pattern writing and baking cycles may be performed until the average depth of imprint and associated read reliability reach a first selected level. Integrated circuits determined to be over-imprinted by exceeding a second selected level may be rejected. The first and second levels of PUF pattern imprint are selected such as to produce FRAM arrays with a unique fingerprint for each individual FRAM array-containing integrated circuit.

Abstract: A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.

Abstract: Embedded refresh controllers included in memory devices and memory devices including the embedded refresh controllers are provided. The embedded refresh controllers may include a refresh counter and an address generator. The refresh counter may generate a counter refresh address signal in response to a counter refresh signal such that the counter refresh address signal may represent a sequentially changing address. The address generator may store information with respect to a hammer address that is accessed intensively and may generates a hammer refresh address signal in response to a hammer refresh signal such that the hammer refresh address signal may represent an address of a row that is physically adjacent to a row of the hammer address. Loss of cell data may be reduced and performance of the memory device may be enhanced by detecting the intensively-accessed hammer address and performing the refresh operation based on the detected hammer address efficiently.

Abstract: Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: A semiconductor memory device includes a memory cell configured to hold 4-bit data according to a threshold. A first bit of the 4-bit data is established by reading operations using a first to a third read levels. A second bit different from the first bit is established by reading operations using a fourth to a seventh read levels. A third bit different from the first and second bits is established by reading operations using an eighth to an eleventh read levels. A fourth bit different from the first to third bits is established by reading operations using a twelfth to a fifteenth read levels.

Abstract: A nonvolatile memory device includes a first resistive memory cell connected to a first word line, a second resistive memory cell connected to a second word line that is different from the first word line, a clamping unit connected between a sensing node and a reference current supplying unit connected to the second resistive memory cell to supply a reference current, and a sense amplifier connected to the sensing node to sense a level change of the sensing node, wherein when the first word line is enabled, the second word line is disabled.

Abstract: A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices.

Abstract: A memory-programming device includes a voltage generator, a resistive random-access memory, a current detector, and a controller. The voltage generator is configured to generate a program voltage. The resistive random-access memory receives the program voltage to generate a program current. The current detector detects the program current. The controller executes a program procedure. The program procedure includes: gradually ramping up the program voltage by the voltage generator and detecting the program current by the current detector; discovering the maximum of the program current to be a reference current; continuing to ramp up the program voltage by the voltage generator and determining whether the program current detected by the current detector is not less than the reference current; controlling the voltage generator to stop generating the program voltage when the program current is not less than the reference current.

Abstract: A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation to simultaneously increase threshold voltages of memory cells having different target levels to sub-levels lower than the different target levels, verifying the memory cells by using different verify voltages, respectively, performing a second program operation to divide the threshold voltages of the memory cells, and performing a third program operation to increase the threshold voltages of the memory cells to the different target levels, respectively.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: A method includes storing data in memory cells by programming the memory cells with respective values. The memory cells are read in multiple readout operations that each compares the programmed values to at least first and second read thresholds, while keeping the first read threshold fixed throughout the readout operations and perturbing only the second read threshold between the readout operations. A preferred value for the second read threshold is estimated based on the multiple readout operations.

Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.

Abstract: A data storage device may include: a nonvolatile memory device including a memory block; and a controller suitable for controlling the nonvolatile memory device to perform a string read operation on the memory block, and estimating a data storage rate of the memory block based on string read data acquired through the string read operation. When performing the string read operation, the nonvolatile memory device may apply the same read voltage to a plurality of word lines included in the memory block at the same time, acquire the string read data from the memory block according to the read voltage, and transmit the string read data to the controller.

Abstract: A clock signal generation device includes a variable voltage providing circuit, a fixed voltage providing circuit and a clock signal generating circuit. The variable voltage providing circuit provides a variable reference voltage based on a selection signal, a reference voltage and a temperature coefficient. The variable reference voltage is varied according to temperature. The fixed voltage providing circuit provides a fixed reference voltage that is determined according to the selection signal. The fixed reference voltage is a constant voltage. The clock signal generating circuit provides a clock signal based on the fixed reference voltage and the variable reference voltage. The performance of the clock signal generation device may be increased by providing the clock signal based on the variable reference voltage that is varied according to the temperature and based on the fixed reference voltage.

Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Abstract: A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.