Patents Issued in January 12, 2017
  • Publication number: 20170011959
    Abstract: Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions.
    Type: Application
    Filed: September 21, 2016
    Publication date: January 12, 2017
    Inventors: Roderick A. Hyde, Muriel Y. Ishikawa, Nathan P. Myhrvold, Clarence T. Tegreene, Charles Whitmer, Lowell L. Wood, JR.
  • Publication number: 20170011960
    Abstract: A method of forming a conductive plug is disclosed. A material layer having at least one opening is provided on a substrate. A first conductive layer is deposited in the opening, wherein the first conductive layer does not completely fill up the opening. A second conductive layer is deposited on the first conductive layer. A surface treatment is performed after the step of depositing the first conductive layer and before the step of depositing the second conductive layer, so that the first deposition rate of the second conductive layer at the lower portion of the opening is greater the second deposition rate of the second conductive layer at the upper portion of the opening. A void-free conductive plug can be easily formed with the method of the invention.
    Type: Application
    Filed: July 7, 2015
    Publication date: January 12, 2017
    Inventors: Meng-Tsung Ko, Yung-Tai Hung, Chin-Ta Su
  • Publication number: 20170011961
    Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.
    Type: Application
    Filed: August 15, 2016
    Publication date: January 12, 2017
    Inventors: YU-MING PENG, WEI-LUN HSU, CHU-CHUN HSU, HONG-SHENG KE, YU CHIA CHANG
  • Publication number: 20170011962
    Abstract: Device structures and fabrication methods for a backside contact to a final substrate. An electrically-conducting connection is formed that extends through a device layer of a silicon-on-insulator substrate and partially through a buried insulator layer of the silicon-on-insulator substrate. After the electrically-conducting connection is formed, a handle wafer of the silicon-on-insulator substrate is removed. After the handle wafer is removed, the buried insulator layer is partially removed to expose the electrically-conducting connection. After the buried insulator layer is partially removed, a final substrate is coupled to the buried insulator layer such that the electrically-conducting connection is coupled with the final substrate.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Inventors: JEFFREY P. GAMBINO, MARK D. JAFFE, STEVEN M. SHANK, ANTHONY K. STAMPER
  • Publication number: 20170011963
    Abstract: In one embodiment, a wafer includes a number of die areas each including a semiconductor device and dedicated to become a separate die. The die areas are disposed on a first face of the wafer and wherein adjacent die areas are distanced from one another. A first trench and a second trench are formed on the first face between adjacent die areas. The first trench and the second trench are spaced apart from one another by a ridge. A third trench is disposed above the ridge on a second face of the wafer.
    Type: Application
    Filed: July 6, 2015
    Publication date: January 12, 2017
    Inventors: Michaela Braun, Markus Menath
  • Publication number: 20170011964
    Abstract: In example implementations, a plurality of material layers and a plurality of etch stop layers are grown on a first substrate. Ions are implanted through at least one material layer of the plurality of material layers into an etch stop layer of the plurality of etch stop layers to create defects in the etch stop layer. A first material layer of the substrate is bonded to a second substrate. The etch stop layer is split to remove the first substrate from the second substrate. The first substrate is reused to bond another material layer of the plurality of material layers to a third substrate.
    Type: Application
    Filed: July 9, 2015
    Publication date: January 12, 2017
    Inventor: Di Liang
  • Publication number: 20170011965
    Abstract: There is provided a wafer processing method including a modified layer forming step. In the wafer processing method, the power of a pulse laser beam set in the modified layer forming step is set to power that forms modified layers and cracks in such a manner that a wafer is allowed to be divided into individual device chips before the thickness of the wafer reaches a finished thickness and, after the wafer is divided into the individual device chips, the time until the thickness of the wafer reaches the finished thickness is such a time that damage due to rubbing of the individual device chips against each other is not caused through grinding under a predetermined grinding condition set in a back surface grinding step.
    Type: Application
    Filed: July 5, 2016
    Publication date: January 12, 2017
    Inventor: Masaru Nakamura
  • Publication number: 20170011966
    Abstract: An interconnect structure is provided. The interconnect structure includes a substrate; and at least a first interconnect component having a first contact region and a second interconnect component having a second contact region. The interconnect structure also includes an interlayer dielectric layer formed on the semiconductor substrate at a same layer as the first interconnect component and the second interconnect component. Further, the interconnect structure includes an interconnect line layer electrically connecting the first contact region and the second contact region formed inside the interlayer dielectric layer.
    Type: Application
    Filed: July 12, 2016
    Publication date: January 12, 2017
    Inventors: YUNCHU YU, YIHUA SHEN
  • Publication number: 20170011967
    Abstract: A method of manufacturing a semiconductor device includes forming a first gate structure on a substrate, the first gate structure including a gate insulation layer, a gate electrode, and a hard mask sequentially stacked on the substrate, forming a preliminary spacer layer on sidewalls of the first gate structure and the substrate, the preliminary spacer layer including silicon nitride, implanting molecular ions into the preliminary spacer layer to form a spacer layer having a dielectric constant lower than a dielectric constant of the preliminary spacer layer, anisotropically etching the spacer layer to form spacers on the sidewalls of the first gate structure, and forming impurity regions at upper portions of the substrate adjacent to the first gate structure.
    Type: Application
    Filed: June 2, 2016
    Publication date: January 12, 2017
    Inventors: Jae-Hyun YEO, Jae-Suk KWON, Kwang-Woo LEE, Eun-Seong LEE
  • Publication number: 20170011968
    Abstract: A method of forming a semiconductor device includes receiving a substrate with a gate structure and forming a spacer layer over the substrate and the gate structure. The method further includes implanting carbon into the spacer layer at an angle tilted away from a first direction perpendicular to a top surface of the substrate, which increases etch resistance of the spacer layer on sidewalls of the gate structure. The method optionally includes implanting germanium into the spacer layer at the first direction, which decreases etch resistance of the spacer layer overlaying the gate structure and the substrate. The method further includes etching the spacer layer to expose the gate structure, resulting in a first portion of the spacer layer on the sidewalls of the gate structure. Due to increased etch resistance, the first portion of the spacer layer maintains its profile and thickness in subsequent fabrication processes.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Chun Hsiung TSAI, Jian-An KE
  • Publication number: 20170011969
    Abstract: A method for complementary metal oxide semiconductor (CMOS) fin integration includes recessing a fin structure buried in a dielectric fill to form a trench in the dielectric fill having a fin portion remaining at a bottom thereof. A new fin is epitaxially grown in the trench from the fin portion. The new fin included SiGe.
    Type: Application
    Filed: March 2, 2016
    Publication date: January 12, 2017
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Publication number: 20170011970
    Abstract: Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a first gate stack and a second gate stack. The method further includes forming sidewall spacers of equal thickness for both the first gate stack and the second gate stack by depositing a liner material over spacer material on sidewalls of the first gate stack and the second gate stack and within a space formed between the spacer material and source and drain regions of the first gate stack.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Inventors: Kangguo CHENG, Balasubramanian PRANATHARTHIHARAN, Soon-Cheon SEO
  • Publication number: 20170011971
    Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: John H. ZHANG, Chengyu NIU, Heng YANG
  • Publication number: 20170011972
    Abstract: A method for fabricating a three-dimensional integrated circuit device includes providing a first substrate having a first crystal orientation, forming at least one or more PMOS devices overlying the first substrate, and forming a first dielectric layer overlying the one or more PMOS devices. The method also includes providing a second substrate having a second crystal orientation, forming at least one or more NMOS devices overlying the second substrate, and forming a second dielectric layer overlying the one or more NMOS devices. The method further includes coupling the first dielectric layer to the second dielectric layer to form a hybrid structure including the first substrate overlying the second substrate.
    Type: Application
    Filed: March 18, 2014
    Publication date: January 12, 2017
    Applicant: MCube, Inc.
    Inventor: XIAO (CHARLES) YANG
  • Publication number: 20170011973
    Abstract: An x-ray inspection system includes a cabinet including an x-ray source, a sample support supporting a sample to be inspected, and an x-ray detector. The system further includes an air mover configured to force air into the cabinet through an air inlet in the cabinet above the sample support. The air mover and cabinet are configured to force air through the cabinet from the air inlet past the sample support to an air outlet in the cabinet below the sample support. The cabinet may be constructed to provide an x-ray shield. The x-ray inspection system can be used in a clean room environment to inspect items such as semiconductor wafers.
    Type: Application
    Filed: April 3, 2015
    Publication date: January 12, 2017
    Inventors: John Tingay, William T. Walker, Kate Stewart
  • Publication number: 20170011974
    Abstract: A substrate processing apparatus includes a substrate heating part, a power supply part and a control device. The control device measures a temperature of the substrate while controlling the substrate heating part such that the temperature of the substrate reaches a first control temperature higher than the target temperature using power supplied by the power supply part. The device measures the temperature of the substrate for a second control temperature lower than the target temperature, and selects the power ratio value providing the best temperature uniformity in the plane of the substrate and a temperature average value for the selected power ratio value from a result of the measurement. The device calculates a control temperature and the power ratio value for the target temperature based on the selected temperature average value and the power ratio value for each of the first and second control temperature.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takashi YOKAWA, Yasuhiro MIZUGUCHI, Makoto NOMURA, Kazuhito SAITO
  • Publication number: 20170011975
    Abstract: Embodiments include a method for controlled cooling of a heated stage. The method includes setting a stage coupling to a maximum value and heating the stage to a process temperature. The method includes providing a wafer on the heated stage in a process chamber. The method includes performing a process on the wafer and reducing the heating stage coupling to a predetermined minimum value and reducing the heated stage temperature. The method includes removing the wafer from the heated stage and the process chamber. The heated stage is covered with a plurality of pixels, each pixel of the plurality of pixels include a level of emissivity and are equipped with an emissivity control device configured to independently adjust the level of emissivity of the pixel. The heated stage coupling is configured to achieve a predetermined radiative coupling and control the wafer cooling rate and target temperature.
    Type: Application
    Filed: July 6, 2015
    Publication date: January 12, 2017
    Applicant: Tokyo Electron Limited
    Inventors: Mirko VUKOVIC, Ronald NASMAN
  • Publication number: 20170011976
    Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.
    Type: Application
    Filed: June 6, 2016
    Publication date: January 12, 2017
    Inventors: Myeong-soon PARK, Hyun-soo CHUNG, Chan-ho LEE
  • Publication number: 20170011977
    Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Inventors: Roland W. Gooch, Buu Q. Diep, Adam M. Kennedy, Stephen H. Black, Thomas A. Kocian
  • Publication number: 20170011978
    Abstract: The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 12, 2017
    Inventors: Kensuke MIKADO, Makoto SHIBUYA, Yasufumi MATSUOKA
  • Publication number: 20170011979
    Abstract: A novel semiconductor chip scale package encapsulates semiconductor chip on the device side, the non-device side, and the four edges with a mold compound. One process to fabricate such a semiconductor chip scale package involves forming trenches on the surface of a wafer around the chips and filling the trenches and covering the device side of the chips with a first mold compound. The wafer is subsequently thinned from the non-device side until the bottom portion of the trenches and the mold compound in the portion are also removed. The thinning process creates a plane that contains the back side of the chips and the mold compound exposed in the trench. This plane is subsequently covered with a second mold compound.
    Type: Application
    Filed: July 7, 2015
    Publication date: January 12, 2017
    Inventor: Duane Thomas Wilcoxen
  • Publication number: 20170011980
    Abstract: Disclosed is a semiconductor package including a lead frame with a chip pad and a lead, a semiconductor chip may be disposed on the lead frame, and an encapsulating layer may be disposed on the lead frame. The chip pad may include a center region and an edge region, and the lead may include a first region and a second region between the edge region of the chip pad and the first region of the lead. The encapsulating layer may cover the semiconductor chip and may extend between the chip pad and the lead to cover a bottom surface of the edge region of the chip pad and a bottom surface of the second region of the lead.
    Type: Application
    Filed: June 15, 2016
    Publication date: January 12, 2017
    Inventor: SOONBUM KIM
  • Publication number: 20170011981
    Abstract: A method of manufacturing a semiconductor device including providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing a conductive material on the pad within the opening.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Inventors: NAI-WEI LIU, JUI-PIN HUNG, JING-CHENG LIN
  • Publication number: 20170011982
    Abstract: An insulated chip comprising a semiconductor chip comprising at least one chip pad and an electrically insulating layer surrounding at least part of the semiconductor chip.
    Type: Application
    Filed: July 5, 2016
    Publication date: January 12, 2017
    Inventors: Horst THEUSS, Gottfried BEER, Juergen HOEGERL
  • Publication number: 20170011983
    Abstract: A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer covers the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.
    Type: Application
    Filed: July 9, 2015
    Publication date: January 12, 2017
    Inventors: Shou-Chian Hsu, Hiroyuki Fujishima
  • Publication number: 20170011984
    Abstract: A semiconductor integrated circuit, a radiation detection unit and a cooling unit are provided. Here, a radiation detection unit is provided near the semiconductor integrated circuit and detects a radiation quantity. The cooling unit cools the semiconductor integrated circuit according to the detected radiation quantity. In an environment where a radiation quantity is more, the generation of a malfunction can be restrained by cooling the semiconductor integrated circuit.
    Type: Application
    Filed: March 18, 2015
    Publication date: January 12, 2017
    Inventors: Daisuke MATSUURA, Yoshikatsu KURODA, Kei GEMBA
  • Publication number: 20170011985
    Abstract: A power electronics module having a base plate, a circuit carrier arranged on the base plate and a plurality of conductor tracks which are electrically insulated from the base plate. A power semiconductor component is arranged on one of the conductor tracks, and has a load connection element. In this case, the base plate has a substantially continuous first recess and the circuit carrier has a substantially continuous second recess, wherein the first and second recesses are arranged such that they are in alignment with one another. The load connection element has a first contact device which is in electrically conductive contact with a contact area of that side of the conductor track which is averted from the base plate, a second contact device for externally making contact with the circuit carrier, and a connecting section, which extends through the first and second recesses, between the first and second contact devices.
    Type: Application
    Filed: July 10, 2016
    Publication date: January 12, 2017
    Applicant: Semikron Elektronik GmbH & Co., KG
    Inventor: Christian WALTER
  • Publication number: 20170011986
    Abstract: A thermally conductive sheet of the present invention includes a thermosetting resin (A) and an inorganic filler material (B) that is dispersed in the thermosetting resin (A). In the thermally conductive sheet of the present invention, at a frequency of 1 kHz and at a temperature of 100° C. to 175° C., the maximum value of a dielectric loss factor of a cured product of the thermally conductive sheet is less than or equal to 0.030, and a change in relative dielectric constant of the cured product of the thermally conductive sheet is less than or equal to 0.10.
    Type: Application
    Filed: January 28, 2015
    Publication date: January 12, 2017
    Applicant: SUMITOMO BAKELITE CO., LTD.
    Inventors: Shunsuke Mochizuki, Kazuya Kitagawa, Yoji Shirato, Keita Nagahashi, Mika Tsuda, Satoshi Maji, Motomi Kurokawa, Kazuya Hirasawa
  • Publication number: 20170011987
    Abstract: Techniques are disclosed for forming a through-body-via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed techniques includes a polymer-based barrier layer and an electrically conductive seed layer formed by applying an electrically conductive ink directly to the barrier layer and then curing it in situ. In some embodiments, after curing, the resultant seed layer may be a thin, substantially conformal, electrically conductive metal film over which the TBV interconnect metal can be deposited. In some example cases, a polyimide, parylene, benzocyclobutene (BCB), and/or polypropylene carbonate (PPC) barrier layer and an ink containing copper (Cu) and/or silver (Ag), of nanoparticle-based or metal complex-based formulation, may be used in forming the TBV.
    Type: Application
    Filed: March 24, 2014
    Publication date: January 12, 2017
    Applicant: INTEL CORPORATION
    Inventor: KEVIN J. LEE
  • Publication number: 20170011988
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Application
    Filed: September 19, 2016
    Publication date: January 12, 2017
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20170011989
    Abstract: A lead frame includes a die paddle, a first lead, and a U-notch coupling the die paddle to the first lead. The U-notch extends from the die paddle and the first lead. The U-notch is configured to be removed to electrically isolate the first lead from the die paddle.
    Type: Application
    Filed: July 7, 2015
    Publication date: January 12, 2017
    Applicant: Infineon Technologies AG
    Inventors: Chip King Tan, Chan Lam Cha
  • Publication number: 20170011990
    Abstract: A semiconductor device includes a semiconductor chip and a plurality of leads. The leads include a first lead including a supporting portion for mounting the semiconductor chip, and a projecting portion which projects in a first direction from the supporting portion. A second lead extends in a second direction non-parallel with the first direction, and one or more third leads extends in the second direction, such that a line extending in a third direction perpendicular to the first direction passes through the second lead and the one or more third leads. The second lead includes a first portion and a second portion, the first portion having a width larger than the second portion, the first portion having one side parallel to the first direction, and the first portion located between the second portion and the first lead.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Applicant: ROHM CO., LTD.
    Inventor: Kazutaka SHIBATA
  • Publication number: 20170011991
    Abstract: An assembly comprises: at least one element that is capable of transmitting heat; at least one electrically insulating substrate comprising at least one film of a polymer that is a good thermal conductor and electrical insulator; at least one sintered metal joint that is in contact with the polymer film; a main radiator; the radiator being in direct contact, or in contact via a sintered joint, with the substrate.
    Type: Application
    Filed: July 8, 2016
    Publication date: January 12, 2017
    Inventor: Rabih KHAZAKA
  • Publication number: 20170011992
    Abstract: A substrate structure may include a base substrate, a plurality of unit substrate regions arranged on the base substrate in one or more rows and one or more columns and spaced apart from one another, and dummy substrate regions between the unit substrate regions. In a row direction or a column direction, a first pitch between central points of two adjacent unit substrate regions among the unit substrate regions and a second pitch between central points of two adjacent second unit substrate regions among the unit substrate regions are different from each other.
    Type: Application
    Filed: June 12, 2016
    Publication date: January 12, 2017
    Inventors: Yu-duk KIM, Kyong-soon CHO, Shle-ge LEE, Da-hee PARK
  • Publication number: 20170011993
    Abstract: Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer.
    Type: Application
    Filed: July 8, 2016
    Publication date: January 12, 2017
    Applicant: Broadcom Corporation
    Inventors: Sam Ziqun ZHAO, Sam Komarapalayam Karikalan, Edward Law, Rezaur Rahman Khan, Pieter Vorenkamp
  • Publication number: 20170011994
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
  • Publication number: 20170011995
    Abstract: Provided is a memory device including a plurality of bit line layers and a plurality of supporting structures. Each bit line layer extends in a plane defined by a first direction and a second direction and has a plurality of bit lines extending along the first direction. Each bit line has a plurality of wide parts and a plurality of narrow parts arranged alternately. The supporting structures are disposed between the wide parts of the corresponding bit lines of adjacent bit line layers. Besides, each narrow part of each bit line substantially has an ellipse-like shape in cross section, and each narrow part has a rounding ratio (RR) of greater than about 30%.
    Type: Application
    Filed: July 9, 2015
    Publication date: January 12, 2017
    Inventors: Yao-An Chung, Shih-Ping Hong
  • Publication number: 20170011996
    Abstract: A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.
    Type: Application
    Filed: July 5, 2016
    Publication date: January 12, 2017
    Inventors: Dohyun LEE, Youngwoo Park, Junghoon Park, Jaeduk Lee
  • Publication number: 20170011997
    Abstract: An embodiment includes a semiconductor structure comprising: a frontend portion including a device layer; a backend portion including a bottom metal layer, a top metal layer, and intermediate metal layers between the bottom and top metal layers; wherein (a) the top metal layer includes a first thickness that is orthogonal to the horizontal plane in which the top metal layer lies, the bottom metal layer includes a second thickness; and the intermediate metal layers includes a third thickness; and (b) the first thickness is greater than or equal to a sum of the second and third thicknesses. Other embodiments are described herein.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Inventors: Kevin J. Fischer, Christopher M. Pelto, Andrew W. Yeoh
  • Publication number: 20170011998
    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Applicant: INTEL CORPORATION
    Inventors: Boyan Boyanov, Kanwal Jit Singh, James Clarke, Alan Myers
  • Publication number: 20170011999
    Abstract: A semiconductor integrated circuit comprising: a first macro cell including a first power line in a first wiring layer; a second macro cell adjacent to the first macro cell, the second macro cell including a second power line in the first wiring layer; a first connection part in the first wiring layer, the first connection part electrically connecting the first power line with the second power line; and a third power line in a second wiring layer different from the first wiring layer, the third power line electrically connected to the first power line; wherein the second power line is electrically connected to the third power line through the first connection part.
    Type: Application
    Filed: June 8, 2016
    Publication date: January 12, 2017
    Inventor: Hun HEO
  • Publication number: 20170012000
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device including a fin structure, a first liner, a first insulating layer and a dummy gate structure. The fin structure is disposed on a substrate, where the fin structure has a trench. The first liner disposed in the trench. The first insulating layer disposed on the first liner. The dummy gate structure is disposed on the first insulating layer and disposed above the trench, where a bottom surface of the dummy gate and a top surface of the fin structure are on a same level.
    Type: Application
    Filed: September 3, 2015
    Publication date: January 12, 2017
    Inventors: I-Ming Tseng, Wen-An Liang, Chen-Ming Huang
  • Publication number: 20170012001
    Abstract: An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces.
    Type: Application
    Filed: July 11, 2016
    Publication date: January 12, 2017
    Inventors: Roy Gerald GORDON, Harish B. BHANDARI, Yeung AU, Youbo LIN
  • Publication number: 20170012002
    Abstract: A method of manufacturing a semiconductor device includes forming a separation trench into a first main surface of a semiconductor substrate and removing substrate material from a second main surface of the semiconductor substrate, so as to thin the substrate to a thickness of less than 100 ?m, the second main surface being opposite to the first main surface, so as to uncover a bottom side of the trench. Additional methods of manufacturing semiconductor devices are provided.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Inventors: Andreas Meiser, Markus Zundel, Martin Poelzl, Paul Ganitzer, Georg Ehrentraut
  • Publication number: 20170012003
    Abstract: There are provided a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate having a ground electrode formed on one surface thereof; at least one electronic component mounted on one surface of the substrate; an insulation layer including an exposed part exposing the ground electrode and a cover part covering the electronic component; and a shielding layer electrically connected to the ground electrode and covering the insulation layer.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Jin O YOO
  • Publication number: 20170012004
    Abstract: A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Inventors: Tomoyuki Yamada, Fumio Ushida, Shigetoshi Takeda, Tomoharu Awaya, Koji Banno, Takayoshi Minami
  • Publication number: 20170012005
    Abstract: A customized seal ring for a semiconductor device is formed of multiple seal ring cells that are selected and arranged to produce a seal ring design. The cells include first cells that are coupled to ground and second cells that are not coupled to ground. The second cells that are not coupled to ground, include a higher density of metal features in an inner portion thereof, than the first seal ring cells. Dummy metal vias and other metal features that may be present in the inner portion of the second seal ring cells are absent from the inner portion of the first seal ring cells that are coupled to ground. The seal ring design may include various arrangements, including alternating and repeating sequences of the different seal ring cells.
    Type: Application
    Filed: September 23, 2016
    Publication date: January 12, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wei CHEN, Chung-Ying YANG
  • Publication number: 20170012006
    Abstract: A high-resistance region is formed right under a seal ring by irradiating a semiconductor substrate with hydrogen ions or helium ions. The high-resistance region has a greater thickness than an isolation insulating layer formed as a shallow trench isolation (STI) region on the surface of the semiconductor substrate. As a result, a semiconductor integrated circuit including a seal ring achieving excellent high-frequency isolation is provided.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Yoshihiro OKUMURA, Yukio HIRAOKA, Shinichirou YONEYAMA, Miki YAMANAKA
  • Publication number: 20170012007
    Abstract: The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially encapsulates the die on the substrate. The seed layer is disposed on the package body and the first metal layer is disposed on the seed layer. The second metal layer is disposed on the first metal layer and the lateral surface of the substrate. The first metal layer and the second metal layer form an outer metal cap that provides thermal dissipation and electromagnetic interference (EMI) shielding.
    Type: Application
    Filed: September 21, 2016
    Publication date: January 12, 2017
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Sheng Chung, Kuo-Hsien Liao, Jin-Feng Yang, Chen-Yin Tai, Yung-I Yeh
  • Publication number: 20170012008
    Abstract: A high-frequency package has: a resin substrate; a high-frequency device mounted on a side of a first surface of the resin substrate; a ground surface conductor of a ground potential formed on a second surface of the resin substrate on an opposite side to the first surface; a transmission line for a high-frequency signal formed in an inner layer of the resin substrate; and a ground via of a ground potential formed within the resin substrate. A through hole is formed in the ground surface conductor. The ground via is placed between the transmission line and the through hole.
    Type: Application
    Filed: March 11, 2014
    Publication date: January 12, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventor: Kosuke YASOOKA