Abstract: An apparatus and methods are provided related to a surface of a reaction chamber assembly component. The surface may be roughened and/or anodized to provide desirable emissivity and porosity to help reduce burn-in time of a reaction chamber and to help reduce particles within the chamber. The apparatus and methods may be suitable for thin film deposition on semiconductor or other substrates.

Abstract: In some embodiments, a reactive curing process may be performed by exposing a semiconductor substrate in a process chamber to an ambient containing hydrogen peroxide, with the pressure in the process chamber at about 300 Torr or less. In some embodiments, the residence time of hydrogen peroxide molecules in the process chamber is about five minutes or less. The curing process temperature may be set at about 500° C. or less. The curing process may be applied to cure flowable dielectric materials and may provide highly uniform curing results, such as across a batch of semiconductor substrates cured in a batch process chamber.

Abstract: A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device design, and a nitride semiconductor element package with excellent voltage tolerance performance and reliability. On a substrate, a buffer layer including an AlN layer, a first AlGaN layer and a second AlGaN layer is formed. On the buffer layer, an element action layer including a GaN electron transfer layer and an AlGaN electron supply layer is formed. Thus, an HEMT element is constituted.

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a polycrystalline semiconductor material, and a polycrystalline dielectric disposed between and adjacent to the flexible substrate and the polycrystalline semiconductor material. The polycrystalline semiconductor material. The polycrystalline semiconductor material may include a polycrystalline III-V material, a polycrystalline II-VI material or polycrystalline germanium. Other embodiments may be disclosed and/or claimed.

Abstract: Method for fabricating a semiconductor structure. The semiconductor structure includes: a crystalline silicon substrate; a dielectric layer on the crystalline silicon substrate, the opening having an opening with sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; and a crystalline compound semiconductor layer thereby forming a processable crystalline compound semiconductor substrate, wherein the bottom of the opening is isolated from the crystalline compound material.

Abstract: A method for coating a substrate comprises producing a plasma ball using a microwave plasma source in the presence of a mixture of gases. The plasma ball has a diameter. The plasma ball is disposed at a first distance from the substrate and the substrate is maintained at a first temperature. The plasma ball is maintained at the first distance from the substrate, and a diamond coating is deposited on the substrate. The diamond coating has a thickness. Furthermore, the diamond coating has an optical transparency of greater than about 80%. The diamond coating can include nanocrystalline diamond. The microwave plasma source can have a frequency of about 915 MHz.

Abstract: The present disclosure relates to methods of making a transition metal dichalcogenide. The methods can include a step of depositing a transition metal onto a substrate to form an epitaxial transition metal layer. The methods can also include a step of depositing a chalcogen onto the epitaxial transition metal layer, and a step of reacting the chalcogen with the epitaxial transition metal layer to form a transition metal dichalcogenide. In some instances, the chalcogen is reacted with the epitaxial transition metal layer at a temperature of between about 300° C. and 600° C., between about 300° C. and 550° C., between about 300° C. and 500° C., between about 300° C. and 450° C., or between about 300° C. and 400° C.

Abstract: Provided is a method of forming a transition metal chalcogenide thin-film and the method includes preparing a first substrate having formed thereon a transition metal-containing precursor thin-film; displacing a second substrate separately with a constant distance from the first substrate by using a bridge unit while the second substrate is facing the first substrate, thereby securing a gas flowing path between the first substrate and the second substrate; heating the first and second substrates to a reaction temperature; and introducing a chalcogen-containing gas from an end of a reactor, such that the chalcogen-containing gas flows via the path.

Abstract: Embodiments of the present disclosure provide methods and apparatus for forming an epitaxial layer on a substrate. The substrate is exposed to pulsed laser radiation to clean, anneal, and/or activate the surface of the substrate. The substrate is then exposed to a deposition precursor in a self-limiting deposition process. The substrate may again be exposed to pulsed laser radiation, and then exposed to a second deposition precursor in a second self-limiting deposition process. The process may be repeated as desired to form an epitaxial layer of very high quality one atomic layer at a time.

Abstract: A manufacturing method of an epitaxial silicon wafer including a silicon wafer doped with boron and having a resistivity of 100 m?•cm or less and an epitaxial film formed on the silicon wafer includes: growing the epitaxial film on the silicon wafer; and applying a heat treatment on the epitaxial silicon wafer at a temperature of less than 900 degrees C.

Abstract: The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 3×108 pieces/cm2 or more and 1×1011 pieces/cm2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.

Abstract: A method provides a substrate having a top surface; forming a first semiconductor layer on the top surface, the first semiconductor layer having a first unit cell geometry; epitaxially depositing a layer of a metal-containing oxide on the first semiconductor layer, the layer ofmetal-containing oxide having a second unit cell geometry that differs from the first unit cell geometry; ion implanting the first semiconductor layer through the layer of metal-containing oxide; annealing the ion implanted first semiconductor layer; and forming a second semiconductor layer on the layer of metal-containing oxide, the second semiconductor layer having the first unit cell geometry. The layer of metal-containing oxide functions to inhibit propagation of misfit dislocations from the first semiconductor layer into the second semiconductor layer. A structure formed by the method is also disclosed.

Abstract: A heat treatment method for a semiconductor substrate is provided which improves the shapes of the sharp corners at the opening and the bottom of a trench without using flammable or explosive gas while improving productivity. The heat treatment is performed on a semiconductor substrate with a recess formed therein in a treatment chamber where gas is sealed at a pressure exceeding a pressure in a molecular flow region.

Abstract: Light is applied for preheating from a halogen lamp to a lower surface of a semiconductor wafer supported on a susceptor within a chamber. Thereafter, flash light is applied for flash heating from a flash lamp to an upper surface of the semiconductor wafer. Treatment gas supplied from a gas supply source is heated by a heater, and supplied into the chamber. A flow amount control valve is provided to increase a flow amount of the treatment gas supplied into the chamber. Contaminants discharged from a film of the semiconductor wafer during heat treatment are discharged to the outside of the chamber with a gas flow formed by a large amount of high-temperature treatment gas supplied into the chamber to reduce contamination inside the chamber.

Abstract: Light is applied for preheating from a halogen lamp to a lower surface of a semiconductor wafer supported on a susceptor within a chamber. Thereafter, flash light is applied for flash heating from a flash lamp to an upper surface of the semiconductor wafer. High-temperature treatment gas heated by a heater is supplied into the chamber to preheat a structure inside the chamber including a susceptor before heat treatment for an initial semiconductor wafer of a lot starts. By raising the temperature of the structure inside the chamber to a temperature substantially equivalent to a temperature of the structure during steady treatment, all semiconductor wafers constituting the lot are supportable on the susceptor maintained at a constant temperature without the necessity of dummy running. Accordingly, a temperature history is equalized for all the semiconductor wafers.

Abstract: A dopant is ion-injected to a semiconductor layer formed of a group III-V compound semiconductor containing nitrogen as a Group V element. A first activation annealing is performed on the semiconductor layer having the ion-injected dopant using a heat-treating furnace under temperature conditions of 700° C. to 900° C. After the first activation annealing is performed, a second activation annealing is performed by allowing a pulsed laser beam to be incident on the semiconductor layer. A dopant activation rate can be improved using the above-described method.

Abstract: A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.

Abstract: Provided is a method of manufacturing a semiconductor device, including: forming a stacked metal nitride film including a first metal nitride film and a second metal nitride film on a substrate by alternately performing steps (a) and (b) a plurality of times, wherein the step (a) includes alternately supplying: a first metal source containing a first halogen element and a metal element; and a nitrogen-containing source to the substrate a plurality of times to form the first metal nitride film, and the step (b) includes alternately supplying: a second metal source containing a second halogen element different from the first halogen element and the metal element; and the nitrogen-containing source to the substrate a plurality of times to form the second metal nitride film.

Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.

Abstract: A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a memory device are also disclosed.

Abstract: A grid comprising a first set of grid lines and a second set of grid lines is formed on a substrate using a first lithography process. At least one of the first set of grid lines and the second set of grid lines are selectively patterned to define a vertical device feature using a second lithography process.

Abstract: Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

Abstract: Methods of selectively etching an exposed portion of a patterned substrate relative to a second exposed portion are described. The etching process is a gas phase etch which uses an oxidizing precursor unexcited in any plasma prior to combination with plasma effluents formed in a remote plasma from an inert precursor. The plasma effluents may be combined with the oxidizing precursor in a plasma-free remote chamber region and/or in a plasma-free substrate processing region. The combination of the plasma effluents excites the oxidizing precursor and removes material from the exposed portion of the patterned substrate. The etch rate is controllable and selectable by adjusting the flow rate of the oxidizing precursor or the unexcited/plasma-excited flow rate ratio.

Abstract: A method of treating a semiconductor device is provided including the steps of loading the semiconductor device in a processing chamber, pressurizing the processing chamber by supplying a processing gas from a pressure chamber to the processing chamber, performing a thermal anneal of the semiconductor device in the processing chamber, and depressurizing the processing chamber by supplying the processing gas from the processing chamber to the pressure chamber.

Abstract: A method comprises providing a handle substrate having a front surface and a back surface; providing a layer of flexible semiconductor material having a front surface and a back surface and an at least partially sacrificial backing layer stack on the back surface of the layer of flexible semiconductor material; bonding the front surface of the layer of flexible semiconductor material to the front surface of the handle substrate; removing at least a portion of the at least partially sacrificial backing layer stack from the back surface of the layer of flexible semiconductor material; opening outgassing paths through the layer of flexible semiconductor material; and processing the layer of flexible semiconductor material.

Abstract: A metal sputtering or metal evaporating process is adopted in an initial fabricating step to fabricate a plurality of metal pads without having substantial dimensional change during fabrication. So that a bottom side of the plurality of metal pads is adapted to electrically couple to a nanochip in a later process. In addition, at least a first fan out circuitry is then built up on a top side of the plurality of metal pads. The bottom side of the redistribution layer is made adapted to electrically couple to a nanochip (Chip side), and the top side of the redistribution layer is made adapted to electrically couple to a printed circuit board side (PCB side) which has a plurality of top metal pads and is made adapted to electrically couple to a mother board in a later process.

Abstract: A semiconductor module radiator plate fabrication method includes soldering a plurality of insulating substrates of different shapes to a flat radiator plate, and forming a convex curve on an insulating substrate side of the radiator plate; obtaining a first concave curve by reversing the convex curve; setting a second concave curve on an insulating substrate side of a radiator plate after soldering, a bottom of the second concave curve being positioned under clearance between the plurality of insulating substrates; adding the first curve and the second curve to calculate a third concave curve on the insulating substrate side; and forming the third curve on a flat plate to form a radiator plate before soldering.

Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.

Abstract: An inkjet coating device comprises a support board and a sprinkler head. The support board is provided for placing the glass plate, the sprinkler head comprises a plurality of spray nozzles, wherein, the spray nozzles comprise an ink entrance port and an ink exit port, the ink is poured from the ink entrance port and poured onto the glass plate from the ink exit port, the internal diameter of the ink entrance port is larger than that of the ink exit port. The inkjet coating device comprises a trumpet-shaped spray nozzle which are closed together without gap, so as to not only increase the spraying capacity, but also make the trumpet-shaped ink drop more disperse in each coating interval belt uniformly to form an ink coating layers with uniform thickness.

Abstract: Embodiments of the invention relate to a reaction chamber and a plasma processing apparatus, which include a chamber body, a dielectric window and a power supply unit, the dielectric window is provided above and hermetically connected with the chamber body, and provided with plural sets of coils arranged at intervals in a vertical direction and wound around the dielectric window at an outer side thereof, and the power supply unit supplies power to the plural sets of coils. In the reaction chamber and the plasma processing apparatus, plasma can be distributed evenly and have an increased density in the reaction chamber, thereby improving uniformity and efficiency of the process; meanwhile, effective power for exciting plasma can be improved, and temperature rise and temperature gradient of the dielectric window during the process can be lowered, so as to prevent the dielectric window from cracking, and prolong service life of the dielectric window.

Abstract: A method for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride, includes: preparing a target object including the first region and the second region in a processing chamber of a plasma processing apparatus; and generating a plasma of a processing gas containing a fluorocarbon gas and a rare gas in the processing chamber. In the generating the plasma of the processing gas, a self-bias potential of a lower electrode on which the target object is mounted is greater than or equal to 4V and smaller than or equal to 350V and a flow rate of the rare gas in the processing gas is 250 to 5000 times of a flow rate of the fluorocarbon gas in the processing gas.

Abstract: When an edge of a wafer passes above a right sensor and a left sensor disposed in a conveyance route of the wafer to a substrate processing chamber, four edge intersecting points are acquired in a first wafer coordinate system, and a reference edge intersecting point set composed of two adjacent edge intersecting points is created from the four edge intersecting points. Between the two remaining edge intersecting points which do not constitute the reference edge intersecting point set, an edge intersecting point present within an area surrounded by two circles defined based on the two edge intersecting points constituting the reference edge intersecting point set is selected as an effective edge intersecting point, and a central position of a circle passing through the reference edge intersecting points and the effective edge intersecting point is acquired as a central position of the wafer.

Abstract: A substrate processing apparatus, including: a development part configured to develop a substrate on which an exposed resist film formed to form a pattern on a surface of the substrate; a heat plate configured to mount and heat the substrate on which the resist film formed on the heat plate before the development is performed; a distribution acquisition part configured to optically acquire a size distribution of a dimension of the pattern on the surface of the substrate, and a determination part configured to determine whether abnormality has occurred in a mounting state of the substrate on the heat plate, based on the size distribution of the dimension of the pattern.

Abstract: The present invention relates to an apparatus for removing fume which includes, a wafer cassette for stacking wafers; and an exhaust for exhausting the fume of the wafers stacked in the wafer cassette, wherein the wafer cassette includes stacking shelves provided at both sides for stacking wafers; and a front opening for incoming and outgoing of the wafers which are being stacked in the stacking shelf, wherein the stacking shelves include multiple inclined ramp portions which are slanted towards the wafers stacked in the stacking shelves as they travel towards the front opening, wherein a purge gas outlet is provided in the inclined ramp portion for supplying purge gas for the wafers stacked in the stacking shelves. According to the present invention, the residual process gases on wafers can be removed efficiently.

Abstract: An attitude changing apparatus which can change an attitude of a component with certainty without damaging the component. The component has a rectangular parallelepiped shape where a pair of rectangular end surfaces opposite to each other are connected to each other by four side surfaces. The component is stored in a cavity which penetrates between main surfaces of a conveyance member, the conveyance member is moved relative to a base, and the component is made to pass through an engaging groove formed on a reference surface of the base.

Abstract: A method comprises providing a handle substrate having a front surface and a back surface; providing a layer of flexible semiconductor material having a front surface and a back surface and an at least partially sacrificial backing layer stack on the back surface of the layer of flexible semiconductor material; bonding the front surface of the layer of flexible semiconductor material to the front surface of the handle substrate; removing at least a portion of the at least partially sacrificial backing layer stack from the back surface of the layer of flexible semiconductor material; opening outgassing paths through the layer of flexible semiconductor material; and processing the layer of flexible semiconductor material.

Abstract: A method comprises providing a handle substrate having a front surface and a back surface; providing a layer of flexible semiconductor material having a front surface and a back surface and an at least partially sacrificial backing layer stack on the back surface of the layer of flexible semiconductor material; bonding the front surface of the layer of flexible semiconductor material to the front surface of the handle substrate; removing at least a portion of the at least partially sacrificial backing layer stack from the back surface of the layer of flexible semiconductor material; opening outgassing paths through the layer of flexible semiconductor material; and processing the layer of flexible semiconductor material.

Abstract: A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a semiconductor substrate; forming an interfacial release layer on an exposed second surface of the semiconductor substrate; adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy; removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate; processing the semiconductor substrate; and removing the semiconductor substrate from the interfacial release layer to impart flexibility to the semiconductor substrate.

Abstract: A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a semiconductor substrate; forming an interfacial release layer on an exposed second surface of the semiconductor substrate; adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy; removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate; processing the semiconductor substrate; and removing the semiconductor substrate from the interfacial release layer to impart flexibility to the semiconductor substrate.

Abstract: A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars of the device wafer. The carrier wafer and the device wafer are fusion bonded together and back side processing effected on the device wafer. The device wafer may be released from the carrier wafer by one or more of mechanically cleaving, thermally cleaving, and mechanically separating. Methods of forming the semiconductor structure including the carrier wafer and the device wafer are disclosed.

Abstract: A protective film forming film 1 is provided in which the product of the breaking stress (MPa) measured at a measurement temperature of 0° C. and the breaking strain (unit: %) measured at a measurement temperature of 0° C. in at least one of the protective film forming film 1 and a protective film formed from the protective film forming film 1 is in a range of 1 MPa·% to 250 MPa·%. According to such a protective film forming film 1, the protective film forming film 1 or the protective film formed from the protective film forming film 1 can be suitably divided in an expanding process performed on a workpiece when the workpiece is divided to obtain a work product.

Abstract: A reaction system for processing semiconductor substrates is disclosed. In particular, the invention discloses an arrangement of a susceptor and a baseplate for when a substrate is placed into a reaction region. Magnets are embedded into the susceptor and the baseplate in order to create a gap between the two. As a result of the gap, the invention prevents an accumulation of gaseous materials that would exist in prior art systems as well as particle generation due to physical contact between parts.

Abstract: Apparatus for depositing a layer on a substrate in a process gas includes a chuck containing a first surface for supporting the substrate, a clamp for securing the substrate to the first surface of the chuck, an evacuatable enclosure enclosing the chuck and the clamp and control apparatus. The evacuatable enclosure includes an inlet, through which the processing gas is insertable into the enclosure. The control apparatus is adapted to move at least one of the chuck and the clamp relative to, and independently of, one another to adjust a spacing between the chuck and the clamp during a single deposition process whilst maintaining a flow of the processing gas and a pressure within the enclosure that is less than atmospheric pressure.

Abstract: An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.

Abstract: A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a semiconductor substrate; forming an interfacial release layer on an exposed second surface of the semiconductor substrate; adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy; removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate; processing the semiconductor substrate; and removing the semiconductor substrate from the interfacial release layer to impart flexibility to the semiconductor substrate.

Abstract: A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a semiconductor substrate; forming an interfacial release layer on an exposed second surface of the semiconductor substrate; adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy; removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate; processing the semiconductor substrate; and removing the semiconductor substrate from the interfacial release layer to impart flexibility to the semiconductor substrate.

Abstract: A method to transfer a layer of graphene from one substrate to another substrate is provided. The method includes providing a first layered structure including, from bottom to top, a copper foil, a layer of graphene, an adhesive layer and a carrier substrate. The copper foil is removed exposing a surface of the layer of graphene. Next, an oxide bonding enhancement dielectric layer is formed on the exposed surface of the layer of graphene. A second layered structure including a receiver substrate and a dielectric oxide layer is provided. Next, an exposed surface of the dielectric oxide layer is bonded to an exposed surface of the oxide bonding enhancement dielectric layer. The carrier substrate and the adhesive layer are removed exposing the layer of graphene.

Abstract: Devices and methods for producing an integrated circuit device, comprising a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion, are disclosed. The metallization layers comprise dielectric layers, preferably low-k dielectric layers, with metal conductors and/or interconnect structures incorporated within the dielectric layers. In an exemplary device, in at least some of the metallization layers of the BEOL stack, the elastic modulus of the dielectric material varies from one area of the layer to one or more other areas of the layer. In some implementations, a mask layer is applied on the BEOL stack or on one of the metallization layers during fabrication of the stack, the mask layer covering portions of the stack area and exposing other portions of the area. Then, a treatment is performed that changes the elastic modulus of the dielectric material in one or more of the metallization layers, but only in areas uncovered by the mask layer.

Abstract: Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer (54) covering a metal interconnect, a fluorine-silicon glass layer on the silicon-rich oxide layer, and a non-doped silicate glass layer on the fluorine-silicon glass layer; the thickness of the silicon-rich oxide layer (54) is 700 angstroms ±10%; the silicon-rich oxide layer having a greater thickness captures movable ions on an unsaturated bond, such that it is difficult for the movable ions to pass through the silicon-rich oxide layer, thus blocking the movable ions. The present invention has good performance in an integrity evaluation of the gate oxide layer, and avoids damage to the device caused by the aggregation of movable ions at an interface. Also provided are a silicon-on-insulator device and a method of manufacturing the intermetallic dielectric layer of the silicon-on-insulator device.

Abstract: A method of manufacturing a semiconductor device may include: (a) loading a substrate into a process chamber, the substrate having: a process surface provided with a first metal film containing at least a first metal element; (b) forming a second metal film on the substrate loaded in the process chamber by alternately supplying a metal compound and a first reactive gas reactive with the metal compound to the substrate a plurality of times; (c) alternately performing steps (c-1) and (c-2) a plurality of times wherein the step (c-1) includes: forming an amorphous third metal film on the second metal film, and the step (c-2) includes: forming a fourth metal film on the third metal film; and (d) forming an amorphous fifth metal film on the fourth metal film by supplying the metal compound mixed with the second reactive gas to the substrate.