Abstract: A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.

Abstract: A method for forming a semiconductor device includes forming a select gate over a substrate and forming a charge storage layer and a control gate over the select gate. The charge storage layer and control gate overlap a first sidewall of the select gate and the charge storage layer is between the select gate and the control gate. A protective spacer is formed, wherein the protective spacer has a first portion adjacent a first sidewall of the charge storage layer and on the substrate, and the protective spacer is thinned. After thinning the protective spacer, a sidewall spacer is formed over the protective spacer, wherein the sidewall spacer has a first portion on the substrate, and the first portion of the protective spacer is between the first sidewall of the control gate and the first portion of the sidewall spacer.

Abstract: A nonvolatile semiconductor memory device comprises: a memory cell region having a memory cell disposed therein; a peripheral region including a first stepped structure in which an end of a lower first layer is further from the memory cell region than is an end of an upper first layer; and a second stepped structure disposed on the first stepped structure, in which an end of a lower third layer is disposed further from the memory cell region than is an end of an upper third layer, a length in a second direction being shorter than a length in the second direction of the first layer or the second layer contacted by the second stepped structure, and a length in a third direction of the second stepped structure being shorter than a length in the third direction of the first layer or the second layer contacted by the second stepped structure.

Abstract: A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure.

Abstract: Methods to connect to back-plate (BP) or well contacts or diode junctions through a RMG electrode in FDSOI technology based devices and the resulting devices are disclosed. Embodiments include providing a polysilicon dummy gate electrode between spacers and extending over a BP, an active area of a transistor, and a shallow-trench-isolation (STI) region therebetween; providing an interlayer dielectric surrounding the spacers and polysilicon dummy gate electrode; removing the polysilicon dummy gate electrode creating a cavity between the spacers; forming a high-k dielectric layer and a work-function (WF) metal layer in the cavity; removing a section of the WF metal layer, high-k dielectric layer, and STI region exposing an upper surface of the BP; filling the cavity with a metal forming a replacement metal gate electrode; and planarizing the metal down to an upper surface of the spacers.

Abstract: A semiconductor-on-insulator (SOI) substrate is provided that includes a silicon or germanium handle substrate that is miscut from 2 degrees to 8 degrees towards the <111> crystallographic direction or the <100> crystallographic direction. The topmost semiconductor layer is removed from a portion of the SOI substrate, and then a trench having a high aspect ratio is formed within the insulator layer of the SOI substrate and along the <111> crystallographic direction or the <100> crystallographic direction. An III-V compound semiconductor pillar, which includes a lower portion that has a first defect density and an upper portion that has a second defect density that is less than the first defect density, is then formed in the trench.

Abstract: Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a defect-free portion of that layer to a handle wafer or other suitable substrate for integration. In accordance with some embodiments, transfer may result in the presence of island-like oxide structures on the handle wafer/substrate, each having a defect-free island of the lattice-mismatched semiconductor material embedded within its upper surface. Each defect-free semiconductor island may have one or more crystalline faceted edges and, with its accompanying oxide structure, may provide a planar surface for integration. In some cases, a layer of a second, different semiconductor material may be heteroepitaxially grown over the handle wafer/substrate to fill areas around the transferred islands. In some other cases, the handle wafer/substrate itself may be homoepitaxially grown to fill areas around the transferred islands.

Abstract: A thin film transistor (TFT) array substrate is provided that includes a TFT on a substrate. The TFT can include an active layer, gate electrode, source electrode, drain electrode, first insulating layer between the active layer and the gate electrode, and second insulating layer between the gate electrode and the source and drain electrodes. A pixel electrode is disposed on the first and second insulating layers. A capacitor including a lower electrode is disposed on a same layer as the gate electrode and an upper electrode. A third insulating layer directly between the second insulating layer and the pixel electrode and between the lower electrode and the upper electrode. A fourth insulating layer covers the source electrode, the drain electrode, and the upper electrode, and exposes the pixel electrode and can further expose a pad electrode.

Abstract: According to one embodiment, a wiring substrate includes a pad group of a first pad to supply a power source voltage of low level, a second pad to supply a power source voltage of high level, and a third pad to supply a necessary signal for displaying an image, a common line, a first connection line to connect the first pad with the common line, a second connection line to connect the second pad with the common line, and a third connection line to connect the third pad with the common line, wherein the first connection line and the second connection line are formed of polysilicon in which no impurity is doped, and the third connection line and the common line are formed of polysilicon in which an impurity is doped.

Abstract: A thin film transistor array panel includes: a first gate line extending in a first direction; a second gate line extending in the first direction; a data line extending in a different second direction; a first common signal distribution line including a plurality of first branches connected to each other, wherein the first branches extend in the second direction and intersect under or over with the first gate line and the second gate line. The first branches are connected to receive an electrostatic offset voltage of polarity opposite to that of data line voltages supplied on the data line. A column of pixel-electrodes are sandwiched between the data line and one of the first branches.

Abstract: An array substrate and a method for fabricating the same are disclosed. The method includes steps of providing a substrate (20), a first metal layer including patterns of gate electrodes (21, 24) of a first and second TFTs, an active layer (27) and a gate insulation layer (28) are formed on the substrate; forming an etch stop layer film and a photoresist sequentially on the substrate (20), and allowing the photoresist to form a first, second and third regions through gray-scale exposing and developing; forming a pattern of an etch stop layer (29), a connection via hole (30), and a contact via hole (31) respectively in the first, second and third regions through a patterning process; and forming source electrodes and drain electrodes (22, 23,25, 26) of the first and second TFTs. Photoresist of different thicknesses are disposed according to etch depths, thereby avoiding the over-etch of relatively shallow via holes.

Abstract: A thin film transistor array panel includes a substrate, an insulation layer, a first semiconductor, and a second semiconductor. The insulation layer is disposed on the substrate and includes a stepped portion. The first semiconductor is disposed on the insulation layer. The second semiconductor is disposed on the insulation layer and includes a semiconductor material different than the first semiconductor. The stepped portion is spaced apart from an edge of the first semiconductor.

Abstract: Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix pattern. Each of the pixels has a photoelectric conversion portion configured to photoelectrically convert light incident from a rear surface side of a semiconductor substrate. The plurality of on-chip lenses are arranged for every other pixel. The on-chip lenses are larger in size than the pixels. Each of color filters at the pixels where the on-chip lenses are present has a cross-sectional shape whose upper side close to the on-chip lens is the same in width as the on-chip lens and whose lower side close to the photoelectric conversion portion is shorter than the upper side.

Abstract: To provide an imaging device capable of obtaining high-quality imaging data. The imaging device includes a first circuit and a second circuit. The first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a third capacitor. The second circuit includes a seventh transistor. The imaging device can compensate variation in electrical characteristics of an amplifier transistor included in the first circuit.

Abstract: A solid-state image sensor is provided. The sensor includes a substrate having a light-receiving surface. The substrate includes a charge accumulation portion that forms part of a photoelectric conversion element, a charge holding portion arranged at a position deeper than the charge accumulation portion from the light-receiving surface, and a first transfer portion configured to transfer charges generated by the photoelectric conversion element to the charge holding portion along a depth direction of the substrate. A distance between the charge holding portion and the light-receiving surface is not less than 4 ?m.

Abstract: A backside illuminated (BSI) image sensor device includes: a first substrate including a front side and a back side; a second substrate bonded with the first substrate on the front side; and a blocking layer between the first substrate and the second substrate. The first substrate includes an image sensor, and the image sensor is configured to collect incident light entering from the back side. The second substrate includes a circuit coupled with the image sensor. The blocking layer is configured to block radiation induced by the circuit.

Abstract: A method for producing a semiconductor light receiving device includes the steps of growing a stacked semiconductor layer on a principal surface of a substrate, the stacked semiconductor layer including a light-receiving layer having a super-lattice structure, the super-lattice structure including a first semiconductor layer and a second semiconductor layer that are stacked alternately; forming a mask on the stacked semiconductor layer; forming a mesa structure on the substrate by etching the stacked semiconductor layer using the mask so as to form a substrate product, the mesa structure having a side surface exposed in an atmosphere; forming a fluorinated amorphous layer on the side surface of the mesa structure by exposing the substrate product in fluorine plasma; and after the step of forming the fluorinated amorphous layer, forming a passivation film containing an oxide on the side surface of the mesa structure.

Abstract: A quantum dot light emitting diode, including a first electrode and a second electrode, a quantum dot light emitting layer disposed between the two electrodes, including at least a red quantum dot, a green quantum dot and a blue quantum dot, and a black matrix at least disposed among the red quantum dot, the green quantum dot and the blue quantum dot; one of the first electrode and the second electrode that is located on a light exiting side is at least a transparent electrode. With the quantum dot light emitting diode, a full-color display can be realized, and the aperture ratio of pixels can be effectively enhanced. There are further disclosed a manufacturing method of the quantum dot light emitting diode and a display device.

Abstract: A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, a patterned sacrificial layer is utilized to form a self-aligned metallization stack and is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes.

Abstract: Systems and methods of integration of resistive memory elements with logic elements in advanced nodes with improved mechanical stability and reduced parasitic capacitance include a resistive memory element and a logic element formed in a common integration layer extending between a bottom cap layer and a top cap layer. At least a first intermetal dielectric (IMD) layer of high-K value is formed in the common integration layer and surrounding at least the resistive memory element, to provide high rigidity and mechanical stability. A second IMD layer of low-K value to reduce parasitic capacitance of the logic element is formed in either the common integration layer, a top layer above the top cap layer or an intermediate layer in between the top and bottom cap layers. Air gaps may be formed in one or more IMD layers to further reduce capacitance.

Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.

Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

Abstract: Image sensors, and electronic devices including the same, include a first photo-sensing device sensing light in a full visible to near infrared ray region, a second photo-sensing device sensing light in a blue wavelength region, a third photo-sensing device sensing light in a red wavelength region, and a fourth photo-sensing device sensing light in a green wavelength region. At least one of the first photo-sensing device, the second photo-sensing device, the third photo-sensing device, and the fourth photo-sensing device includes a pair of light-transmitting electrodes facing each other, and a photoactive layer between the light-transmitting electrodes. The photoactive layer includes an organic light-absorbing material.

Abstract: An image sensor including a semiconductor substrate integrated with a plurality of photo-sensing devices and a nanopattern layer on the semiconductor substrate, the nanopattern layer having a plurality of nanopatterns, wherein a single nanopattern of the plurality of nanopatterns corresponds to a single photo-sensing device in the plurality of photo-sensing devices.

Abstract: A display substrate and a display device applying the same are provided. The display substrate includes a base plate and a display structure. The display structure is disposed on the base plate and includes first region. The first region includes a first sub-pixel, a second sub-pixel and two third sub-pixels. One of the two third sub-pixels has a first light emitting region having a first end point and a second end point. The other one of the two third sub-pixels has a second light emitting region having a third end point and a fourth end point. The first sub-pixel has a third light emitting region and the second sub-pixel has a fourth light emitting region. The third light emitting region and the fourth light emitting region are inside a quadrilateral region enclosed by the first, second, third and fourth end points.

Abstract: An organic light emitting diode (OLED) display device includes: a first substrate comprising red, green, and blue pixel areas; a first electrode on the first substrate; red, green, and blue organic light emitting layers on the first electrode at the red, green, and blue pixel areas, respectively; a second electrode on the red, green, and blue organic light emitting layers; a capping layer on the second electrode, and having a greater thickness at the red and green pixel areas than a thickness at the blue pixel area; a thin film encapsulation layer on the capping layer; and a red color filter on the thin film encapsulation layer at the red pixel area.

Abstract: A method and apparatus for an OLED display system is presented. A substrate is provided and a display is provided on the substrate. At least one sensor is also provided on the substrate. A barrier is provided on the substrate between the display and said the least one sensor, the barrier blocking emissions from the display from being sensed by the at least one sensor.

Abstract: OLED display that includes: a substrate; a plurality of thin film transistors formed on the substrate; a plurality of first electrodes respectively connected to the thin film transistors; a pixel definition layer formed on the substrate and having a first opening, a second opening, and a third opening respectively exposing first, second, and third first electrodes of the plurality of first electrodes; an emission layer formed at the first opening, the second opening, and the third opening; and a second electrode formed on the emission layer, wherein the first opening has a first pair of boundary lines facing each other and a second pair of boundary lines facing each other, and the first pair of boundary lines overlap boundary lines of a pair of boundary lines of the first first electrode or are positioned outside the boundary lines of the pair of boundary lines of the first first electrode.

Abstract: Disclosed is an organic white light emitting display apparatus. The organic white light emitting device includes a first substrate including a first sub-pixel area, a second sub-pixel area, a third sub-pixel area, and an organic light emitting device (OLED) that includes a first electrode, a second electrode, and an organic white light emitting layer interposed between the first and second electrodes, and emits whit light for respective sub-pixel areas, a second substrate including first, second, and third color filters of different colors formed on positions corresponding to the respective sub-pixel areas, the second substrate being arranged to face the first substrate, and a partition wall that is extended to an area between neighboring color filters among the color filters and partitions the sub-pixel areas, the partition wall being formed on the first substrate.

Abstract: A flexible display includes: a first flexible substrate; an intermediate barrier layer positioned on the first flexible substrate and comprising silicon oxide; an adhesive layer positioned on the intermediate barrier layer and comprising at least one of amorphous silicon on which a P-type or N-type conductive impurity is doped, or hydrogenated amorphous silicon; a second flexible substrate positioned on the adhesive layer; a first barrier layer positioned on the second flexible substrate and comprising silicon oxide; a second barrier layer positioned on the first barrier layer and comprising silicon nitride; a buffer layer positioned on the second barrier layer and comprising silicon oxide; a thin film transistor positioned on the buffer layer; and an organic light emitting element connected to the thin film transistor.

Abstract: An organic light-emitting display apparatus including a substrate; a thin-film transistor (TFT) arranged on the substrate; a black matrix located between the substrate and the TFT; a pixel electrode, which is located between the substrate and the TFT and having edge portions covered by the black matrix; an insulation layer, which covers the TFT and opens the top surface of the pixel electrode; an organic emission layer, which is arranged on the pixel electrode; and a counter electrode, which is arranged on the organic emission layer.

Abstract: The invention relates to a matrix display screen which includes, in sequence: a mounting (50); at least one first metal portion (156); a stack of layers (52, 72, 86, 104) including transistors (TFT1, TFT2); and organic light-emitting diodes (32).

Abstract: A display unit includes: a display layer including a pixel electrode; a semiconductor layer provided in a layer below the display layer, the semiconductor layer including a wiring layer that includes a material removable by an etchant by which the pixel electrode is also removable; and a terminal section configured to electrically connect the semiconductor layer to an external circuit, the terminal section including a first electrically-conductive layer made of a material same as a material of the wiring layer.

Abstract: A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer.

Abstract: Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor. A local interconnect (LI) layer is deposited over the top surface of the first dielectric layer and the first contact, a ferro stack including a bottom electrode, a top electrode and ferroelectric layer there between deposited over the LI layer, and the ferro stack and the LI layer patterned to form a ferroelectric capacitor and a LI through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor.

Abstract: Embodiments disclose a method of fabrication and a semiconductor structure comprising a Metal-insulator-metal (MIM) capacitor. The method of fabrication includes depositing a first conductive material on a semiconductor substrate. A first dielectric material is deposited on the first conductive material. A second conductive material is deposited on the first dielectric material. The top plate is formed by etching the second conductive material. The bottom plate is formed by etching a portion of the first conductive material. At least one opening is formed in the first dielectric layer down to the first conductive material.

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

Abstract: According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby reducing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.

Abstract: A semiconductor device of the present invention includes a semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode being in contact with a surface of the semiconductor layer. The semiconductor layer includes a drift layer that forms the surface of the semiconductor layer and a high-resistance layer that is formed on a surface layer portion of the drift layer and that has higher resistance than the drift layer. The high-resistance layer is formed by implanting impurity ions from the surface of the semiconductor layer and then undergoing annealing treatment at less than 1500° C.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first conductivity type. An epitaxial layer having the first conductivity type is disposed on the substrate, and a trench is formed in the epitaxial layer. A polysilicon layer having the first conductivity type fills the trench, and a first doping region having a second conductivity type that is different from the first conductivity type is disposed in the epitaxial layer and on sidewalls of the trench. A method for forming the semiconductor device is also provided.

Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.

Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

Abstract: Embodiments of the present invention provide an improved shallow trench isolation structure and method of fabrication. The shallow trench isolation cavity includes an upper region having a sigma cavity shape, and a lower region having a substantially rectangular cross-section. The lower region is filled with a first material having good gap fill properties. The sigma cavity is filled with a second material having good stress-inducing properties. In some embodiments, source/drain stressor cavities may be eliminated, with the stress provided by the shallow trench isolation structure. In other embodiments, the stress from the shallow trench isolation structure may be used to complement or counteract stress from a source/drain stressor region of an adjacent transistor. This enables precise tuning of channel stress to achieve a desired carrier mobility for a transistor.

Abstract: A patterned stack of a first silicon-germanium alloy nanowire, a second silicon-germanium alloy nanowire, and a silicon-containing nanowire is formed on a substrate. After formation of a first dielectric isolation layer around the patterned stack, a disposable gate structure can be formed. End portions of the second silicon-germanium alloy nanowire are removed to form first cavities underlying end portions of the silicon-containing nanowire. Dielectric nanowires are formed in cavities concurrently with formation of a gate spacer. After recessing the first dielectric isolation layer, a second cavity is formed by removing the first silicon-germanium alloy nanowire. The second cavity is filled with a second dielectric isolation layer, and raised active regions can be formed by a selective epitaxy process. After formation of a planarization dielectric layer, the disposable gate structure and the remaining portion of the second silicon-germanium alloy nanowire with a replacement gate structure.

Abstract: A method for forming a semiconductor device includes providing a semiconductor structure, which includes a semiconductor substrate and a first mask layer on the substrate. The first mask layer is used to form a plurality of first trenches that extends into the substrate and extends laterally in a first direction and do not intersect each other. The first trenches are then filled with a fill material. Next, a second mask layer is formed on the semiconductor structure filled with the fill material. The second mask layer is then used to form a second plurality of trenches in the semiconductor substrate that extend laterally in a second direction and do not intersect each other. Each of the second trenches intersects at least one of the first plurality of trenches. Next, the fill material is removed to form a plurality of vertical pillars defined by intersecting first trenches and second trenches.

Abstract: A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

Abstract: An embodiment semiconductor device includes a fin extending upwards from a semiconductor substrate. The fin includes an anti-punch through (APT) layer having APT dopants and a channel region over the APT layer. The channel region is substantially free of APT dopants. The semiconductor device further includes a conductive gate stack on a sidewall and a top surface of the channel region.