Patents Issued in January 24, 2017
  • Patent number: 9553214
    Abstract: A positioning method of a photoelectric conversion device (an imaging device) includes irradiating an optical member with light and receiving light which passes through an opening of a light shielding member and the optical member with the photoelectric conversion device. The photoelectric conversion device is moved in a direction orthogonal to an optical axis of the optical member and a first position at which the photoelectric conversion device detects a side of an opening and a second position at which the photoelectric conversion device detects another side opposing the side are acquired. A position of the photoelectric conversion device at which a center of the opening and a center position of the photoelectric conversion device are aligned based on the first position and the second position is determined. The photoelectric conversion device is fixed at the determined position.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: January 24, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Mitsutaka Ide, Hideyuki Kataoka, Hiroyuki Kobayashi
  • Patent number: 9553215
    Abstract: The invention relates to a method and a device for recognizing faults in a photovoltaic system (1). A first output voltage (U0, UMPP) of the system (1) and/or a first parameter derived from the output voltage (U0, UMPP) is determined at a first point in time in a first operating state of the photovoltaic system (1). At a second point in time in a second operating state comparable to the first operating state, a second output voltage (U0, UMPP) and/or a second parameter of the system (1) derived from the output voltage (U0, UMPP) is determined. Finally, a deviation between the first and the second output voltage (U0, UMPP) and/or between the first and the second parameter is identified and a fault notification is output if the deviation exceeds a predeterminable threshold.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: January 24, 2017
    Assignee: Fronius International GmbH
    Inventors: Michael Ammer, Thomas Muehlberger, Roland Proetsch, Yvonne Zwirchmayr
  • Patent number: 9553216
    Abstract: A method of operating an avalanche photodiode includes providing an avalanche photodiode having a multiplication region capable of amplifying an electric current when subject to an electric field. The multiplication region, in operation, has a first ionization rate for electrons and a second, different, ionization rate for holes. The method also includes applying the electric field to the multiplication region, receiving a current output from the multiplication region, and varying the electric field in time, whereby a portion of the current output is suppressed.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: January 24, 2017
    Assignee: Voxtel, Inc.
    Inventors: George Williams, Andrew S. Huntington
  • Patent number: 9553217
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a passivation film on a substrate including a first element region, a second element region adjacent to the first element region in a first direction, a third element region adjacent to the first region in a second direction, and a first scribe region extending to the first direction between the first element region and the third element region, forming a first trench in the passivation film between the first scribe region and the first element region, forming a second trench in the passivation film between the third element region and the first scribe region, and forming a film on the passivation film where the trenches have been formed by coating. The each of trenches is formed continuously along the first and the second element region.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: January 24, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masao Ishioka, Nobutaka Ukigaya
  • Patent number: 9553218
    Abstract: A high transmittance thin film solar panel includes a transparent substrate, a front electrode layer, a light absorption layer and a rear electrode layer. The light absorption layer is formed with opening patterns with the same width at positions aligned correspondingly to form at least one first opening trench, a plurality of second opening trenches with continuously and periodically sinusoidal-wave shape, and a plurality of third opening trenches parallel to, interlace with or superpose the second opening trenches, and extend in a direction orthogonal to the direction of the first opening trench. The high transmittance thin film solar panel of the present invention is mainly used for green buildings. The opening trenches of the high transmittance thin film solar panel are formed in a manner of curve shape by an oscillating laser head, and can enhance the transmittance by more than about 3% in comparison with the conventional one.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: January 24, 2017
    Assignee: NEXPOWER TECHNOLOGY CORPORATION
    Inventors: Chih-Jen Mao, Jia-Shian Lin, Sheng-Jui Lee, Chi-Shan Huang, Chih-Wei Chang
  • Patent number: 9553219
    Abstract: A glass unit includes an energy collecting layer attached to a light directing device for collecting a light energy from the light directing device, and an energy converting layer electrically coupled to the energy collecting layer for converting the light energy into an electric energy, and the light directing device includes a number of nanometer particles to direct the light energy toward the energy collecting layer. The light directing device includes one or more glass layers, and a light collecting panel attached to the glass layer with a bonding layer and made of polymer materials which are mixed with the nanometer particles to form the light collecting panel.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: January 24, 2017
    Assignee: APA Solutions Holdings, LLC
    Inventor: Aaron Mei
  • Patent number: 9553220
    Abstract: A field shaping multi-well avalanche detector and method for fabrication thereof are disclosed. The field shaping multi-well avalanche detector provides stable avalanche multiplication gain in direct conversion amorphous selenium radiation detectors. The detector provides stable avalanche multiplication gain by eliminating field hot-spots using high-density avalanche wells with insulated wells and field-shaping within each well.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: January 24, 2017
    Assignee: The Research Foundation for The State University of New York
    Inventors: Amirhossein Goldan, Wei Zhao
  • Patent number: 9553221
    Abstract: Disclosed is an electromagnetic casting method of polycrystalline silicon which is characterized in that polycrystalline silicon is continuously cast by charging silicon raw materials into a bottomless cold mold, melting the silicon raw materials using electromagnetic induction heating, and pulling down the molten silicon to solidify it, wherein the depth of solid-liquid interface before the start of the final solidification process is decreased by reducing a pull down rate of ingot in a final phase of steady-state casting. By adopting the method, the region of precipitation of foreign substances in the finally solidified portion of ingot can be reduced and cracking generation can be prevented upon production of a polycrystalline silicon as a substrate material for a solar cell.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: January 24, 2017
    Assignee: SUMCO CORPORATION
    Inventors: Koichi Maegawa, Tomohiro Onizuka, Mitsuo Yoshihara
  • Patent number: 9553222
    Abstract: A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at ?4 V reverse bias. 3-dB bandwidth is 30 GHz.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: January 24, 2017
    Assignee: Elenion Technologies, LLC
    Inventors: Thomas Wetteland Baehr-Jones, Yi Zhang, Michael J. Hochberg, Ari Novack
  • Patent number: 9553223
    Abstract: A method of aligning microwires includes modifying the microwires so they are more responsive to a magnetic field. The method also includes using a magnetic field so as to magnetically align the microwires. The method can further include capturing the microwires in a solid support structure that retains the longitudinal alignment of the microwires when the magnetic field is not applied to the microwires.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: January 24, 2017
    Assignee: California Institute of Technology
    Inventors: Joseph A. Beardslee, Nathan S. Lewis, Bryce Sadtler
  • Patent number: 9553224
    Abstract: A semiconductor photodetector element includes a semiconductor substrate having a first conductivity type; a columnar structure formed on a first surface of the semiconductor substrate, the columnar structure being composed of a semiconductor of the first conductivity type; a light absorption layer formed so as to surround the columnar structure; and a semiconductor layer formed so as to surround the light absorption layer.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: January 24, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kenichi Kawaguchi, Nami Yasuoka, Hiroyasu Yamashita, Yoshiaki Nakata
  • Patent number: 9553225
    Abstract: A tapered trunking bus for carrying electricity from a row of solar panel arrays to a safety switch. The trunking bus includes a number of combiner and junction boxes connected in series. Each successive combiner and junction box combines the output of the previous combiner and junction box, received on a conductor of a first cross-sectional area, with electrical current received from a pair of solar panel arrays and outputs a higher current on a conductor of higher cross-sectional area. The cross-sectional area of each conductor is chosen to match the current to be carried and to account for the distance to the next combiner and junction box. For lower current segments of the trunking bus, cables or wires in conduits, of increasing gauges, can be used between combiner and junction boxes. For higher-current segments, metal bus bars of increasing cross-sectional area can be used between combiner and junction boxes.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: January 24, 2017
    Assignee: Schneider Electric USA, Inc.
    Inventor: James R. Ramsey
  • Patent number: 9553226
    Abstract: A method for manufacturing a solar cell module includes a cell forming operation of forming a plurality of first and second electrodes on a back surface of a semiconductor substrate to form each a plurality of solar cells, and a tabbing operation including at least one of a connection operation of performing a thermal process to respectively connect a first conductive line and a second conductive line to the first electrodes and the second electrodes of each solar cell using a conductive adhesive and an optional string forming operation of performing a thermal process to connect the first conductive line included in one solar cell and the second conductive line included in other solar cell adjacent to the one solar cell to an interconnect. The tabbing operation includes at least two thermal processes each having a different maximum temperature.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: January 24, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Bojoong Kim, Minpyo Kim, Daehee Jang, Hyeyoung Yang
  • Patent number: 9553227
    Abstract: Provided are an optical element and a concentrating photovoltaic device which are each capable of preventing warpage and deformation of an optical functional pattern formed in a surface thereof due to stress even in an environment with extreme temperature changes. An optical element (4) of a concentrating photovoltaic device (1) concentrating sunlight includes: a glass substrate (5) and a sheet-like molded body (6) which is made of an organic resin and includes a Fresnel lens pattern (6a) in a surface and has the other surface bonded to the glass substrate (5). The sheet-like molded body (6) has a tensile elastic modulus of 1500 MPa or less, a linear expansion coefficient of 7.0×10?5/° C. or less, an average transmittance of 85% or more in a wavelength range from 350 to 1850 nm at a thickness of 400 ?m, and a haze value of 1.0% or less.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: January 24, 2017
    Assignee: KURARAY CO., LTD.
    Inventors: Koji Abe, Shinji Hiramatsu, Katsuhiro Fujita
  • Patent number: 9553228
    Abstract: A solar cell of the invention includes a collecting electrode on a first principal surface of a photoelectric conversion section. The collecting electrode includes a first electroconductive layer and a second electroconductive layer in this order from the photoelectric conversion section. On the first principal surface of the photoelectric conversion section, an insulating layer is provided in a first electroconductive layer-non-formed region where the first electroconductive layer is not formed. The insulating layer includes a first insulating layer is in contact with the first electroconductive layer on the first principal surface of the photoelectric conversion section, and a second insulating layer that is formed so as to cover at least a part of the first insulating layer.
    Type: Grant
    Filed: May 17, 2014
    Date of Patent: January 24, 2017
    Assignee: KANEKA CORPORATION
    Inventors: Masashi Hino, Daisuke Adachi
  • Patent number: 9553229
    Abstract: A solar cell is fabricated by etching one or more of its layers without substantially etching another layer of the solar cell. In one embodiment, a copper layer in the solar cell is etched without substantially etching a topmost metallic layer comprising tin. For example, an etchant comprising sulfuric acid and hydrogen peroxide may be employed to etch the copper layer selective to the tin layer. A particular example of the aforementioned etchant is a Co-Bra Etch® etchant modified to comprise about 1% by volume of sulfuric acid, about 4% by volume of phosphoric acid, and about 2% by volume of stabilized hydrogen peroxide. In one embodiment, an aluminum layer in the solar cell is etched without substantially etching the tin layer. For example, an etchant comprising potassium hydroxide may be employed to etch the aluminum layer without substantially etching the tin layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: January 24, 2017
    Assignee: SunPower Corporation
    Inventors: Douglas H. Rose, Pongsthorn Uralwong, David D. Smith
  • Patent number: 9553230
    Abstract: A method for fabricating a light emitting apparatus in which at least a portion of a light emitting element is covered with a light transmissive resin containing phosphor which emits light when excited by light emitted by the light emitting element, the method including directly processing the phosphor by irradiating the phosphor with a laser beam which passes through the light transmissive resin, to adjust the chromaticity of light to be emitted by the light emitting apparatus.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: January 24, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Norio Yoshida, Hirotaka Uemi
  • Patent number: 9553231
    Abstract: The semiconductor layer sequence includes an n-conductive layer, a p-conductive layer and an active zone located therebetween. The active zone comprises N quantum wells with N?2. At a first working point (W1) at a first current density, the quantum wells have a first emission wavelength and, at a second working point (W2) at a second current density, a second emission wavelength. At least two of the first emission wavelengths differ from one another and at least some of the second emission wavelengths differ from the first emission wavelengths. The first current density is smaller than the second current density and the current densities differ from one another at least by a factor of 2.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: January 24, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Tobias Meyer, Jürgen Off
  • Patent number: 9553232
    Abstract: A light emitting device includes an n-type layer, a p-type layer structure, a layer of p-type nano-dots imbedded in the p-type layer structure, and an active region sandwiched between the n-type layer and the p-type layer structure, where the p-type nano-dots possess a sheet density of 1010 to 1012 cm?2, a lateral dimension of 2-20 nm, and a vertical dimension of 1-5 nm. The p-type layer structure with a layer of p-type nano-dots imbedded therein provides good vertical conductivity and UV transparency. Also provided is a method for making the light emitting device.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: January 24, 2017
    Assignee: BOLB INC.
    Inventors: Jianping Zhang, Hongmei Wang
  • Patent number: 9553233
    Abstract: A light emitting diode includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are orderly stacked on the substrate. The first electrode is electrically connected to the first semiconductor layer. The second electrode electrically is connected to the second semiconductor layer. The substrate has a number of three-dimensional nano-structures, and each of the number of three-dimensional nano-structures has a stepped structure.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: January 24, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 9553234
    Abstract: A method of manufacturing a nanostructure semiconductor light emitting device may includes preparing a mask layer by sequentially forming a first insulating layer and a second insulating layer on a base layer configured of a first conductivity-type semiconductor, forming a plurality of openings penetrating the mask layer, growing a plurality of nanorods in the plurality of openings, removing the second insulating layer, preparing a plurality of nanocores by re-growing the plurality of nanorods, and forming nanoscale light emitting structures by sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores. The plurality of openings may respectively include a mold region located in the second insulating layer, and the mold region includes at least one curved portion of which an inclination of a side surface varies according to proximity to the first insulating layer.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Goo Cha, Ki Hyung Lee, Wan Tae Lim, Geun Woo Ko, Min Wook Choi
  • Patent number: 9553235
    Abstract: A method for manufacturing a semiconductor light emitting device may include steps of forming a mask layer and a mold layer having a plurality of openings exposing portions of a base layer, forming a plurality of first conductivity-type semiconductor cores each including a body portion extending through each of the openings from the base layer and a tip portion disposed on the body portion and having a conical shape, and forming an active layer and a second conductivity-type semiconductor layer on each of the plurality of first conductivity-type semiconductor cores. The step of forming the plurality of first conductivity-type semiconductor cores may include forming a first region such that a vertex of the tip portion is positioned on a central vertical axis of the body portion, removing the mold layer, and forming an additional growth region on the first region such that the body portion has a hexagonal prism shape.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae Myung Chun, Ji Hye Yeon, Jae Hyeok Heo, Hyun Seong Kum, Han Kyu Seong, Young Jin Choi
  • Patent number: 9553236
    Abstract: A light emitting device includes a first conductive semiconductor layer on a substrate, a control layer interposed between the substrate and the first conductive semiconductor layer. The control layer includes a first nitride semiconductor layer having aluminum (Al), a plurality of nano-structures on the first nitride semiconductor layer, and a second nitride semiconductor layer provided on the first nitride semiconductor layer and having gallium (Ga).
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: January 24, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jae Hoon Choi, Young Jae Choi
  • Patent number: 9553237
    Abstract: A light emitting element includes a semiconductor layer; an upper electrode disposed on an upper surface of the semiconductor layer; and a lower electrode disposed on a lower surface of the semiconductor later. In a plan view, the upper electrode includes a first extending portion extending in an approximately rectangular shape along an outer periphery of the semiconductor layer, a first pad portion connected to a first side among four sides of the first extending portion, a second pad portion connected to a second side that is opposite to the first side, among the four sides of the first extending portion, and a second extending portion and a third extending portion, each disposed in a region surrounded by the first extending portion, the second extending portion and the third extending portion each connecting the first pad portion and the second pad portion.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 24, 2017
    Assignee: NICHIA CORPORATION
    Inventor: Hidetoshi Tanaka
  • Patent number: 9553238
    Abstract: A method of manufacturing a semiconductor light emitting element includes forming a semiconductor stacked layer body on a substrate, the semiconductor stacked layer body including a first semiconductor layer and a second semiconductor layer; removing a portion of the semiconductor stacked layer body and exposing the first semiconductor layer such that the second semiconductor layer includes an extending portion that extends in a plane direction; forming a conductor layer electrically connecting the first semiconductor layer and the extending portion of the second semiconductor layer; forming a first electrode electrically connected to the first semiconductor layer and a second electrode electrically connected to the second semiconductor layer; forming a protective film covering at least a portion of the first electrode and at least a portion of the second electrode; and after forming the protective film, removing a portion of the exposed portion of the extending portion.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: January 24, 2017
    Assignee: NICHIA CORPORATION
    Inventors: Kazuki Kashimoto, Masafumi Itasaka, Hisashi Kasai, Naoki Azuma
  • Patent number: 9553239
    Abstract: A light emitting device includes a first conductive-type semiconductor layer laminated on a substrate; a light emitting layer laminated on the first conductive-type semiconductor layer; a second conductive-type semiconductor layer laminated on the light emitting layer; a first ITO layer laminated at a side of the first conductive-type semiconductor layer opposite to the substrate; a second ITO layer laminated at a side of the second conductive-type semiconductor layer opposite to the substrate; a first metal layer laminated on the first ITO layer; and a second metal layer laminated on the second ITO layer. The first and second metal layers have the same structure and each includes a lower metal layer which contacts a corresponding ITO layer of the first ITO layer and the second ITO layer; and an upper metal layer laminated on the lower metal layer, the upper metal layer being thicker than the lower metal layer.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: January 24, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Takao Fujimori, Nobuaki Matsui
  • Patent number: 9553240
    Abstract: A semiconductor light-emitting element includes a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type, a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer, a first electrode connected to the first semiconductor layer, and a second electrode connected to the second semiconductor layer. The second electrode includes an ohmic electrode contacting the second semiconductor layer, and a semiconductor electrode made of a semiconductor layer contacting the ohmic electrode.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 24, 2017
    Assignee: NICHIA CORPORATION
    Inventor: Masahiko Sano
  • Patent number: 9553241
    Abstract: A method for producing a semiconductor light emitting device includes a light-emitting-element provision step, a light-emitting-element placement step, and a light-reflection-layer coating step, in this order. In the light-emitting-element provision step, a light emitting element is prepared which includes a semiconductor layer structure on the lower-surface side of a substrate. In the light-emitting-element placement step, the light emitting element is placed on or above a supporting member from the semiconductor layer structure side. In the light-reflection-layer coating step, the surfaces of the substrate and the semiconductor layer structure is coated with a light reflection layer by using atomic layer deposition so as to expose at least a part of the upper surface or a part of side surface of the substrate as a light-extracting region. The intended functioning of the light reflection layer can be ensured. The highly reliable light reflection layer can make the device good quality.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 24, 2017
    Assignee: NICHIA CORPORATION
    Inventor: Masatsugu Ichikawa
  • Patent number: 9553242
    Abstract: A semiconductor device package assembly which increases production efficiency of semiconductor devices by enabling the number of semiconductor device packages held by a carrier to be increased. A predetermined area of a first housing molded of white-colored resin, which holds a plurality of bent contacts, is covered by a second housing molded of black-colored resin, and a plurality of second housings are supported by a secondary molding carrier in high density. A linking portion of each contact and one or both of the first and second housings are integrated by insert molding.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: January 24, 2017
    Assignee: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED
    Inventors: Takaaki Kudo, Naofumi Ikenaga, Tetsu Urano
  • Patent number: 9553243
    Abstract: This disclosure relates to a light-emitting apparatus comprising a submount, a chip carrier formed on the submount, a light-emitting chip formed on the chip carrier, a reflecting cup formed on the submount and enclosing the light-emitting chip and the chip carrier, and a transparent encapsulating material for encapsulating the light-emitting chip.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: January 24, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Ta-Cheng Hsu, Meng-Lun Tsai, Chih-Chiang Lu, Chien-Yuan Wang, Yen-Wen Chen, Ya-Ju Lee
  • Patent number: 9553244
    Abstract: Disclosed herein is a light emitting device, comprising: a lighting element located in a housing, wherein the housing is formed from a plastic composition comprising: a conversion material, and a polycarbonate composition comprising: a flame retardant comprising a sulfonate salt and three polycarbonates. The first polycarbonate has a branching level of greater than or equal to 2%, a weight average molecular weight of 20,000 g/mole to 55,000 g/mole and a peak melt viscosity of greater than or equal to 25,000 poise. The second polycarbonate has a glass transition temperature greater than or equal to 170° C. The third polycarbonate has a branching level of 0 to less than 2% and a molecular weight of 17,000 to 40,000 g/mol.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: January 24, 2017
    Assignee: SABIC GLOBAL TECHNOLOGIES B.V.
    Inventors: Jean-Francois Morizur, Peter Hendrikus Theodorus Vollenberg
  • Patent number: 9553245
    Abstract: A light emitting device includes: a substrate having a base body and a plurality of wiring parts provided on at least one side of the base body; a first covering part that covers part of the wiring parts; a plurality of light emitting elements that are disposed on the wiring parts exposed from the first covering part; a second covering part that is disposed on the first covering part surrounding the light emitting elements and is formed from a material whose reflectivity is higher than that of the first covering part, and a resin component that seals the substrate and the light emitting elements, and is disposed in contact with the first covering part and the second covering part.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: January 24, 2017
    Assignee: NICHIA CORPORATION
    Inventor: Kazuhiro Kamada
  • Patent number: 9553246
    Abstract: A silicone-grafted core-shell particle is described wherein the silicone-grafted core-shell particle comprises a core of an inorganic particle and a shell of a grafted poly(dimethylsiloxane) polymer formed from a bi-terminated poly(dimethylsiloxane) having reactive groups at each terminal end. The silicone-grafted core-shell particles may be dispersed in a polysiloxane polymer matrix and employed as an LED encapsulant.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 24, 2017
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: Maxim N. Tchoul, Alan L. Lenef, David W. Johnston
  • Patent number: 9553247
    Abstract: A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: January 24, 2017
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Kazunori Oda, Masaki Yazaki
  • Patent number: 9553248
    Abstract: A lighting device comprising a plurality of LEDs; a plurality of optic devices corresponding to the plurality of LEDs; at least one optical separator for substantially preventing the light emitted from one LED from effecting the other LEDs; a thermoelectric device configured to harvest heat generated by the LEDs and convert the harvested heat into electrical energy; and a low temperature material for creating a temperature difference across the thermoelectric device.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: January 24, 2017
    Assignee: Photon Holding LLC
    Inventor: Daniel Stewart Lang
  • Patent number: 9553249
    Abstract: The invention relates to a method for producing a thermoelectric component or at least one semi-finished product of same, in which a multiplicity of thermolegs made of a thermoelectrically active material are introduced into an essentially planar substrate made of an electrically and thermally insulating substrate material such that the thermolegs extend through the substrate essentially perpendicular to the substrate plane, and in which the active material is provided in pulverulent form, is pressed to give green bodies and is then sintered within the substrate to give thermolegs. It is based on the object of refining the method of the generic type mentioned in the introduction so as to increase the freedom of choice of the thermally and electrically insulating substrate material.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: January 24, 2017
    Assignee: Evonik Degussa GmbH
    Inventors: Jens Busse, Sascha Hoch, Magdalena Kern, Mareike Giesseler, Thorsten Schultz, Patrik Stenner, Paw V. Mortensen, Ali Asghar Enkeshafi
  • Patent number: 9553250
    Abstract: An insulating substrate to which intermediate portions or conductive pastes constituting the intermediate portions are disposed, a front surface protective member to which front surface patterns are formed, and a back surface protective member to which back surface patterns are formed are prepared. A laminated body, to which first end portions or conductive pastes constituting the first end portions are disposed between the intermediate portions or the conductive pastes constituting the intermediate portions and the front surface patterns, and second end portions or conductive pastes constituting the second end portions are disposed between the intermediate portions or the conductive pastes constituting the intermediate portions and the back surface patterns, is constituted. Then, thermoelectric conversion elements are formed by integrating the laminated body.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: January 24, 2017
    Assignee: DENSO CORPORATION
    Inventors: Norio Gouko, Atusi Sakaida, Toshihisa Taniguchi, Yoshihiko Shiraishi, Keiji Okamoto
  • Patent number: 9553251
    Abstract: A piezoelectric device includes a deformation portion, a non-deformation portion which hinders deformation of the elastic layer, and a piezoelectric element. The deformation portion includes a first area in which the piezoelectric element is disposed, a third area adjacent to the non-deformation portion, and a second area disposed between the first area and the third area. In the first area, the elastic layer, an insulation layer, the lower electrode layer, the piezoelectric layer, and the upper electrode layer are sequentially stacked. In the second area, the elastic layer, the insulation layer, the piezoelectric layer, and the upper electrode layer are sequentially stacked. In the third area, the elastic layer and the upper electrode layer are sequentially stacked. The elastic layer is silicon oxide, and impurities are added to the upper electrode layer in the silicon oxide in the third area.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: January 24, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Yoichi Naganuma, Masao Nakayama, Eiju Hirai, Takeshi Saito, Yoshihiro Hokari
  • Patent number: 9553252
    Abstract: Provided is a piezoelectric/electrostrictive film type element in which the film thickness of the piezoelectric/electrostrictive film is small, the piezoelectric/electrostrictive film is dense, and the piezoelectric/electrostrictive film has good durability and insulation quality. The piezoelectric/electrostrictive film type element includes a substrate, a lower electrode film, a piezoelectric/electrostrictive film and an upper electrode film. The substrate and the lower electrode film are fixed adherently each other. The film thickness of the piezoelectric/electrostrictive film is 5 ?m or less. The piezoelectric/electrostrictive film is composed of a piezoelectric/electrostrictive ceramic. The piezoelectric/electrostrictive ceramic contains lead zirconate titanate and a bismuth compound.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: January 24, 2017
    Assignee: NGK Insulators, Ltd.
    Inventors: Takaaki Koizumi, Tomohiko Hibino, Takashi Ebigase
  • Patent number: 9553253
    Abstract: A lower electrode and an adhesive layer made of an insulator are formed on a back surface on the ion implantation layer side of a piezoelectric single crystal substrate. A supporting substrate in which sacrificial layers made of a conductive material have been formed is bonded to the surface of the adhesive layer. By heating the composite body including the piezoelectric single crystal substrate, the lower electrode, the adhesive layer, and the supporting substrate, a layer of the piezoelectric single crystal substrate is detached to form a piezoelectric thin film. A liquid polarizing upper electrode is formed on a detaching interface of the piezoelectric thin film. A pulsed electric field is applied using the polarizing upper electrode and the sacrificial layers as counter electrodes. Consequently, the piezoelectric thin film is polarized.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: January 24, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takashi Iwamoto, Hajime Kando
  • Patent number: 9553254
    Abstract: A process for producing a patterned deformable polymer film for use in a deformable polymer device is disclosed. The process includes positioning an intermediary layer between a deformable film and a process tooling and printing at least one electrode on the deformable film by depositing an ink to form the at least one electrode on a first surface of the deformable film, wherein the intermediary layer permits release of the deformable film from the process tooling subsequent to the printing process. Films produced by the inventive processes may find use in electroactive polymer devices.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: January 24, 2017
    Assignee: Parker-Hannifin Corporation
    Inventors: Francois Egron, Pat Liptawat, Junfeng Mei, Hooman Mousavi Nazari, Xina Quan, Marcus A. Rosenthal, William D. Sutherland, Luther L. White, III
  • Patent number: 9553255
    Abstract: A memory element includes a memory layer having magnetization perpendicular to a film face of the memory layer in which a direction of the magnetization configured to be changed. The memory element includes a magnetization-fixed layer having a magnetization perpendicular to the film face. The memory element includes an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. The memory layer includes a multilayer structure in which a non-magnetic material and an oxide are laminated. The direction of the magnetization of the memory layer is configured to be changed by applying a current in a lamination direction of the layered structure to record information in the memory layer.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: January 24, 2017
    Assignee: SONY CORPORATION
    Inventors: Hiroyuki Uchida, Masanori Hosomi, Hiroyuki Ohmori, Kazuhiro Bessho, Yutaka Higo, Tetsuya Asayama, Kazutaka Yamane
  • Patent number: 9553256
    Abstract: A spin valve element 10 including a spin injector 12 made of a ferromagnetic material, a spin detector 16 made of a ferromagnetic material, and a channel part 14 made of a non-magnetic material. The spin detector 16 is arranged at a position separated from the spin injector 12, the channel part 14 is connected with the spin injector 12 and the spin detector 16 directly or through an insulating layer, and a plurality of spin diffusion portions 30 to 34 with enlarged cross section areas in a direction perpendicular to a spin current is formed in the channel part 14.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: January 24, 2017
    Assignees: Japan Science and Technology Agency, The University of York
    Inventor: Atsufumi Hirohata
  • Patent number: 9553257
    Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Michael C. Gaidis, Rohit Kilaru
  • Patent number: 9553258
    Abstract: A magnetoresistive memory element (for example, a spin-torque magnetoresistive memory element), includes first and second dielectric layers, wherein at least one of the dielectric layers is a magnetic tunnel junction. The memory element also includes a free magnetic layer having a first surface in contact with the first dielectric layer and a second surface in contact with the second dielectric layer. The free magnetic layer, which is disposed between the first and second dielectric layers, includes (i) a first high-iron interface region located along the first surface of the free magnetic layer, wherein the first high-iron interface region has at least 50% iron by atomic composition, and (ii) a first layer of ferromagnetic material adjacent to the first high-iron interface region, the first high-iron interface region between the first layer of ferromagnetic material and the first surface of the free magnetic layer.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: January 24, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jijun Sun, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine, Frederick Mancoff
  • Patent number: 9553259
    Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is spaced from the first electrode and comprises magnetic reference material. A non-magnetic tunnel insulator material is between the first and second electrodes. The magnetic recording material of the first electrode comprises a first crystalline magnetic region, in one embodiment comprising Co and Fe. In one embodiment, the first electrode comprises a second amorphous region comprising amorphous XN, where X is one or more of W, Mo, Cr, V, Nb, Ta, Al, and Ti. In one embodiment, the first electrode comprises a second region comprising Co, Fe, and N.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Manzar Siddik
  • Patent number: 9553260
    Abstract: A conductive via disposed beneath a magnetic device and aligned therewith. In certain embodiments, an electrode formed on the conductive via may be polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to, for example, a 45 nanometer node.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: January 24, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Kenneth Smith, Moazzem Hossain, Sanjeev Aggarwal
  • Patent number: 9553261
    Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: January 24, 2017
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Renu Whig, Phillip Mather, Kenneth Smith, Sanjeev Aggarwal, Jon Slaughter, Nicholas Rizzo
  • Patent number: 9553262
    Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Kunal R. Parekh
  • Patent number: 9553263
    Abstract: A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Christopher W. Petz, Yongjun Jeff Hu, Scott E. Sills, D. V. Nirmal Ramaswamy