Patents Issued in January 24, 2017
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Patent number: 9553113Abstract: A pixel unit includes a scan line, data lines, first and second pixel structures, first and second common electrode lines, and a common connecting portion. The first pixel structure includes a first switching element, a first main pixel electrode, a first sub pixel electrode, and a first active element. The second pixel structure includes a second switching element, a second main pixel electrode, a second sub pixel electrode, and a second active element. The first main and sub pixel electrodes and the first active element are electrically connected to the first switching element. The second main and sub pixel electrodes and the second active element are electrically connected to the second switching element. The first and second common electrode lines are separated at a position where the scan line passes. The common connecting portion electrically connects the first common electrode line and the second common electrode line.Type: GrantFiled: June 16, 2016Date of Patent: January 24, 2017Assignee: AU OPTRONICS CORPORATIONInventors: Hung-Che Lin, Sheng-Ju Ho, Shang-Jie Wu
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Patent number: 9553114Abstract: A novel display device capable of adjusting color purity is provided. A novel display device with improved adhesion of a color filter is provided. A novel display device capable of excellent reflective display is provided. The display device includes a transistor, a reflective electrode layer formed on the same surface as a source electrode layer or a drain electrode layer of the transistor, a first insulating layer over the reflective electrode layer, a coloring layer which is over the first insulating layer and overlaps with the reflective electrode layer, a second insulating layer over the coloring layer, and a pixel electrode layer over the second insulating layer. The coloring layer includes at least a first opening and a second opening. The pixel electrode layer is electrically connected to the transistor through the first opening. The second insulating layer is in contact with the first insulating layer in the second opening.Type: GrantFiled: October 16, 2014Date of Patent: January 24, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masataka Nakada, Hidenori Mori, Hisashi Ohtani
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Patent number: 9553115Abstract: The present invention provides a manufacturing method of a TFT substrate structure, which includes sequentially forming a first passivation layer, a planarization layer, and a first transparent conductive film and then first subjecting the first transparent conductive film to patterning to form a first pixel electrode and thereafter, a photolithographic process is applied to the planarization layer for exposure and thus forming a first via located above and corresponding to a drain terminal, followed by using the planarization layer as a self-aligning mask to apply dry etching to the first passivation layer for etching to form a second via that corresponds to the first via, whereby residues of the first transparent conductive film in the first and second vias can be effectively prevented and product yield is enhanced.Type: GrantFiled: July 27, 2015Date of Patent: January 24, 2017Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Xiaowen Lv
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Patent number: 9553116Abstract: A substrate-removed, surface passivated, and anti-reflective (AR) coated detector assembly is provided. The assembly has an AR coating or passivation layer which includes a wide bandgap thin-film dielectric/passivation layer integrated therein. The wide bandgap thin-film dielectric/passivation layer is positioned proximal to a back interface of a substrate-removed detector assembly. A method of manufacturing the detector assembly includes etching a backside of a partially-removed-substrate detector assembly to obtain an etched detector assembly removed from a substrate. A wide bandgap layer is deposited, in a vacuum chamber, on the etched detector assembly without utilizing an adhesive layer. Additional anti-reflective coating layers are deposited, in the same vacuum chamber, on the wide bandgap layer to form an anti-reflective coating layer with the wide bandgap layer integrated therein.Type: GrantFiled: June 1, 2015Date of Patent: January 24, 2017Assignee: Teledyne Scientific & Imaging, LLCInventors: Donald L. Lee, Eric Piquette, Majid Zandian, Paul H. Kobrin, Haluk Sankur
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Solid-state image pickup apparatus, and image pickup system using solid-state image pickup apparatus
Patent number: 9553117Abstract: A solid-state image pickup apparatus includes a photoelectric conversion unit, a charge storage unit, and a floating diffusion unit, all disposed on a semiconductor substrate. The solid-state image pickup apparatus further includes a first gate electrode disposed on the semiconductor substrate and extending between the photoelectric conversion unit and charge storage unit, and a second gate electrode disposed on the semiconductor substrate and extending between the charge storage unit and the floating diffusion unit. The solid-state image pickup apparatus further includes a light shielding member including a first part and a second part, wherein the first part is disposed over the charge storage unit and at least over the first gate electrode or the second gate electrode, and the second part is disposed between the first gate electrode and the second gate electrode such that the second part extends from the first part toward a surface of the semiconductor substrate.Type: GrantFiled: December 2, 2015Date of Patent: January 24, 2017Assignee: CANON KABUSHIKI KAISHAInventors: Masahiro Kobayashi, Yuichiro Yamashita, Yusuke Onuki -
Patent number: 9553118Abstract: A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A buffer layer is disposed over the second side of the substrate. A plurality of elements is disposed over the buffer layer. The elements and the buffer layer have different material compositions. A plurality of light-blocking structures is disposed over the plurality of elements, respectively. The radiation-sensing regions are respectively aligned with a plurality of openings defined by the light-blocking structures, the elements, and the buffer layer.Type: GrantFiled: June 18, 2014Date of Patent: January 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun-Wei Cheng, Chiu-Jung Chen, Volume Chien, Kuo-Cheng Lee, Yung-Lung Hsu, Hsin-Chi Chen
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Patent number: 9553119Abstract: Methods of forming an image sensor are provided. A method of forming an image sensor includes forming a trench in a substrate to define a unit pixel region of the substrate. The method includes forming an in-situ-doped passivation layer on an exposed surface of the trench. The method includes forming a capping pattern on the in-situ-doped passivation layer, in the trench. The method includes forming a photoelectric conversion region in the unit pixel region. Moreover, the method includes forming a floating diffusion region in the unit pixel region.Type: GrantFiled: September 9, 2015Date of Patent: January 24, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Young Choi, Taegon Kim, JunHyun Cho
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Patent number: 9553120Abstract: A technology capable of simplifying a process and securing a misalignment margin when bonding two wafers to manufacture an image sensor using backside illumination photodiodes. When manufacturing an image sensor through a 3D CIS (CMOS image sensor) manufacturing process, two wafers, that is, a first wafer and a second wafer are electrically connected using the vias of one wafer and the bonding pads of the other wafer. Also, when manufacturing an image sensor through a 3D CIS manufacturing process, two wafers are electrically connected using the vias of both the two wafers.Type: GrantFiled: October 31, 2014Date of Patent: January 24, 2017Assignee: SILICONFILE TECHNOLOGIES INC.Inventors: Jae Young Park, Young Ha Lee, Jun Ho Won, Do Young Lee
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Patent number: 9553121Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.Type: GrantFiled: August 25, 2015Date of Patent: January 24, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiroaki Sekikawa, Hidenori Sato, Yotaro Goto, Takuya Maruyama, Masaaki Shinohara
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Patent number: 9553122Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.Type: GrantFiled: April 9, 2013Date of Patent: January 24, 2017Assignee: INTELLECTUAL VENTURES II LLCInventors: Jaroslav Hynecek, Leonard Forbes, Homayoon Haddad, Thomas Joy
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Patent number: 9553123Abstract: A back-illuminated sensor chip is disclosed, which includes one or more pixel areas each including a plurality of pixels located in a plane and arranged in a matrix. Each pixel area includes: a central portion consisting of a plurality of first pixels located in vicinity of a center of the pixel area; and a peripheral portion surrounding the central portion and consisting of the other pixels in the pixel area than the first pixels. The plurality of first pixels have a first height in a vertical direction perpendicular to the plane, and the pixels in the peripheral portion have a second height in the vertical direction that is greater than the first height so that the peripheral portion protrudes outward beyond the central portion and is thus located nearer to a light source during imaging than the central portion. As a result, light sensibility of the peripheral portion is increased.Type: GrantFiled: April 20, 2016Date of Patent: January 24, 2017Assignee: OMNIVISION TECHNOLOGIES (SHANGHAI) CO., LTD.Inventors: Feng Lin, Quanbao Li, Guo Ye
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Patent number: 9553124Abstract: A CMOS image sensor including a plurality of pixels, each including: a photodiode; a sigma-delta modulator of order p, p being an integer greater than or equal to 1, capable of delivering a binary digital signal representative of the illumination level of the photodiode; and a configurable connection circuit enabling to couple the sigma-delta modulator of the pixel to a sigma-delta modulator of another pixel, so that the modulators of the two pixels form with each other a sigma-delta modulator of order greater than p.Type: GrantFiled: November 12, 2015Date of Patent: January 24, 2017Assignee: Commissariat a l'energie atomique et aux energies alternativesInventor: Arnaud Verdant
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Patent number: 9553125Abstract: Disclosed is a solid-state imaging device including: a solid-state imaging element which outputs an image signal according to an amount of light sensed on a light sensing surface; a semiconductor element which performs signal processing with respect to the image signal output from the solid-state imaging element; and a substrate which is electrically connected to the solid-state imaging element and the semiconductor element, in which the semiconductor element is sealed by a molding resin in a state of being accommodated in an accommodation area which is provided on the substrate, and in which the solid-state imaging element is layered on the semiconductor element via the molding resin.Type: GrantFiled: December 8, 2014Date of Patent: January 24, 2017Assignee: Sony CorporationInventor: Yosuke Ogata
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Patent number: 9553126Abstract: A wafer-level method for fabricating a plurality of cameras includes modifying an image sensor wafer to reduce risk of the image sensor wafer warping, and bonding the image sensor wafer to a lens wafer to form a composite wafer that includes the plurality of cameras. A wafer-level method for fabricating a plurality of cameras includes bonding an image sensor wafer to a lens wafer, using a pressure sensitive adhesive, to form a composite wafer that includes the plurality of cameras.Type: GrantFiled: May 5, 2014Date of Patent: January 24, 2017Assignee: OmniVision Technologies, Inc.Inventors: Alan Martin, Edward Nabighian
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Patent number: 9553127Abstract: A light-emitting diode structure comprises a first epitaxial unit; a second epitaxial unit separated from the first epitaxial unit; a crossover metal layer comprising a first protruding portion entering the first epitaxial unit; a conductive layer separated from the crossover metal layer and comprising a second protruding portion entering the second epitaxial unit; a conductive connecting layer surrounding the first protruding portion; and an electrode arranged on the conductive connecting layer.Type: GrantFiled: November 30, 2015Date of Patent: January 24, 2017Assignee: Epistar CorporationInventors: Li-Ping Jou, Yu-Chen Yang, Jui-Hung Yeh
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Patent number: 9553128Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.Type: GrantFiled: June 30, 2015Date of Patent: January 24, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Annunziata, Michael C. Gaidis, Rohit Kilaru
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Patent number: 9553129Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate defined with a memory cell region. A first upper dielectric layer is provided over the substrate. The first upper dielectric layer includes a first upper interconnect level with one or more metal lines in the memory cell region. A second upper dielectric layer is provided over the first upper dielectric layer. The second upper dielectric layer includes a via plug coupled to the metal line of the first upper interconnect level. An alignment trench which extends from a top surface of the second upper dielectric layer to a portion of the second upper dielectric layer is formed. Various layers of a MTJ stack are formed over the second upper dielectric layer. Profile of the alignment trench is transferred to surfaces of the various layers of the MTJ stack to form a topography feature which serves as an alignment mark.Type: GrantFiled: September 23, 2015Date of Patent: January 24, 2017Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Yi Jiang, Wanbing Yi, Juan Boon Tan, Danny Pak-Chum Shum
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Patent number: 9553130Abstract: A semiconductor device includes four or more memory cells arranged on a row, the memory cells each including a first pillar-shaped semiconductor layer, a first gate insulating film around the semiconductor layer, a first gate line around the first gate insulating film, a third gate insulating film around an upper portion of the semiconductor layer, a first contact electrode around the third gate insulating film, a second contact electrode connecting upper portions of the semiconductor layer and the first contact electrode, and a magnetic tunnel junction storage element on the second contact electrode, a first source line connecting lower portions of the semiconductor layers to each other, a first bit line extending in a direction perpendicular to a direction of the first gate line and connected to an upper portion of the storage element, and a second source line extending in a direction perpendicular to the first source line.Type: GrantFiled: April 8, 2016Date of Patent: January 24, 2017Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9553131Abstract: Disclosed is a semiconductor device that reduces the area of a transistor in a ReRAM. A plurality of memory cells differ from each other in the combination of bit line and plate line. The potential of plate line PL2 is a forming voltage. By contrast, the potentials of the other plate lines are +Vi. The potential of bit line BL2 is 0 V (ground potential). By contrast, the potentials of the other bit lines are +Vi. The potential of is +Vgf. By contrast, the potentials of the other word lines are +Vi.Type: GrantFiled: July 24, 2015Date of Patent: January 24, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Toshiharu Nagumo, Kiyoshi Takeuchi, Toyoji Yamamoto
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Patent number: 9553132Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.Type: GrantFiled: March 14, 2016Date of Patent: January 24, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kobayashi, Yoshihisa Iwata, Takeshi Sugimoto
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Patent number: 9553133Abstract: A method for producing an optoelectronic assembly having a first and at least a second optoelectronic components may include forming a first electrically conductive layer on a substrate, forming a second electrically conductive layer on the first electrically conductive layer, applying an insulator material on the second electrically conductive layer and the substrate, such that at least a first insulator region, which insulates a first component region from a second component region, a second insulator region, which insulates the second component region from a first contact region, a third insulator region arranged on a side of the first component region, and a fourth insulator region arranged between the first and second insulator regions on a side of the second component region are formed by the insulator material, forming a first and second optically functional layers in the first and second component regions, respectively, and applying an electrically conductive electrode layer.Type: GrantFiled: September 26, 2013Date of Patent: January 24, 2017Assignee: OSRAM OLED GMBHInventor: Andrew Ingle
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Patent number: 9553134Abstract: Provided is a display device, including: a first substrate including a display area and a non-display area adjacent to the display area; a display unit on the first substrate at the display area and configured to display an image; a display wiring on the first substrate at the non-display area and coupled to the display unit; a second substrate on the first substrate with the display unit and the display wiring therebetween; a touch unit on the second substrate, corresponding to the display unit, and configured to recognize a touch; a touch wiring on the second substrate at the non-display area and coupled to the touch unit; and an anti-noise electrode between the display wiring and the touch wiring at the non-display area.Type: GrantFiled: August 28, 2014Date of Patent: January 24, 2017Assignee: Samsung Display Co., Ltd.Inventors: Hui Nam, Jong-Seo Lee, Beom Shik Kim, Joon Hak Oh
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Patent number: 9553135Abstract: Disclosed is a flexible display substrate and a method for manufacturing the same which can avoid break and peeling of film layers disposed on a flexible base and further reduce degree of a warpage occurred in the flexible base when separating the support substrate from the flexible base located above the support substrate. The flexible display substrate comprises the flexible base, a first buffer layer and a second buffer layer disposed on an upper surface and a lower surface of the flexible base, respectively, and a plurality of display modules disposed on the first buffer layer, each display module includes at least one thin film transistor and at least one electrode corresponding to the thin film transistor.Type: GrantFiled: March 27, 2014Date of Patent: January 24, 2017Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Ming-Che Hsieh, Chunyan Xie, Lu Liu
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Patent number: 9553136Abstract: An organic light emitting diode (OLED) display, including a flexible substrate bent in a first direction, an OLED arranged on the flexible substrate, a first thin film transistor connected to the OLED and including a first channel area extending in a second direction crossing the first direction, and one or more additional thin film transistors connected to the first thin film transistor and including corresponding additional channel areas extending in the second direction.Type: GrantFiled: September 20, 2013Date of Patent: January 24, 2017Assignee: Samsung Display Co., Ltd.Inventors: Tae-Woong Kim, Hyun-Woo Koo, Young-Gug Seol, Young-Ki Hong, Won-Kyu Kwak, Yang-Wan Kim, Han-Sung Bae
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Patent number: 9553137Abstract: A display device includes a substrate, a plurality of first layered link lines spaced apart from each other on the substrate, a first insulating layer on the plurality of first layered link lines, a plurality of second layered link lines spaced apart from each other on the first insulating layer, each second layered link line between neighboring first layered link lines, a second insulating layer on the plurality of second layered link lines, and a plurality of data lines or a plurality of gate lines connected to the plurality of first layered link lines and the plurality of second layered link lines.Type: GrantFiled: November 21, 2014Date of Patent: January 24, 2017Assignee: LG Display Co., Ltd.Inventors: Geun-Young Kim, Du-Hwan Oh, Soon-Jae Hwang
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Patent number: 9553138Abstract: An organic light-emitting diode display is disclosed. In one aspect, the OLED display includes a first connection line extending in a first direction and electrically connected to an OLED configured to emit light, a repair line extending in a second direction crossing the first direction, and an insulating layer formed between the first connection line and the repair line and configured to electrically insulate the first connection line from the repair line. The repair line includes a joining portion extending from the repair line in the first direction and at least partially overlapping a portion of the first connection line.Type: GrantFiled: October 26, 2015Date of Patent: January 24, 2017Assignee: Samsung Display Co., Ltd.Inventors: Dae-Woo Kim, Jong-Hyun Park, Sun Park
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Patent number: 9553139Abstract: In accordance with an embodiment, a semiconductor component and a method for manufacturing a semiconductor component are provided. A first dielectric material is formed over a body of semiconductor material of the first conductivity type and a plurality of semiconductor fingers are formed over the first of dielectric material. Semiconductor fingers of the plurality of semiconductor fingers spaced apart from each other and at least one of the semiconductor fingers has a first end spaced apart from a second end by a central region. A second dielectric material is formed over central region of the at least one semiconductor finger of the plurality of semiconductor fingers. An electrically conductive material is formed over the second dielectric material that is over the central region of the at least one semiconductor finger. The electrically conductive material serves as a shielding structure and the semiconductor material may be coupled to a fixed potential.Type: GrantFiled: January 30, 2015Date of Patent: January 24, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Akinobu Onishi, Takashi Oomikawa
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Patent number: 9553140Abstract: An integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the integrated circuit includes a substrate and a polysilicon resistor. The polysilicon resistor is disposed on the substrate. The polysilicon resistor has at least one positive TCR portion and at least one negative TCR portion. The positive TCR portion is adjacent to the negative TCR portion, and the positive TCR portion is in direct contact with the negative TCR portion.Type: GrantFiled: March 31, 2016Date of Patent: January 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung-Sen Wang, Shih-Chi Yang, Kuo-Ching Chang, Wei-Sho Hung, Ho-Chun Liou
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Patent number: 9553141Abstract: A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.Type: GrantFiled: September 18, 2015Date of Patent: January 24, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Jeong Yang, Soon-Wook Jung, Bong-Jin Kuh, Wan-Don Kim, Byung-Hong Chung, Yong-Suk Tak
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Patent number: 9553142Abstract: A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a source region disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the source region along a first direction, and a buried layer having the second conductivity type and disposed under an area between the source region and the drain region.Type: GrantFiled: June 12, 2015Date of Patent: January 24, 2017Assignee: Macronix International Co., Ltd.Inventors: Yu-Jui Chang, Cheng-Chi Lin
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Patent number: 9553143Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor layer disposed over the semiconductor layer; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the semiconductor layer between the first isolation element and the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region. The bottom surface of the gate structure is above, below or substantially level with a bottom surface of the first isolation structure.Type: GrantFiled: February 12, 2015Date of Patent: January 24, 2017Assignee: Vanguard International Semiconductor CorporationInventors: Shang-Hui Tu, Yu-Lung Chin, Shin-Cheng Lin
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Patent number: 9553144Abstract: A semiconductor device includes a semiconductor substrate; a first semiconductor region that includes an extension portion extending in a specific direction at a specific width as viewed along a direction orthogonal to the main surface; a second semiconductor region that is shaped to include a portion running along the extension portion of the first semiconductor region as viewed along the direction orthogonal to the main surface; a field relaxation layer that relaxes a field generated between the first semiconductor region and the second semiconductor region, that is formed on the second semiconductor region side of the main surface, and that is formed by a semiconductor layer; and a conductor that is connected to the second semiconductor region, and that has an end portion on the first conductor region side positioned within the range of the field relaxation layer.Type: GrantFiled: August 6, 2015Date of Patent: January 24, 2017Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Toru Mori
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Patent number: 9553145Abstract: Methods of forming bipolar device structures and bipolar device structures. An opening may be formed in a device layer of a silicon-on-insulator substrate that extends to a buried insulator layer of the silicon-on-insulator substrate. An intrinsic base layer may be grown within the device layer opening by lateral growth on opposite first and second sidewalls of the device layer bordering the opening. A first collector of a first bipolar junction transistor of the device structure may be formed at a first spacing from the first sidewall. A second collector of a second bipolar junction transistor of the device structure may be formed at a second spacing from the second sidewall. An emitter, which is shared by the first bipolar junction transistor and the second bipolar transistor, is formed inside the opening. Portions of the intrinsic base layer may supply respective intrinsic bases for the first and second bipolar junction transistors.Type: GrantFiled: September 3, 2014Date of Patent: January 24, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: David L. Harame, Michael L. Kerbaugh, Qizhi Liu
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Patent number: 9553146Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.Type: GrantFiled: June 5, 2014Date of Patent: January 24, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yanli Zhang, Matthias Baenninger, Akira Matsudaira, Yao-Sheng Lee, Johann Alsmeier
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Patent number: 9553147Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.Type: GrantFiled: March 30, 2015Date of Patent: January 24, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Ying Zhang, Hua Chung
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Patent number: 9553148Abstract: In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.Type: GrantFiled: April 3, 2015Date of Patent: January 24, 2017Assignee: ASM IP HOLDING B.V.Inventors: Qi Xie, Vladimir Machkaoutsan, Jan Willem Maes
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Patent number: 9553149Abstract: A semiconductor device with a strained region is provided. The semiconductor device includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the second dielectric layer having a first fin disposed therein and an interface disposed proximate the first fin. The interface includes a first oxide region disposed in the first dielectric layer and a second oxide region disposed in the second dielectric layer. The interface induces strain in a region of the semiconductor device. A method of making a semiconductor device with a strained region is also provided.Type: GrantFiled: November 8, 2013Date of Patent: January 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
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Patent number: 9553150Abstract: Some embodiments of the present disclosure relate to a transistor device formed in a semiconductor substrate containing dopant impurities of a first impurity type. The transistor device includes channel composed of a delta-doped layer comprising dopant impurities of the first impurity type, and configured to produce a peak dopant concentration within the channel. The channel further includes a layer of carbon-containing material overlying the delta-doped layer, and configured to prevent back diffusion of dopants from the delta-doped layer and semiconductor substrate. The channel also includes of a layer of substrate material overlying the layer of carbon-containing material, and configured to achieve steep retrograde dopant concentration profile a near a surface of the channel.Type: GrantFiled: October 12, 2015Date of Patent: January 24, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Yuan Chen, Tsung-Hsing Yu, Ken-Ichi Goto, Zhiqiang Wu
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Patent number: 9553151Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.Type: GrantFiled: June 5, 2015Date of Patent: January 24, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sameer Pendharkar, Naveen Tipirneni, Jungwoo Joh
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Patent number: 9553152Abstract: A semiconductor device includes: a first semiconductor layer which is formed over a substrate and is formed from a nitride semiconductor; a second semiconductor layer which is formed over the first semiconductor layer and is formed from a nitride semiconductor; a third semiconductor layer which is formed over the second semiconductor layer and is formed from a nitride semiconductor; a source electrode and a drain electrode which are formed over the third semiconductor layer; an opening which is formed in the second semiconductor layer and the third semiconductor layer between the source electrode and the drain electrode; an insulating layer which is formed on a side surface and a bottom surface of the opening; and a gate electrode which is formed in the opening through the insulating layer.Type: GrantFiled: December 4, 2014Date of Patent: January 24, 2017Assignee: FUJITSU LIMITEDInventors: Toshihiro Ohki, Lei Zhu, Naoya Okamoto, Yuichi Minoura, Shirou Ozaki
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Patent number: 9553153Abstract: A method of reducing defects in epitaxially grown III-V semiconductor material comprising: epitaxially growing a III-V semiconductor on a substrate; patterning and removing portions of the III-V semiconductor to form openings; depositing thermally stable material in the openings; depositing a capping layer over the semiconductor material and thermally stable material to form a substantially enclosed semiconductor; and annealing the substantially enclosed semiconductor.Type: GrantFiled: December 2, 2015Date of Patent: January 24, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John A. Ott, Devendra K. Sadana, Brent A. Wacaser
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Patent number: 9553154Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein the memory gate structure comprises a memory gate electrode and a memory gate spacer, and wherein the memory gate electrode is an L-shaped structure, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.Type: GrantFiled: June 5, 2015Date of Patent: January 24, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Ming Wu, Shih-Chang Liu, Chia-Shiung Tsai
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Patent number: 9553155Abstract: In an embodiment, a semiconductor device includes a High Electron Mobility Transistor (HEMT) including a floating gate. The floating gate includes two or more electrically separated floating gate segments.Type: GrantFiled: February 4, 2015Date of Patent: January 24, 2017Assignee: Infineon Technologies Austria AGInventors: Matthias Strassburg, Gerhard Prechtl
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Patent number: 9553156Abstract: Provided are an organic light emitting display device and a method of manufacturing the organic light emitting display device according to an exemplary embodiment of the present disclosure. The organic light emitting display device includes: a substrate including a display area and a pad area; a pad electrode structure on the substrate in the pad area and including a first pad electrode and a second pad electrode on the first pad electrode; and a protection conductive layer covering a lateral surface of the second pad electrode so as to reduce corrosion of the second pad electrode.Type: GrantFiled: July 16, 2015Date of Patent: January 24, 2017Assignee: LG Display Co., Ltd.Inventors: Binn Kim, TaeHwan Kim
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Patent number: 9553157Abstract: A device is created by forming a layer of dielectric material on a silicon-containing region of a semiconductor substrate. An opening is created through the layer of dielectric material, the opening having a bottom and exposing the silicon-containing region. A metal stack is formed within the opening. The metal stack includes at least a first metal film on the silicon-containing region and a second gettering metal film on the first metal film. The metal stack is annealed to cause oxygen to migrate from the substrate to the gettering metal film. A first liner is formed within the opening. A fill metal is deposited in the opening.Type: GrantFiled: October 7, 2015Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Emre Alptekin, Ahmet S. Ozcan, Viraj Y. Sardesai, Kathryn T. Schonenberg, Cung D. Tran
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Patent number: 9553158Abstract: Embodiments of the invention provide a conductive structure, a thin film transistor, an array substrate, and a display device. The conductive structure comprises a copper layer formed of copper or copper alloy; a blocking layer for preventing copper ions of the copper layer from diffusing outward; and a diffusion prevention layer for preventing exterior ions from diffusing to the copper layer and disposed between the copper layer and the blocking layer. The multilayer conductive structure according to an embodiment of the invention can prevent exterior ions from diffusing into a copper layer and prevent copper ions from diffusing outward to reduce ions diffusion that adversely impacts the electricity performance and chemical corrosion resistance of the copper metal layer, and meanwhile can enhance adhesiveness of the conductive structure, which may be helpful for etching/patterning of the multilayer conductive structure.Type: GrantFiled: October 17, 2012Date of Patent: January 24, 2017Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Jaemoon Chung, Qiuping Huang, Seong Sil Im, Dongseob Kim, Chao-Huan Hsu, Huawei Xu, Zhengwei Chen, Jianshe Xue
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Patent number: 9553159Abstract: A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.Type: GrantFiled: November 3, 2015Date of Patent: January 24, 2017Assignee: SK HYNIX INC.Inventors: Kyong Bong Rouh, Yong Seok Eun, Young Jin Son
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Patent number: 9553160Abstract: Embodiments of mechanisms of monitoring metal impurity in a high-k dielectric film are provided. The method includes forming an interfacial layer over a substrate. The method also includes forming a high-k dielectric film on the interfacial layer, and the interfacial layer and the high-k dielectric film form a stacked structure over the substrate. The method further includes conducting the first thickness measurement on the stacked structure. In addition, the method includes performing a treatment to the stacked structure after the first thickness measurement, and the treatment includes an annealing process. The method also includes conducting the second thickness measurement on the stacked structure after the treatment.Type: GrantFiled: October 9, 2013Date of Patent: January 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Jen Chen, Yen-Yu Chen, Chang-Sheng Lee, Wei Zhang
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Patent number: 9553161Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate and forming a metal gate stack including a metal gate electrode over the semiconductor substrate. The method also includes applying an oxidizing solution containing an oxidizing agent over the metal gate electrode to oxidize the metal gate electrode to form a metal oxide layer on the metal gate electrode.Type: GrantFiled: June 22, 2015Date of Patent: January 24, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Jen Liu, Li-Chieh Wu, Shich-Chang Suen, Liang-Guang Chen
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Patent number: 9553162Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A conductive layer can be formed over the encapsulant and the semiconductor die. A transmissive layer can be formed over the semiconductor die. An interconnect structure can be formed through the encapsulant and electrically connected to the conductive layer, whereby the interconnect structure is formed off to only one side of the semiconductor die.Type: GrantFiled: March 29, 2013Date of Patent: January 24, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Thomas J. Strothmann, Steve Anderson, Byung Joon Han, Il Kwon Shim, Heap Hoe Kuan