Patents Issued in January 24, 2017
  • Patent number: 9553163
    Abstract: In one aspect, a diode comprises: a semiconductor layer having a first side and a second side opposite the first side, the semiconductor layer having a thickness between the first side and the second side, the thickness of the semiconductor layer being based on a mean free path of a charge carrier emitted into the semiconductor layer; a first metal layer deposited on the first side of the semiconductor layer; and a second metal layer deposited on the second side of the semiconductor layer.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: January 24, 2017
    Assignee: Carnegie Mellon University
    Inventors: Rozana Hussin, Yixuan Chen, Yi Luo
  • Patent number: 9553164
    Abstract: A method for manufacturing an IGBT, comprising: providing a substrate having a first surface and a second surface and of a first or second type of electrical conductance; forming grooves at intervals on the first surface of the substrate; filling a semiconductor material of the second or first type of electrical conductance into the grooves to form channels, where the type of electrical conductance of the channels is different from the type of electrical conductance of the substrate; bonding on the first surface of the substrate to form a drift region of the second type of electrical conductance; forming a front-side structure of the IGBT on the basis of the drift region; thinning the substrate starting from the second surface of the substrate until the channels are exposed; and forming a rear-side metal electrode on the channels and the thinned substrate.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: January 24, 2017
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Xuan Huang, Wanli Wang, Genyi Wang
  • Patent number: 9553165
    Abstract: In one embodiment, an IGBT is formed to include a plurality of termination trenches in a termination region of the IGBT. An embodiment may include that one end of one or more termination trenches may be exposed on one surface of the semiconductor device.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: January 24, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. Grivna, Ali Salih
  • Patent number: 9553166
    Abstract: A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 24, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Pranita Kerber, Effendi Leobandung, Amlan Majumdar, Renee T. Mo, Yanning Sun
  • Patent number: 9553167
    Abstract: A semiconductor device is disclosed. The semiconductor device comprising: a semiconductor substrate having first type conductivity and including an active region and a device isolation film, a doping layer having second type conductivity and buried in a bottom part of the semiconductor substrate of the active region, a recess formed in the semiconductor substrate, a gate electrode provided in the recess.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: January 24, 2017
    Assignee: SK Hynix Inc.
    Inventor: Kyoung Chul Jang
  • Patent number: 9553168
    Abstract: The present technology includes a semiconductor memory device, including a channel layer and interlayer insulation layers surrounding the channel layer. The interlayer insulation layers are stacked with a trench interposed therebetween. A seed pattern is formed on a surface of the trench and a metal layer is formed on the seed pattern in the trench.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: January 24, 2017
    Assignee: SK Hynix Inc.
    Inventor: Sang Hyon Kwak
  • Patent number: 9553169
    Abstract: The present invention provides a method for manufacturing an AMOLED backplane, in which after a first metal layer is patternized to form a first gate terminal (61), a second gate terminal (63), and an electrode plate (65), with the patternized first metal layer as a shielding layer, a patternized polysilicon layer is subjected to N-type light doping; and then, an insulation layer (7) is deposited and the insulation layer (7) is subjected to non-isotropic etching to form spacers (71), and with patternized first metal layer and the spacers (71) as a shielding layer, the patternized polysilicon layer is subjected to N-type heavy doping to form light-doping drain areas (N?) exactly below the spacers (71) on the opposite sides of the first gate terminal (61), whereby light-doping drain areas (N?) on opposite sides of a channel area of a switching TFT are made symmetric to each other and the length of the light-doping drain areas (N?) is shorten; a conduction current is increased; a photoelectric current can be eff
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: January 24, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Yuanjun Hsu
  • Patent number: 9553170
    Abstract: A manufacturing method of a thin film transistor and a thin film transistor are provided. In the manufacturing method, formation of pattern of a source electrode (7), a drain electrode (8) and an active layer (6) comprises: forming a semiconductor layer (10) and a conductive layer (11) that cover the whole substrate on the substrate in sequence; forming a first photoresist layer (4) at a region where the source electrode is to be formed and at a region where the drain electrode is to be formed on the conductive layer (11), respectively; forming a second photoresist layer (5) at least at a gap between the source electrode and the drain electrode that are to be formed on the conductive layer (11); conducting an etching process on the substrate with the first photoresist layer (4), the second photoresist layer (5), the semiconductor layer (10) and the conductive layer (11) formed thereon, so as to form pattern of the active layer (6), the source electrode (7) and the drain electrode (8).
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: January 24, 2017
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Xuecheng Hou, Tao Wu, Jian Guo
  • Patent number: 9553171
    Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a substrate and a first fin structure extending above the substrate. The FinFET also includes a first transistor formed on the first fin structure. The first transistor includes a first gate dielectric layer conformally formed on the first fin structure and a first gate electrode formed on the first gate dielectric layer. The FinFET further includes an inter-layer dielectric (ILD) structure formed adjacent to the first transistor. The first gate electrode is in direct contact with a sidewall of the ILD structure.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Yung-Jung Chang
  • Patent number: 9553172
    Abstract: A semiconductor device and a method of forming the same are disclosed. The method includes receiving a substrate having a fin projecting through an isolation structure over the substrate; etching a portion of the fin, resulting in a trench; forming a doped material layer on sidewalls of the trench; and growing at least one epitaxial layer in the trench. The method further includes exposing a first portion of the at least one epitaxial layer over the isolation structure; and performing an annealing process, thereby driving dopants from the doped material layer into a second portion of the at least one epitaxial layer. The first portion of the at least one epitaxial layer provides a strained channel for the semiconductor device and the second portion of the at least one epitaxial layer provides a punch-through stopper.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Patent number: 9553173
    Abstract: A field effect transistor device comprises a semiconductor substrate, a doped source layer arranged on the semiconductor substrate, an insulator layer arranged on the doped source layer, a fin arranged on the insulator layer, a source region extension portion extending from the doped source layer and through the fin, a gate stack arranged over a channel region of the fin and adjacent to the source region extension portion, a drain region arranged on the fin adjacent to the gate stack; the drain region having a graduated doping concentration.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chung H. Lam, Chung-hsun Lin, Darsen D. Lu, Philip J. Oldiges
  • Patent number: 9553174
    Abstract: Embodiments of the present invention provide methods for forming fin structure with desired materials using a conversion process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming a fin structure on a substrate includes performing an directional plasma process on a fin structure formed from a substrate comprising a first type of atoms, the directional plasma process dopes a second type of atoms on sidewalls of the fin structure, performing a surface modification process to form a surface modified layer on the sidewalls of the fin structure reacting with the first type of atoms, replacing the first type of the atoms with the second type of the atoms in the fin structure during the surface modification process, and forming the fin structure including the second type of the atoms on the substrate.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: January 24, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ludovic Godet, Christopher Hatem, Matthew D. Scotney-Castle, Martin A. Hilkene
  • Patent number: 9553175
    Abstract: A method includes forming a first oxide layer. The method further includes etching a portion of the first oxide layer using a first decoupled plasma nitridation process. The method includes forming, subsequent to the etching, a charge-trapping layer on the first oxide layer.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: January 24, 2017
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Helmut Puchner, Igor Polishchuk, Sagy Charel Levy
  • Patent number: 9553176
    Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: January 24, 2017
    Assignee: Industrial Technology Research Institute
    Inventors: Jing-Yi Yan, Chih-Chieh Hsu, Hsiao-Chiang Yao, Chu-Yin Hung
  • Patent number: 9553177
    Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn
  • Patent number: 9553178
    Abstract: A semiconductor component includes a first emitter zone of a first conductivity type, a second emitter zone of a second conductivity type, a first base zone arranged between the first and second emitter zones and a first control structure. The first control structure includes a control electrode arranged adjacent the first emitter zone, the control electrode being insulated from the first emitter zone by a first dielectric layer and extending in a current flow direction of the semiconductor component. The first control structure includes a first control connection and at least one first connection zone arranged between the first control connection and the control electrode and comprising a semiconductor material.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: January 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze
  • Patent number: 9553179
    Abstract: A semiconductor device includes a semiconductor mesa which is formed between cell trench structures extending from a first surface into a semiconductor body. The semiconductor mesa includes a body zone forming a first pn junction with a drift zone between the body zone and a second surface opposite to the first surface. Source zones are arranged along a longitudinal axis of the semiconductor mesa at a first distance from each other and form second pn junctions with the body zone. A barrier structure, which has the conductivity type of the source zones, forms at least one of a unipolar homojunction with the drift zone and a pn junction with the body zone at least outside a vertical projection of the source zones perpendicular to the first surface. The barrier structure may be absent in the vertical projection of the source zones.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 24, 2017
    Assignee: Infineon Technologies AG
    Inventors: Antonio Vellei, Johannes Georg Laven, Roman Baburske, Alexander Philippou
  • Patent number: 9553181
    Abstract: The present disclosure presents a novel structure for a dielectric material for use with Group III-V material systems and a method of fabricating such a structure. More specifically, the present disclosure describes a novel dielectric layer that is formed on the top surface of a III-V material where the dielectric layer comprises a first region in contact with the top surface of the III-V material crystalline and a second region adjacent to the first region and at the upper side of the dielectric layer. The dielectric layer has material properties different from traditional dielectric layers as it is composed of both crystalline and amorphous structures. The crystalline structure is at the interface with the III-V material (such as AlGaN or GaN) but gradually transitions into an amorphous structure, both within the same layer and both comprising the same material.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: January 24, 2017
    Assignee: Toshiba Corporation
    Inventor: Long Yang
  • Patent number: 9553182
    Abstract: A circuit structure includes a substrate, a III-V semiconductor compound over the substrate, a AlxGa(1?X)N (AlGaN) layer over the III-V semiconductor compound, a gate over the AlGaN layer, a passivation film over the gate and over a portion of the AlGaN layer, a source structure, and a drain structure on an opposite side of the gate from the source structure, wherein X ranges from 0.1 to 1. The source structure has a source contact portion and an overhead portion. The overhead portion is over at least a portion of the passivation film between the source contact portion and the gate. A distance between the source contact portion and the gate is less than a distance between the gate and the drain structure.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Lei Jerry Yu, Fu-Wei Yao, Chen-Ju Yu, Chun-Wei Hsu, King-Yuen Wong
  • Patent number: 9553183
    Abstract: A normally-off compound semiconductor transistor includes a heterostructure body and a gate stack on the heterostructure body. The heterostructure body includes a source, a drain spaced apart from the source, and a channel for connecting the source and the drain. The channel includes a first two-dimensional charge carrier gas of a first polarity arising in the heterostructure body due to piezoelectric effects. The gate stack controls the channel in a region of the heterostructure body under the gate stack. The gate stack includes at least one III-nitride material which gives rise to a second two-dimensional charge carrier gas of a second polarity opposite the first polarity in the gate stack or in the heterostructure body under the gate stack due to piezoelectric effects. The second two-dimensional charge carrier gas counter-balances polarization charges in the first two-dimensional charge carrier gas so that the channel is disrupted under the gate stack.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: January 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Gilberto Curatola
  • Patent number: 9553184
    Abstract: A semiconductor device includes a semiconductor layer disposed at a substrate and a plurality of active cells disposed at the semiconductor layer. Each active cell includes a trench extending into the semiconductor layer and a body region disposed in the semiconductor layer adjacent to a sidewall of the trench and at a first depth below the surface of the semiconductor layer. The semiconductor device further includes a termination cell disposed at the semiconductor layer adjacent to an edge of the plurality of active cells. The termination cell includes a trench extending into the semiconductor layer, and further includes a body region disposed in the semiconductor layer adjacent to a sidewall of the trench of the termination cell and at a second depth less than the first depth. The body regions of the active cells and of the termination cell have a conductivity type different than that of the semiconductor layer.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 24, 2017
    Assignee: NXP USA, INC.
    Inventors: Moaniss Zitouni, Edouard de Frésart, Pon Sung Ku, Ganming Qin
  • Patent number: 9553185
    Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: January 24, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kin-On Sin, Chun-Wai Ng, Hitoshi Sumida, Yoshiaki Toyada, Akihiko Ohi, Hiroyuki Tanaka, Takeyoshi Nishimura
  • Patent number: 9553186
    Abstract: Embodiments of a manufacturing process for recessed gate devices on silicon-on-insulator (SOI) substrate with self-aligned lateral isolation are described. This allows the creation of true in-pitch recessed gate devices without requiring an extra isolation dimension. A lateral isolation trench is formed between pairs of recessed gate devices by etching the silicon-on-insulator area down to a buried oxide layer on which the silicon-on-insulator layer is formed. The position of the trench is self-aligned and defined by the gate width and the dimension of spacers disposed on either side of the gate. The isolation trench is filled with a dielectric material and then etched back to the middle of the SOI body and the remaining volume is filled with a doped conductive material. The doped conductor is subject to a thermal cycle to create source and drain regions of the device through out-diffusion of the doped material.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: January 24, 2017
    Inventor: John Kim
  • Patent number: 9553187
    Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a body well region having a first conductivity type, a drift region and a source region each having a second conductivity type, where a channel portion of the body well region resides laterally between the source region and a first portion of the drift region that is adjacent to the channel portion. A gate structure overlies the channel portion and the adjacent portion of the drift region. A portion of the gate structure overlying the channel portion proximate the source region has the second conductivity type. Another portion of the gate structure that overlies the adjacent portion of the drift region has a different doping, and overlaps at least a portion of the channel portion, with the threshold voltage associated with the gate structure being influenced by the amount of overlap.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: January 24, 2017
    Assignee: NXP USA, Inc.
    Inventors: Weize Chen, Richard J. De Souza, Mazhar Ul Hoque, Patrice M. Parris
  • Patent number: 9553188
    Abstract: A high-voltage semiconductor device includes a semiconductor substrate, a gate structure, a drain, an insulation structure, and a plurality of conductive structures. The insulation structure is disposed in the semiconductor substrate and disposed between the gate structure and the drain. The insulation structure includes a plurality of insulation units disposed separately from one another. Each of the conductive structures is embedded in one of the insulation units.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: January 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lingzi Li, Zhaobing Li, Hui Lu, Zhang Hu Sun
  • Patent number: 9553189
    Abstract: According to certain embodiments, a silicide layer is formed after the fabrication of a functional gate electrode using a gate-last scheme. An initial semiconductor structure has at least one impurity regions formed on a semiconductor substrate, a sacrifice film formed over the impurity region, an isolation layer formed over the sacrifice film and a dielectric layer formed over the isolation film. A via is patterned into the dielectric layer of the initial semiconductor structure and through the thickness of the isolation layer such that a contact opening is formed in the isolation layer. The sacrifice film underlying the isolation layer is then removed leaving a void space underlying the isolation layer. Then, a metal silicide precursor is placed within the void space, and the metal silicide precursor is converted to a silicide layer through an annealing process.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: January 24, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Uozumi
  • Patent number: 9553190
    Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: January 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keum Seok Park, Jungho Yoo, Jinyeong Joe, Bonyoung Koo, Dongsuk Shin, Hongsik Yoon, Byeongchan Lee
  • Patent number: 9553191
    Abstract: A method of fabricating a FinFET includes at last the following steps. A semiconductor substrate is patterned to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin between the trenches. Insulators are formed in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. A strained material doped with a conductive dopant is formed over portions of the semiconductor fin revealed by the gate stack, and the strained material is formed by selectively growing a bulk layer with a gradient doping concentration.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-I Liao, Mon-Nan How, Shih-Chieh Chang, Ying-Min Chou, Ting-Chang Chang
  • Patent number: 9553192
    Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: January 24, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-hoon Kim, Jin-bum Kim, Kwan-heum Lee, Byeong-chan Lee, Cho-eun Lee, Su-jin Jung
  • Patent number: 9553193
    Abstract: A semiconductor device is provided that includes a fin having a first upper gate on a sidewall of the fin in a first trench and a second upper gate formed on the opposite sidewall of the fin. The device also includes a first lower gate on the sidewall and a second lower gate on the opposite sidewall, wherein the first upper gate is formed above the first lower gate and the second upper gate is formed above the second lower gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first upper gate and second upper gate to preselect the transistors of a fin and then biasing the first lower gate and second lower gate to operate the transistors of the fin.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 9553194
    Abstract: A method can include performing an etching process to define a fin trench having a first depth, the first depth being less that a target height of fin. A method can also include forming a layer to protect sidewalls defining the fin trench. A method can also include performing a second etching process to increase a depth of fin trench.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Nicholas Vincent Licausi, Zhenyu Hu, Hong Yu, Jinping Liu
  • Patent number: 9553195
    Abstract: The present invention generally relates to a method of manufacturing a TFT. The TFT has an active channel that comprises IGZO or zinc oxide. After the source and drain electrodes are formed, but before the passivation layers or etch stop layers are deposited thereover, the active channel is exposed to an N2O or O2 plasma. The interface between the active channel and the passivation layers or etch stop layers are either altered or damaged during formation of the source and drain electrodes. The N2O or O2 plasma alters and repairs the interface between the active channel and the passivation or etch stop layers.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: January 24, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Jrjyan Jerry Chen, Soo Young Choi, Dong-Kil Yim, Yan Ye
  • Patent number: 9553196
    Abstract: The present invention discloses a multi-gate thin film transistor for realizing a multi-gate occupying a small area, pixels provided with the multi-gate TFTs are high in aperture ratio, and a display device provided with the multi-gate TFTs is high in resolution. The multi-gate thin film transistor comprises: at least three gate electrodes; a plurality of active layers corresponding to each of the gate electrodes, respectively, the active layers being formed into an integrated structure; a source electrode connected with one of the plurality of active layers; and a plurality of drain electrodes connected with each of the remainder of the plurality of active layers, respectively. The present invention further discloses an array substrate comprising the multi-gate thin film transistor, and a display device.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: January 24, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Tuo Sun
  • Patent number: 9553197
    Abstract: A thin film transistor includes: a lower gate electrode on a substrate; a gate insulating layer on the lower gate electrode; a first semiconductor layer on the gate insulating layer; a source electrode on the first semiconductor layer, a drain electrode on the first semiconductor layer and spaced apart form the source electrode; a second semiconductor layer on a channel region of the first semiconductor layer and on the source electrode and the drain electrode; a passivation layer on the second semiconductor layer; and an upper gate electrode disposed on the passivation layer, corresponding to the channel region.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joon Seok Park, Bosung Kim, Changjung Kim
  • Patent number: 9553198
    Abstract: The present invention provides a TFT substrate structure and a manufacturing method thereof. The TFT substrate structure of the present invention includes an N-type lightly-doped amorphous silicon layer and an N-type heavily-doped amorphous silicon layer arranged between an amorphous silicon layer and a metal layer to form a gradient of doping concentration so as to reduce the potential barrier between the metal layer and the amorphous silicon layer, making injection of electrons easy and reducing the leakage current without lowering an operation current, thereby improving the electrical property of the TFT.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: January 24, 2017
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaowen Lv
  • Patent number: 9553199
    Abstract: Semiconductor devices and methods of forming the same are provided. A source/drain electrode stack is formed over a substrate, wherein the source/drain electrode stack comprises a first source/drain electrode and a second source/drain electrode. A source/channel/drain layer is formed on a sidewall of the source/drain electrode stack, wherein the source/channel/drain layer comprises a 2D material. A gate stack is formed on the source/channel/drain layer.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: January 24, 2017
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Tuo-Hung Hou, Samuel C. Pan
  • Patent number: 9553200
    Abstract: An oxide semiconductor layer is formed, a gate insulating layer is formed over the oxide semiconductor layer, a gate electrode layer is formed to overlap with the oxide semiconductor layer with the gate insulating layer interposed therebetween, a first insulating layer is formed to cover the gate insulating layer and the gate electrode layer, an impurity element is introduced through the insulating layer to form a pair of impurity regions in the oxide semiconductor layer, a second insulating layer is formed over the first insulating layer, the first insulating layer and the second insulating layer are anisotropically etched to form a sidewall insulating layer in contact with a side surface of the gate electrode layer, and a source electrode layer and a drain electrode layer in contact with the pair of impurity regions are formed.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: January 24, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Sachiaki Tezuka, Shinji Ohno
  • Patent number: 9553201
    Abstract: The inventive concept relates to a thin film transistor and a thin film transistor array panel and, in detail, relates to a thin film transistor including an oxide semiconductor. A thin film transistor according to an exemplary embodiment of the inventive concept includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a first semiconductor and a second semiconductor that overlap the gate electrode with the gate insulating layer interposed therebetween, the first semiconductor and the second semiconductor contacting each other; a source electrode connected to the second semiconductor; and a drain electrode connected to the second semiconductor and facing the source electrode, wherein the second semiconductor includes gallium (Ga) that is not included in the first semiconductor, and a content of gallium (Ga) in the second semiconductor is greater than 0 at. % and less than or equal to about 33 at. %.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: January 24, 2017
    Assignees: Samsung Display Co., Ltd., Kobe Steel, Ltd.
    Inventors: Byung Du Ahn, Ji Hun Lim, Gun Hee Kim, Kyoung Won Lee, Je Hun Lee, Hiroshi Goto, Aya Miki, Shinya Morita, Toshihiro Kugimiya, Yeon Hong Kim, Yeon Gon Mo, Kwang Suk Kim
  • Patent number: 9553202
    Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: January 24, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Katsuaki Tochibayashi, Tomoaki Moriwaka, Jiro Nishida, Hidekazu Miyairi, Shunpei Yamazaki
  • Patent number: 9553203
    Abstract: A display panel includes a base substrate including a pixel area and a peripheral area, a semiconductor layer disposed on a portion of the base substrate, a display element disposed in the pixel area, and a thin film transistor which controls the display element and includes an input electrode, an output electrode and a control electrode, in which the semiconductor layer includes a first portion disposed on the input electrode of the first thin film transistor, a second portion disposed on the output electrode of the first thin film transistor, and a third portion which connects the first portion and the second portion, overlaps the control electrode of the first thin film transistor, and defines a channel of the first thin film transistor.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: January 24, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Hwan Cho, Yoonho Khang, Hyunjae Na, Youngki Shin, Donghwan Shim
  • Patent number: 9553204
    Abstract: A semiconductor device excellent in writing operation is provided. In a structure where a data voltage supplied to a source line is supplied to a node of a memory cell via a bit line, a switch is provided between memory cells connected to the bit line. During a period in which the data voltage is supplied to the node of the memory cell, the switch on the bit line, which is provided between the memory cells, is off. With such a structure, parasitic capacitance of the bit line during a period in which the data voltage is supplied to the node of the memory cell can be reduced. As a result, writing of the data voltage into the memory cell can be performed fast.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: January 24, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takanori Matsuzaki, Tatsuya Onuki
  • Patent number: 9553205
    Abstract: To provide a semiconductor device having a high aperture ratio and including a capacitor with a high charge capacitance. To provide a semiconductor device with a narrow bezel. A transistor over a substrate; a first conductive film over a surface over which a gate electrode of the transistor is provided; a second conductive film over a surface over which a pair of electrodes of the transistor is provided; and a first light-transmitting conductive film electrically connected to the first conductive film and the second conductive film are included. The second conductive film overlaps the first conductive film with a gate insulating film of the transistor laid between the second conductive film and the first conductive film.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: January 24, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Kouhei Toyotaka
  • Patent number: 9553206
    Abstract: The present invention provides an EEPROM core structure embedded into BCD process and forming method thereof. The EEPROM core structure embedded into BCD process comprises a selection transistor and a storage transistor connected in series, wherein the selection transistor is an LDNMOS transistor. The present invention may embed the procedure for forming the EEPROM core structure into the BCD process, which is favorable to reduce the complexity of the process.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: January 24, 2017
    Assignee: ADVANCED SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jianhua Liu
  • Patent number: 9553207
    Abstract: A nonvolatile memory (“NVM”) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: January 24, 2017
    Assignee: Synopsys, Inc.
    Inventors: Andrew E. Horch, Troy N. Gilliland
  • Patent number: 9553208
    Abstract: A current sensor device for sensing a measuring current includes a semiconductor chip having a magnetic field sensitive element. The current sensor device further includes an encapsulant embedding the semiconductor chip. A conductor configured to carry the measuring current is electrically insulated from the magnetic field sensitive element. A redistribution structure includes a first metal layer having a first structured portion which forms part of the conductor.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: January 24, 2017
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Volker Strutz, Horst Theuss
  • Patent number: 9553209
    Abstract: The process is based upon the steps of: forming a trench in a body including a substrate and at least one insulating layer; and depositing a metal layer above the body for closing the open end or mouth of the trench. The trench is formed by selectively etching the body, wherein the reaction by-products deposit on the walls of the trench and form a passivation layer along the walls of the trench and a restriction element in proximity of the mouth of the trench.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 24, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Antonino Fiumara
  • Patent number: 9553210
    Abstract: High frequency power diode including a semiconductor wafer having first and second main sides, a first layer of a first conductivity type formed on the first main side, a second layer of a second conductivity type formed on the second main side and a third layer of the second conductivity type formed between the first layer and the second layer. The first layer has a dopant concentration decreasing from 1019 cm?3 or more adjacent to the first main side of the wafer to 1.5·1015 cm?3 or less at an interface of the first layer with the third layer. The second layer has a dopant concentration decreasing from 1019 cm?3 or more adjacent to the second main side of the wafer to 1.5·1015 cm?3 at an interface of the second layer with the third layer and the third layer has a dopant concentration of 1.5·1015 cm?3 or less.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: January 24, 2017
    Assignee: ABB Schweiz AG
    Inventors: Jaroslav Homola, Jiri Podzemsky, Ladislav Radvan, Ilja Muller
  • Patent number: 9553211
    Abstract: A Schottky barrier diode includes a first semiconductor layer, a LOCOS layer arranged in contact with the first semiconductor layer, a Schottky junction region provided on a contact surface between the first semiconductor layer and a first electrode, a second semiconductor layer connected to the first semiconductor layer and having a higher carrier concentration than that of the first semiconductor layer, and a second electrode forming an ohmic contact with the second semiconductor layer. In this case, the Schottky junction region and the LOCOS layer are in contact.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: January 24, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yasushi Koyama
  • Patent number: 9553212
    Abstract: An optical coupler includes an optical transmitting unit and an optical receiving unit in a facing arrangement. The optical transmitting unit includes a power lead having a first die-pad portion, a light emitting element on the first die-pad portion, a ground lead having a second die-pad portion, and an integrated circuit on the second die-pad portion. The integrated circuit has a power pad portion, a light emitting element pad portion, and input pad portions thereon. An inter-center distance between an inner lead of the first input lead and an inner lead of the second input lead is equal to or less than an inter-center distance between an outer lead of the first input lead and an outer lead of the second input lead.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: January 24, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuta Kugiyama
  • Patent number: 9553213
    Abstract: Disclosed are a solar cell apparatus, and a method of fabricating the same. The solar cell apparatus includes: dummy parts disposed on a support substrate; a plurality of solar cells disposed on the support substrate and disposed between the dummy parts; and a bus bar electrically connected to the solar cells and disposed between the support substrate and the dummy parts. Each of the solar cells and the dummy parts has a back electrode layer, a light absorbing layer, and a front electrode layer sequentially disposed on the support substrate.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: January 24, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Min Jung Shin