Abstract: A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read data from and write data to the array.

Abstract: A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes: a semiconductor body, source and drain formed in a semiconductor pillar; a gate insulating layer formed on a surface of the semiconductor body; a gate electrode formed on a surface of the gate insulating layer. The gate electrode includes a first gate electrode and a second gate electrode being electrically connected with the first gate electrode. The first gate electrode has a work function higher than that of the second gate electrode. Accordingly, the gate induced drain leakage (GIDL) can be reduced, so that an off-state leakage current can be greatly reduced.

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

Abstract: Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.

Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.

Abstract: A multi-chip package includes a plurality of semiconductor devices each having an address which is designated based on unique values corresponding to the respective semiconductor devices; and a controller suitable for activating each of the semiconductor devices based on the address, and controlling the activated semiconductor device to perform a normal operation.

Abstract: A memory apparatus and a memory accessing method are provided. The memory accessing method includes: calculating an accessed times of each of a plurality of word line addresses; setting each of the corresponding word line addresses as an aggressor word line address by comparing the accessed times of the each of the word line addresses and a threshold accessed times; and setting a backup word line address, and replacing memory cells of the aggressor word line address by memory cells of the backup word line address.

Abstract: Embodiments of the present invention relate to a latch circuit (L20) which latches a data mask signal (DM) in response to a one-shot signal (NS), and changes the data mask signal (DM) to an active level in response to an error signal (ERR), which indicates that an error is present in write data (DQ), being at an active level; a buffer circuit (BF2) which outputs the data mask signal (DM) that has been latched by the latch circuit (L20), said data mask signal (DM) being output in response to a write clock signal (WCLK2); and a main amplifier (80) which outputs the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit (BF2) is at an inactive level. The present invention can prevent the writing of erroneous write data, and is capable of preventing increased chip surface area.

Abstract: A semiconductor memory device which performs a refresh operation. The semiconductor memory device may include an information detection unit suitable for detecting a refresh characteristic of a memory cell, a control signal generation unit suitable for generating a refresh control signal having a refresh cycle corresponding to the refresh characteristic, and a refresh driving unit suitable for driving a refresh operation on the memory cell with the refresh cycle in response to the refresh control signal.

Abstract: The invention concerns a memory cell having: first and second cross-coupled gated inverters (102, 104), each including first and second inputs (IN1, IN2) and an output (OUT) and being adapted to couple its output to a first logic level only when the first and second inputs both receive the inverse of the first logic level; a first cut-off circuit (106) coupling the second input (IN2) of the first gated inverter (102) to the first input (IN1) of the first gated inverter (102); and a second cut-off circuit (108) coupling the second input (IN2) of the second gated inverter (104) to the first input (IN1) of the second gated inverter (104).

Abstract: A non-volatile SRAM cell comprises a first inverter, a second inverter, a first access transistor, a second access transistor, and a variable resistive element. The first inverter voltage is supplied by a first differential supply. The second inverter voltage is supplied by a second differential supply. The variable resistive element coupling with a third access transistor in series is coupled to the first output node. The non-volatile SRAM cell operates in a restore operation comprising a dual supply initialization phase and a pulse-overwrite phase. During the dual supply initialization phase, the first differential supply increases before the second differential supply so as to initialize the first output node to a logic state. During the pulse-overwrite phase, the third access transistor is turned on for a switch period in order to discharge/charge the first output node.

Abstract: A static random access memory (SRAM) includes a first bitcell and a second bitcell. The first bitcell includes an aging transistor and the second bitcell includes a non-aging transistor. An aging sensor is coupled between the first bitcell and the second bitcell to determine an amount of aging associated with the aging transistor. In one aspect, the amount of aging associated with the aging transistor is determined based on a difference between a voltage or current associated with the aging transistor and a voltage or current associated with the non-aging transistor.

Abstract: A static random access memory (SRAM) chip including a plurality of SRAM cells and a plurality of cell current tracking cells. Each of the SRAM cells include a source voltage reference conductor, a first ground reference conductor, two cross-coupled inverters, and two pass-gate devices. Each cell current tracking cell include a first half-cell and a second half-cell. The first half-cell is different from the second half-cell.

Abstract: Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. Certain embodiments provide a non-volatile solid-state memory array and a controller configured to receive write data from a host device, program the write data to a first block of the memory array in a lower-page-only (LPO) programming mode, and perform a data consolidation operation on the first block, wherein said performing garbage collection comprises programming at least a portion of the write data to a second block not in LPO programming mode.

Abstract: A non-volatile storage system includes a plurality of non-volatile storage elements arranged in two dimensional or three dimensional structures. The system applies programming to the non-volatile storage elements and performs verification of the programming. The verification includes performing a multi-strobe sensing operation to test for multiple data states while applying a common word line voltage.

Abstract: According to one embodiment, a memory device includes a controller; a first electrode and a second electrode connected to the controller; and a variable resistance layer provided between the first electrode and the second electrode. The variable resistance layer has a first structure, and a second structure. The controller configured to be able to perform a first operation of applying a first voltage between the first electrode and the second electrode, a second operation of applying a second voltage between the first electrode and the second electrode and determining whether or not the variable resistance layer has the second structure, and a third operation of applying a third voltage between the first electrode and the second electrode having the interposed variable resistance layer determined to not have the second structure in the second operation.

Abstract: Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address cycle. A memory system determines whether the individual memory cells or bits of a column at a bay can be skipped. For each sense amplifier group having at least one memory cell (or bit) that needs to be programmed, the system determines for the first column address whether the memory cell can be skipped. If a bit or memory cell having a first column address from the sense amplifier group can be skipped, the system determines a next bit having a column address from the group that needs to be programmed. The system groups the next column address for programming during the first column address cycle. The system can program a different column address for different sense amplifier groups within the bay during a single column address cycle.

Abstract: A memory circuit is described that includes an array of memory cells including a plurality of blocks. The circuit includes a controller including logic to execute program sequences for selected blocks in the plurality of blocks. The program sequences include patterns of program/verify cycles. The circuit includes logic to assign different patterns of program/verify cycles to different blocks in the plurality of blocks. The circuit includes logic to change a particular pattern assigned to a particular block in the plurality of blocks. The circuit includes logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks. The controller includes logic to apply a stress sequence to one of the selected blocks, the stress sequence including stress pulses applied to memory cells in the one of the selected blocks.

Abstract: A semiconductor memory device includes a semiconductor substrate having a main surface, at least a first dielectric layer on the main surface of the semiconductor substrate, a first OS FET device and a second OS FET device disposed on the first dielectric layer, at least a second dielectric layer covering the first dielectric layer, the first OS FET device, and the second OS FET device, a first MIM capacitor on the second dielectric layer and electrically coupled to the first OS FET device, and a second MIM capacitor on the second dielectric layer and electrically coupled to the second OS FET device.

Abstract: An associative memory circuit including a first memristor, a second memristor, a fixed value resistor R, and an operational comparator. One terminal of the first memristor is a first input terminal of the associative memory circuit, and the other terminal of the first memristor is connected to a first input terminal of the operational comparator. One terminal of the second memristor is a second input terminal of the associative memory circuit, and the other terminal of the second memristor is connected to the first input terminal of the operational comparator. One terminal of the fixed value resistor is connected to the first input terminal of the operational comparator, and the other terminal of the fixed value resistor is connected to the ground. A second input terminal of the operational comparator is connected to a reference voltage.

Abstract: For a non-volatile memory device having a NAND type of architecture, techniques are presented for determining NAND strings that are slow to program, including comparing the amount of current drawn by different sets of memory cells during different write operations. These techniques are particularly applicable to memory devices have a 3D structure, such as of BiCS type, where the slow programming can arise from defects of the spacing between the memory holes, in which the NAND strings are formed, and the local interconnects, such as for connecting common source lines and which run in a vertical direction between groups of NAND strings. The slow to program NAND strings can be recorded and this information can be used when writing data to the NAND strings. Several methods of writing data along a word line that includes such slow to program cells are described.

Abstract: A semiconductor device includes memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of pages, and an operation circuit suitable for outputting operating voltages to local lines of the memory blocks to perform a program loop, an erase loop and a read operation on the plurality of memory cells, wherein the operation circuit is suitable for applying a dummy pulse having a positive potential to the local lines after the program loop or the erase loop is completed.

Abstract: A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

Abstract: Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic level of a command signal line to generate a command signal to control circuitry of the integrated circuit device having the logic level of the command signal line when the output signal indicates that the operation is not being performed, and having a particular logic level when the output signal indicates that the operation is being performed. Integrated circuit devices include a command signal management circuit to provide a logic level of a particular command signal to control circuitry of the integrated circuit device when control signals indicate a desire to allow the particular command signal, and to provide a particular logic level to the control circuitry when the control signals indicate a desire to block the particular command signal.

Abstract: Disclosed is a semiconductor device, including: a memory block including a plurality of memory strings, each of the memory strings including a drain select transistor coupled to a bit line, a source select transistor coupled to a common source line, memory cells coupled to the drain select transistor and the source select transistor, and dummy memory cells coupled to the drain select transistor and the memory cell; and an operation circuit configured to perform a program operation on the memory cells. The operation circuit generates operation voltages applied to the dummy memory cells so that electric charges are generated by a band to band tunneling effect in the dummy memory cell adjacent to the drain select transistor during the program operation.

Abstract: A semiconductor device according to an embodiment comprises: a field effect transistor comprising a semiconductor layer and a gate electrode; a wiring line layer positioned above the field effect transistor; and a control circuit that adjusts a voltage of a wiring line in the wiring line layer. The wiring line layer comprises: a contact wiring line connected to a source or a drain of the field effect transistor; and a first wiring line facing a position between the gate electrode and the contact wiring line, of the semiconductor layer. The control circuit adjusts the contact wiring line to a certain voltage and sets the first wiring line to a floating state.

Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.

Abstract: Techniques are provided for reducing current consumption while programming non-volatile storage. A smart verify is performed using a subset of memory cells. By applying the smart verify to just a subset of the memory cells current is saved. The smart verify may be used to characterize programming speed. Results of the smart verify may be used to determine a magnitude of a dummy program pulse to be applied later in the programming process. The dummy program pulse is not followed by a program verify, which reduces current. If the dummy program pulse pushes threshold voltages high enough, then those memory cells will not conduct a current when verifying later in programming. Thus, current is saved during the program verify. Also, bit lines of memory cells that received the dummy pulses do not need to be pre-charged prior to a program pulse, which can save more current.

Abstract: A sensing voltage may be applied to a particular memory cell that is in a particular layer of a plurality of layers of memory cells. While the sensing voltage is applied to the particular memory cell, a source voltage may be applied to an end of a string of memory cells that includes the particular memory cell. The source line voltage may be based on a programming rate of the particular layer.

Abstract: A semiconductor memory device includes a memory cell, and a control circuit configured to execute a writing operation on the memory cell in response to a write command. The writing operation includes a first operation in which a first initial program voltage is applied and a second operation in which a second initial program voltage higher than the first initial program voltage is applied. The control circuit, in response to a status inquiry command, outputs a first signal when the status inquiry command is received during execution of the first operation, and outputs a second signal which is different from the first signal when the status inquiry command is received during execution of the second operation.

Abstract: In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time, wherein the program loop includes a programming step for programming selected memory cells among the memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In the programming the selected memory cells, a level of a voltage being applied to a common source line connected to the strings in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.

Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell array configured to include memory cells, a peripheral circuit configured to perform an erase operation and a soft program operation and a control circuit configured to control the peripheral circuit so that the memory cells are programmed though a hot carrier injection HCI method when the soft program operation is performed.

Abstract: A non-volatile memory device includes a memory array with memory cells arranged in rows and columns. Each cell has respective current-conduction regions and a control-gate region. The control-gate regions of the memory cells of a same row are coupled to a control-gate terminal and biased at a respective control-gate voltage. A control-gate decoder selects and biases the control-gate regions of the rows at respective control voltages according to operations to be performed on the memory cells. The current-conduction regions of the memory cells are arranged within a same bulk well, and the control-gate decoder has a number of driver blocks each of which supplies the control-gate voltages to a respective number of rows of the array. The driver blocks are provided in respective biasing wells, separate and distinct from one another.

Abstract: Provided herein is a semiconductor memory device including a memory cell array including a drain select transistor and a plurality of memory cells, a voltage generator configured to apply a program voltage, first and second pass voltages, and a drain control voltage to the memory cell array, a control logic configured to control the voltage generator so that during a program operation, after the program voltage is applied to a selected one of the plurality of memory cells, the program voltage applied to the selected memory cell is discharged while the first pass voltage or the second pass voltage is applied to memory cells adjacent to the selected memory cell.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for adjusting a voltage level for a write operation on a partially programmed block of a nonvolatile storage device. A write module receives a request to perform a write operation for one or more storage cells of an partially programmed block of a nonvolatile storage device. A characteristic module determines whether a characteristic for a partially programmed block of a nonvolatile storage device satisfies a threshold. A voltage adjustment module adjusts a voltage level applied to one or more source lines connected to the one or more storage cells during a write operation in response to determining a characteristic satisfies a threshold.

Abstract: Systems and methods of sequentially accessing memory cells in a nonvolatile memory device (NVM) are provided. The NVM has a plurality of strings and a common signal line coupled to the plurality of strings. Each string includes a plurality of memory cells and a selection transistor coupled between the plurality of memory cells and the common signal line. A command that accesses multiple memory cells is received, a voltage is applied to a first selection transistor of a first string to electrically connect the common signal line to the first string, a pulse is applied for a predetermined time period to selection transistors of other strings, and memory cells of the first string are accessed. Advantages such as removal of boosting charges from unselected strings prior to sequentially accessing memory cells from selected strings can improve performance and reliability of NVM-based systems.

Abstract: A trimmable current reference generator for use in a sense amplifier is disclosed.

Abstract: The disclosure provides a NAND flash memory and a reading method thereof, which may read a negative threshold value of a memory cell without using a negative-voltage-generating circuit. The disclosed NAND flash memory includes a sense amplifier, a bit line selecting circuit and an array having a plurality of NAND string units. The disclosed NAND flash memory includes a ?V supplying portion element that applies a positive voltage to a source line, a P well formed with a selected memory cell, and a non-selected bit line which is adjacent to a selected bit line, within a predetermined time period, after the selected bit line is pre-charged and during a reading process.

Abstract: A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.

Abstract: The present invention relates to a flash memory device that uses dummy memory cells as source line pull down circuits. In one embodiment, when a memory cell is in read mode or erase mode, its source line is coupled to ground through a bitline of a dummy memory cell, which in turn is coupled to ground. When the memory cell is in program mode, the bitline of the dummy memory cell is coupled to an inhibit voltage, which places the dummy memory cell in a program inhibit mode that maintains the dummy memory cell in erased state.

Abstract: A method for operating a memory controller includes: performing a hard decision read operation to read hard decision data from a memory device; if a hard decoding for the hard decision data fails, assigning log likelihood ratio (LLR) values to cells falling in a plurality of voltage regions corresponding to a plurality of read reference voltages; performing a soft decision read operation based on the LLR values and a soft decoding for the soft decision data to generate an error free data; performing a read operation to read data from the memory device using each of the plurality of read reference voltages to generate raw data for each of the plurality of read reference voltages; and determining an optimal read reference voltage among the plurality of the read reference voltages based on the raw data and the error free data.

Abstract: A semiconductor storage device according to an embodiment includes a memory cell array including a plurality of memory cells. A plurality of word lines are connected to the memory cells. A plurality of bit lines are connected to one end of current paths of the memory cells. A sense amplifier part is connected to the bit lines. A data write operation includes a first write loop and a second write loop. The first write loop includes a first program operation and a first verify operation. The second write loop includes a second program operation and a second verify operation. The sense amplifier part discharges a voltage of at least one of the bit lines in the first verify operation. The sense amplifier part keeps voltages of the bit lines in the second verify operation.

Abstract: In one embodiment, the method includes receiving a read request for reading data from a memory area of the memory, and determining whether an identifier of the memory area is stored in one of the plurality of entries of a characteristic table. Each of the plurality of entries is associated with a different range of at least one memory area characteristic and each of the plurality of entries is associated with different read condition information. The method further includes obtaining the read condition information associated with the entry storing the identifier of the memory area if the determining determines the identifier is stored in one of the plurality of entries of the characteristic table, and controlling the memory to read data from the memory area using the obtained read condition information.

Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

Abstract: Technologies are provided for measuring a programming current (PC) for a memory cell (MC) of a one-time programmable read-only memory array. The MC includes a fuse equivalent circuit (FEC) that includes a first current path (CP) having a first node, a second CP having a fuse of the memory cell and a second node, and a third CP. The PC is split into a first current, a second current and a third current that flow over the first CP, the second CP, and the third CP, respectively. A first voltage applied along the first path is divided to generate a second voltage at the first node, and an output voltage generated by an operational amplifier controls the second current to maintain a third voltage at the second node at substantially the same value as the second voltage so that the second current has a sufficiently low value and does not burn the fuse.

Abstract: A shift register unit, a shift register, a display panel and a display. The shift register unit comprises a holding module for holding a high level at a pulling up (PU) node when the PU node is at a high level. With the present invention, the level at the PU node may be pulled up rapidly in a charging stage, and a PD node may also be ensured to be at a higher potential in a noise eliminating stage, which may eliminate noises at the PU node and a signal output terminal OUTPUT effectively, so that a picture quality may be enhanced.

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.

Abstract: A semiconductor device includes: memory blocks including main data storage units and cycling information storage units; a circuit group that performs a wear leveling operation on the memory blocks; and a control circuit that sets a threshold value based on the cycling information, and controls the circuit group so that the wear leveling operation is performed based on the set threshold value.

Abstract: A smart self-repair device includes an ARE array configured to store information on respective bits of a fail address in fuses; a self-repair control block configured to store a row address and a column address corresponding to a fail bit when a fail occurs, analyze a fail mode by comparing the fail address inputted in a test and the stored addresses, and output fail address information and row fuse set information or column fuse set information according to the fail mode; a data control block configured to output repair information to the ARE array according to the fail address information and the row fuse set information or the column fuse set information; and a rupture control block configured to control a rupture operation of the ARE array.

Abstract: A system and apparatus for controlled fusion in a field reversed configuration (FRC) magnetic topology and conversion of fusion product energies directly to electric power. Preferably, plasma ions are magnetically confined in the FRC while plasma electrons are electrostatically confined in a deep energy well, created by tuning an externally applied magnetic field. In this configuration, ions and electrons may have adequate density and temperature so that upon collisions they are fused together by the nuclear force, thus forming fusion products that emerge in the form of an annular beam. Energy is removed from the fusion product ions as they spiral past electrodes of an inverse cyclotron converter. Advantageously, the fusion fuel plasmas that can be used with the present confinement and energy conversion system include advanced (aneutronic) fuels.