Abstract: A semiconductor memory device may include a string including at least one drain select transistor, a plurality of first memory cells, a first connection element, a plurality of second memory cells, a second connection element, a plurality of third memory cells, and at least one source select transistor, wherein the at least one drain select transistor, the plurality of first memory cells, the plurality of second memory cells, the plurality of third memory cells, and the at least one source select transistor connected serially via the first connection element and the second connection element.

Abstract: A semiconductor memory device includes: a first string unit including first and second memory cell transistors; a second string unit including third and fourth memory cell transistors; a first word line coupled to gates of the first and third memory cell transistors; and a second word line coupled to gates of the second and fourth memory cell transistors. When the first string unit is selected and the first word line is selected, a first voltage is applied. The first voltage is larger than an initial value of the voltage in the step-up operation.

Abstract: An operating method of a non-volatile memory device having a string including a plurality of memory cells and a plurality of auxiliary cells, the plurality of memory cells and the plurality of auxiliary cells being connected in series, includes detecting a threshold voltage of at least one of the plurality of auxiliary cells and generating an output signal corresponding to a deterioration level of the plurality of memory cells, based on the threshold voltage.

Abstract: Apparatuses and methods for a non-volatile memory scheme are described herein. An example apparatus may include a memory block including a plurality of subblocks of memory cells and further may include a control unit. The control unit may be configured to program a first access line group of each subblock of the plurality of subblocks during a program operation and to program a second access line group of each subblock of the plurality of subblocks during the program operation responsive to programming the first access line group of each of the plurality of subblocks.

Abstract: The semiconductor device includes a memory block including programmed pages and non-programmed pages, a peripheral circuit configured to perform a read operation of the memory block, and a control circuit configured to control the peripheral circuit so that a read voltage is applied to a word line coupled to a selected page among the pages for the read operation, a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation, and a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation.

Abstract: In a method of programming a nonvolatile memory device, a program operation is performed on a selected memory cell coupled to a selected word line in response to a program command, a negative bias voltage is applied to the selected word line, a verification pass voltage is applied to an unselected word line after the negative bias voltage is applied to the selected word line, and a first program verification voltage, which is higher than the negative bias voltage and lower than a ground voltage, is applied to the selected word line.

Abstract: An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly.

Abstract: After a predetermined period of time in a life cycle of a flash memory device, a plurality of reliability values corresponding to a plurality of reads of one or more of the plurality of memory cells are generated; each of the reads using a variation of a predetermined read level voltage. An offset voltage is then identified, offset from the read level voltage. The offset voltage corresponds to a zero crossing point in the range of the reliability values. Once the offset voltage is identified, the read level voltage is set to a calibrated voltage based on the offset voltage.

Abstract: A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode.

Abstract: Disclosed herein are techniques for sensing multiple reference levels in non-volatile storage elements without changing the voltage on the selected word line. One aspect includes determining a first condition of a selected non-volatile storage element with respect to a first reference level based on whether a sensing transistor conducts in response to a sense voltage on a sense node. Then, a voltage on the source terminal of the sensing transistor is modified after determining the first condition with respect to the first reference level. A second condition of the selected non-volatile storage element is then determined with respect to a second reference level based on whether the sensing transistor conducts in response to the sense voltage on the sense node. This allows two different reference levels to be efficiently sensed. Dynamic power is saved due low capacitance of the sensing transistor relative to the sense node.

Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

Abstract: A semiconductor device includes: an electric fuse circuit including first electric fuses used as data bits and second electric fuses used as polarity bits; and a write circuit configured to selectively pass a current through the first electric fuses and the second electric fuses and thereby write data in the electric fuse circuit. The write circuit is configured to perform a first process when number of write bits included in write data is larger than a value obtained by dividing total number of bits in the write data by 2. The first process includes writing of inverted write data in a plurality of first electric fuses, and including writing of inversion data in one of the second electric fuses. The plurality of first electric fuses are part of the first electric fuses. The inverted write data is inverted data of the write data. The inversion data represents inversion.

Abstract: A scan driving circuit is disclosed, and the scan driving circuit has a pull-up control module, a pull-up module, a pull-down module, a pull-down maintaining module, a down-stream module and a bootstrap capacitor; when the pull-up control module generates a scan level signal, the pull-up control module and the pull-down maintaining module use a constant high-level voltage to avoid an electrical leakage phenomenon; and the pull down module uses a present-level scan signal to avoid the electrical leakage phenomenon. Thus, the electrical leakage phenomenon can be efficiently avoided.

Abstract: A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.

Abstract: A circuit may include a first sample node configured to provide a low precision sample of an input signal, a second sample node configured to store a high precision sample of an input signal, and a first switch circuit coupled between an input and the first sample node. The circuit may further include a second switch circuit coupled between the first sample node and the second sample node and configured to limit leakage current that could discharge the second sample node.

Abstract: A semiconductor device may be provided. The semiconductor device may include a failure information generation circuit configured to generate first failure information. The semiconductor device may include a first latch data generation circuit configured to include the first failure information into first latch data of a first block and configured to output the first latch data including the first failure information. The semiconductor device may include a data synthesis circuit configured to generate first synthesis data.

Abstract: A semiconductor device includes a semiconductor device, comprising a memory cell array including a plurality of memory cells connected to a first bit line and a second bit line, respectively, a page buffer group, and bit line selection circuits including a plurality of selection circuit blocks to connect the first bit lines or the second bit lines to the page buffer group, wherein each of the selection circuit blocks includes a first contact region and a second contact region to which the first and second bit lines coupled, and same bit lines of the first and second bit lines are coupled to contact regions adjacent to one another of the first and second contact regions included in bit line selection circuits adjacent to one another of the bit line selection circuits.

Abstract: The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.

Abstract: Various embodiments generally relate to a semiconductor device and a device for a semiconductor device, and more particularly, to a technology relating to a margin of a data retention time. The semiconductor device may include a repair detection unit configured to determine whether an inputted address is a repair address and output a repair detection signal. The semiconductor device may include a refresh control unit configured to simultaneously activate two or more word lines in response to a refresh command signal and sequentially activate the two or more word lines according to the repair detection signal.

Abstract: In one embodiment, the fuel bundle for a liquid metal cooled reactor includes a channel, a nose assembly secured to a lower end of the channel, and a plurality of fuel rods disposed within the channel. At least one of the fuel rods has at least one guard ring surround the fuel rod and spacing the fuel rod from adjacent fuel rods.

Abstract: A nuclear reactor includes a nuclear core comprising a fissile material, and a pressure vessel containing the nuclear core immersed in primary coolant water. Turbo pumps disposed in the pressure vessel provide active circulation of primary coolant water in the pressure vessel. Each turbo pump includes a turbine driving an impeller. A manifold plenum chamber is disposed in the pressure vessel, and is in fluid communication with inlets of the turbines of the turbo pumps. An electrically driven pump operatively connected with the manifold plenum chamber to pressurize the manifold plenum chamber with primary coolant water. The turbo pumps may be disposed in openings passing through the manifold plenum chamber. The pressure vessel may be vertically oriented and cylindrical, with a cylindrical riser oriented coaxially inside, and the manifold plenum chamber may be annular and disposed in a downcomer annulus defined between the cylindrical riser and the cylindrical pressure vessel.

Abstract: Illustrative embodiments provide for the operation and simulation of the operation of fission reactors, including the movement of materials within reactors. Illustrative embodiments and aspects include, without limitation, nuclear fission reactors and reactor modules, including modular nuclear fission reactors and reactor modules, nuclear fission deflagration wave reactors and reactor modules, modular nuclear fission deflagration wave reactors and modules, methods of operating nuclear reactors and modules including the aforementioned, methods of simulating operating nuclear reactors and modules including the aforementioned, and the like.

Abstract: A critical heat flux prediction device, a critical heat flux prediction method, a safety evaluation system, and a core monitoring system using the safety evaluation system can predict critical heat flux in a core of a reactor with a high degree of accuracy by obtaining a correlation plot distribution representing a relation of critical heat flux on a thermal equilibrium quality based on experimental data, approximating a correlation plot distribution through a logistic function that is a model function in which critical heat flux is expressed by a function of a thermal equilibrium quality, and obtaining a critical heat flux correlation of critical heat flux and a thermal equilibrium quality.

Abstract: Examples of apparatus and methods for transmutation of an element are disclosed. An apparatus can include a neutron emitter configured to emit neutrons with a neutron output, a neutron moderator configured to reduce the average energy of the neutron output to produce a moderated neutron output, a target configured to absorb neutrons when exposed to the moderated neutron output, the absorption of the neutrons by the target producing a transmuted element, and an extractor configured to extract the desired element. A method can include producing a neutron output, reducing the average energy of the neutron output with a neutron moderator to produce a moderated neutron output, absorbing neutrons from the moderated neutron output with the target to generate a transmuted element, and eluting a solution through the target to extract a desired element. In some examples, the target includes molybdenum-98, and the desired element includes technetium-99m.

Abstract: A system for radioisotope production uses fast-neutron-caused fission of depleted or naturally occurring uranium targets in an irradiation chamber. Fast fission can be enhanced by having neutrons encountering the target undergo scattering or reflection to increase each neutron's probability of causing fission (n, f) reactions in U-238. The U-238 can be deployed as one or more layers sandwiched between layers of neutron-reflecting material, or as rods surrounded by neutron-reflecting material. The gaseous fission products can be withdrawn from the irradiation chamber on a continuous basis, and the radioactive iodine isotopes (including I-131) extracted.

Abstract: A method for producing 99mTc may include: providing a solution comprising 100Mo-molybdate-ions; providing a proton beam having an energy suitable for inducing a 100Mo(p,2n)99mTc-nuclear reaction when exposing 100Mo-molybdate-ions; exposing the solution to the proton beams and inducing a 100Mo(p,2n)99mTc-nuclear reaction; and applying an extraction method for extracting the 99mTc from the solution. Further, a device for producing 99mTc may include: a solution with 100Mo-molybdate-ions; an accelerator for providing a proton beam with energy which is suitable for inducing a 100Mo(p,2n)99mTc-nuclear reaction when exposing 100Mo-molybdate-ions, for exposing the solution and for inducing a 100Mo(p,2n)99mTc-nuclear reaction; and an extraction step for extracting 99mTc from the solution.

Abstract: There are provided a metal material for electronic component which has low insertability/extractability, low whisker formability, and high durability, and a method for manufacturing the metal material. The metal material 10 for electronic components has a base material 11, an A layer 14 constituting a surface layer on the base material 11 and formed of Sn, In or an alloy thereof, and a B layer 13 constituting a middle layer provided between the base material 11 and the A layer 14 and formed of Ag, Au, Pt, Pd, Ru, Rh, Os, Ir or an alloy thereof, wherein the surface layer (A layer) 14 has a thickness of 0.002 to 0.2 ?m, and the middle layer (B layer) 13 has a thickness of 0.001 to 0.3 ?m.

Abstract: This invention relates to novel applications for alliform carbon, useful in conductors and energy storage devices, including electrical double layer capacitor devices and articles incorporating such conductors and devices. Said alliform carbon particles are in the range of 2 to about 20 percent by weight, relative to the weight of the entire electrode. Said novel applications include supercapacitors and associated electrode devices, batteries, bandages and wound healing, and thin-film devices, including display devices.

Abstract: A graphene-based laminate including a doped polymer layer is disclosed. The graphene-based laminate may include a substrate; a graphene layer disposed on the substrate and including at least one layer; and a doped polymer layer disposed on at least one surface of the graphene layer and including an organic dopant.

Abstract: A drive substrate, including: an insulating substrate (10); an internal connection terminal (12b) made of ITO or IZO provided on the substrate (10); and a lead interconnect (14) that is connected to the connection terminal (12b) with one end thereof lying on the connection terminal and is led out to an outer edge of the insulating substrate (10) at the other end thereof, wherein a contact portion of the lead interconnect (14) with the internal connection terminal (12b) is formed of a barrier metal layer (15A) made of titanium nitride (TiN) and the nitride concentration thereof is between 35 atoms/cm2 and 65 atoms/cm2 inclusive.

Abstract: A multilayer electronic component may include a multilayer body including a plurality of magnetic material layers, and an internal electrode disposed in the multilayer body. The internal electrode may contain a conductive metal and glass, and the glass contains a vanadium (V) oxide. Also, a conductive paste composition for an internal electrode includes a conductive metal and glass, wherein the glass contains a vanadium (V) oxide.

Abstract: A method for forming a polyimide-carbon nanotube composite film on a substrate is provided. The method comprises: suspending carbon nanotubes in a solution comprising a poly(amic acid) and a suitable solvent; casting the solution onto a substrate to form a layer on the substrate; and heating the layer to convert the poly(amic acid) into a polyimide to form the polyimide-carbon nanotube composite film. A polyimide-carbon nanotube composite film and an electronic device comprising the polyimide-carbon nanotube composite film are also provided.

Abstract: There is provided a wiring member including: a wiring substrate including wirings including a ground line, and a first insulating layer that covers the wirings and has an opening portion exposing at least a portion of the ground line; a conductive sheet sandwiched between a second insulating layer and a conductive bonding layer and disposed on the first insulating layer in a state where the conductive sheet is folded so that the second insulating layers faces to each other, and in which the conductive bonding layer in a portion which is not folded is electrically connected to the ground line through the opening portion; and a shielding member disposed on the wiring substrate and the conductive sheet to be bonded to the conductive bonding layer in a portion of the conductive sheet which is folded, and is electrically connected to the ground line through the folded portion.

Abstract: A binding tape member and a wire harness having a binding tape member configured to having the same function of conventional wire harnesses without the need for corrugated tube, pre-wrapping or post wrapping. The binding tape member has a tape member body that covers a group of electrical lines by being wrapped around the group of electrical lines. The tape body has a trapezoidal upper surface portion with an upper side and a lower side that correspond to the tape width end edges and a trapezoidal lower surface portion facing a direction opposite to the trapezoidal upper surface portion are alternatingly arranged in the tape length direction. Also, in a trapezoidal upper surface portion and a trapezoidal lower surface portion that are adjacent to each other, sides thereof in the tape length direction are connected to each other in an integrated manner by a rectangular side wall portion.

Abstract: A high-voltage wiring structure in a vehicle includes an extending member extending in an extending direction which is a longitudinal direction or a width direction of the vehicle, a plurality of bulkheads respectively provided at a plurality of portions of the extending member in the extending direction, a high-voltage wire extended from a battery for driving the vehicle, and a pipe, in which the high-voltage wire is inserted, and which is surrounded by the extending member. A plurality of portions of the pipe in a longitudinal direction of the pipe are respectively fixed to the bulkheads by welding.

Abstract: An armored cable features a core and an armor generally surrounding the core and having an inner diameter. The armor has a thickness of 0.001 to 0.100 times the inner diameter of the armor. In addition, the armor has corrugations with a pitch of 0.050 to 1.000 times the inner diameter of the armor. The armor has a corrugation depth of 0.010 to 0.400 times the inner diameter of the armor.

Abstract: A cable includes at least one electrical conductor and at least one electrically insulating layer surrounding the electrical conductor, wherein the at least one electrically insulating layer includes: (a) a thermoplastic polymer material selected from: at least one copolymer (i) of propylene with at least one olefin comonomer selected from ethylene and an a-olefin other than propylene, the copolymer having a melting point greater than or equal to 130° C.

Abstract: A wire harness waterproof structure is provided that allows the water sealant to be visually checked, enables reliably filling of the periphery of a splice portion with the water sealant, and enables water in an unfilled region to easily drain. The wire harness waterproof structure includes electrical lines forming an intermediate splice portion, an exterior member surrounding the entire circumference of the intermediate splice portion and adjacent end portions, and a curing layer made up of a water sealant wherein a gap between the intermediate splice portion and the exterior member is filled. The waterproof sheet material is curved so as to surround the splice portion and the adjacent end portions. The sheet material has seeping holes allowing a portion of the curing layer to seep, and enable moisture to be drained to the outer surface in a region not filled with the water sealant.

Abstract: There is provided a support module of a sleeve for a transmission line, which is inserted into a part of a plurality of accommodation spaces formed at a flexible sleeve for a transmission line to prevent the sleeve for a transmission line from being slack, including a flexible flat plate; a plurality of bases fixed to the flat plate so as to be arranged in a longitudinal direction of the flat plate; a plurality of slack-preventing blocks that is connected to the bases to be positioned at a top of the flat plate and prevents the flat plate from being slack by coming in contact with each other; and a plurality of bending-degree restricting blocks that is connected to the bases and the slack-preventing blocks to be positioned a bottom of the flat plate and restricts a bending degree of the flat plate by coming in contact with each other.

Abstract: Disclosed is a method for preparing a carbon nanomaterial/polymer composite. More particularly, it relates to an improved method for preparing a carbon nanomaterial/polymer composite capable of solving a dust problem of a carbon nanomaterial powder and a layer separation problem due to large density difference between the carbon nanomaterial powder and a polymer pellet and providing superior physical properties of the composite, whereby an additive used to prepare the carbon nanomaterial/polymer composite is mixed with the carbon nanomaterial powder and prepared into a pellet, which is then mixed with the polymer pellet.

Abstract: A conductive thin film, a transparent electrode, and methods of producing the same are provided. A method for preparing a conductive thin film may involve forming a layer of reduced graphene oxide and carbon nanotube on a substrate using a reducing agent containing a halogen atom.

Abstract: Apparatus for replacing a suspension insulator on a tower having a davit arm supporting an attached insulator and a conductor shoe attaching an energized conductor to the insulator lower end including a non-conductive board longer than and mounted to the tower below the davit arm, struts extending between the board and the tower, and a movable slider mounted on the board, the slider supporting a jack and a conductor lifting bar attached to the jack. Without contacting any energized components, a lineman moves the slider and operates the jack to lift and support the energized components, detaches the shoe from the insulator, moves the energized components to a remote position on the board, detaches and replaces the insulator while it is supported by a helicopter, moves the slider and operates the jack to lift the shoe into alignment with the insulator and attaches the shoe to the insulator.

Abstract: A transformer is provided having a stacked core with a pair of outer legs extending between a pair of yokes. The core is arranged in a plurality of layers. Each of the layers includes a pair of yoke plates and a pair of outer leg plates. In an inner-most layer, the width of each yoke plate is less than the width of each outer leg plate. In each of the layers, the inner points of the outer leg plates are substantially in contact with the yoke plates. The cross-section of the inner leg and the outer legs may be rectangular or cruciform.

Abstract: A magnetic device comprises a lead frame, a first core body and a coil. The lead frame has a first portion and a second portion spaced apart from the first portion. A first core body is disposed on the lead frame, wherein the first core body comprises a first through opening and a second through opening. A coil is disposed on the first core body, wherein the coil has a first terminal and a second terminal, wherein the first portion is electrically connected with the first terminal via the first through opening, and the second portion is electrically connected with the second terminal via the second through opening, respectively.

Abstract: There are provided a coil component and a board having the same. The coil component includes: a magnetic body including a substrate having two cores, first and second coil parts disposed on one surface of the substrate and wound in the same direction, and third and fourth coil parts disposed on the other surface of the substrate to be spaced apart from each other; and first to fourth external electrodes disposed on outer surfaces of the magnetic body and connected to the first to fourth coil parts.

Abstract: A magnetic circuit that forms an arc-shaped magnetic field space is provided. Of two magnets constituting a first magnetic circuit 10, a first magnetic pole 1 is provided with a first yoke 11 that is arc-shaped in planar view, a first magnet 13 that is arc-shaped in planar view and a magnetic pole piece 15. On the other hand, a second magnetic pole 2 is provided with a second yoke 21 that is arc-shaped in planar view, a second magnet 23 that is arc-shaped in planar view and a magnetic pole piece 25. The first magnetic pole piece 15 and the second magnetic pole piece 25 are disposed so as to be opposed to each other while being separated from each other. The first magnet 13 and the second magnet 23 are formed by arranging a plurality of small magnets.

Abstract: An example variable reluctance device includes a load structure connected to an armature through a connecting arm. The armature is positioned between two oppositely oriented core structures. A structural frame secures the core structures in a fixed position, forming gap regions between the core structures and the armature, forming a magnetic circuit. The armature is resiliently centered between the core structures by a spring, such that the gaps and are approximately equal in width when the armature is at rest. The device further includes a magnetic substance within the gaps that is compressed or stretched to allow movement of the armature.

Abstract: A magnetic actuator includes: a movable unit, movable between a first position and a second position, and including an integrally formed eddy-current component and first magnet yoke component; a second magnet yoke component to form a magnetic circuit with the first magnet yoke component; an electromagnetic coil capable of generating an exciting magnetic field when being energized, magnetic lines generated thereby being energized penetrating the magnetic circuit formed by the first and second magnet yoke components; an eddy-current coil to enable an eddy current to be generated in the eddy-current component, to produce an electromagnetic repulsive force to the movable unit; and a permanent magnetic holding component to hold the movable unit in the first position or the second position. The magnetic actuator can simplify the actuator, reduce the number of components and the size thereof, as well as reducing the energy consumption and improving the stability thereof.