Abstract: A method of patterning a silicon containing ARC (anti-reflective coating) layer underlying a patterned layer is described that includes establishing a flow of a process gas to a plasma processing system, selecting a process condition that increases an etch selectivity of the silicon containing ARC layer relative to the patterned layer, igniting plasma from the process gas using a plasma source in accordance with the process condition, and exposing the substrate to the plasma to extend the feature pattern of the patterned layer into the silicon containing ARC layer. The process gas includes a first gaseous molecular constituent composed of C, F and optionally H, a second gaseous molecular constituent composed of C, F, and optionally H, and a third gaseous molecular constituent containing atomic hydrogen, diatomic hydrogen, or a CxHy-containing gas, wherein x and y are real numbers greater than zero.

Abstract: After forming spacers over a hard mask layer using a sidewall image transfer process, a neutral material layer is formed on the portions of the hard mask layer that are not covered by the spacers. The spacers and the neutral material layer guide the self-assembly of a block copolymer material. The microphase separation of the block copolymer material provides a lamella structure of alternating domains of the block copolymer material.

Abstract: Provided herein are polishing compositions for removal of Co, for example, selectively over Cu, and methods of their use. A polishing composition comprising an abrasive and one or more Co complexors, where the polishing composition has a pH of 9 or more, and the Co complexor comprises one or more of functional groups selected from phosphonic acid (—P(?O)(OH)2) group or carboxyl (—C(?O)OH) group.

Abstract: A method of doping a compound semiconductor substrate includes: setting a first substrate temperature for the compound semiconductor substrate in a first temperature range; implanting a dopant species into the compound semiconductor substrate at a first ion dose at the first substrate temperature; and annealing the compound semiconductor substrate after the implanting the ions. In conjunction with the annealing, the first ion dose is effective to generate a first dopant activation in the first temperature range higher than a second dopant activation resulting from implantation of the first ion dose at a second substrate temperature below the first temperature range, and is higher than a third dopant activation resulting from implantation of the first ion dose at a third substrate temperature above the first temperature range.

Abstract: A method of manufacturing a chip fan-out structure, said method includes forming a dry film with a predetermined pattern. Providing a chip wherein the distribution of the pad is corresponding to the dry film's predetermined pattern. Contacting the surface of the pad with the dry film. Forming a molding compound to encapsulate the chip, and removing the dry film to expose the pads.

Abstract: A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side.

Abstract: The present disclosure relates to enhancing the thermal performance of encapsulated flip chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a top surface of a carrier, and a first mold compound is applied over the top surface of the carrier to encapsulate the plurality of flip chip dies. The first mold compound is thinned down to expose a substrate of each flip chip die and the substrate of each flip chip die is then substantially etched away to provide an etched flip chip die that has an exposed surface at the bottom of a cavity. Next, a second mold compound with high thermal conductivity is applied to substantially fill each cavity and the top surface of the second mold compound is planarized. Finally, the encapsulated etched flip chip dies can be marked, singulated, and tested as a module.

Abstract: Shielded electronic packages may have metallic lead frames to connect an electromagnetic shield to ground. In one embodiment, a metallic lead frame of the electronic package and a surface of the metallic lead frame defines a component area for attaching an electronic component. The metallic lead frame includes a metallic structure associated with the component area that may have a grounding element for connecting to ground and one or more signal connection elements, such as signal leads, for transmitting input and output signals. The electromagnetic shield connects to the metallic lead frame to safely connect to ground while maintaining the signal connection elements isolated from the shield.

Abstract: In an apparatus for etching a semiconductor wafer or sample (101), the semiconductor wafer or sample is placed on a sample holder (104) disposed in a first chamber (103). The combination of the semiconductor wafer or sample and the sample holder is enclosed within a second chamber (130) inside the first chamber. Gas is evacuated from the second chamber and an etching gas is introduced into the second chamber, but not into the first chamber, to etch the semiconductor wafer or sample.

Abstract: Device and method for alignment of a first contact surface of a first substrate with a second contact surface of a second substrate which can be held on a second platform. The device includes first X-Y positions of first alignment keys located along the first contact surface, and second X-Y positions of second alignment keys which correspond to the first alignment keys and which are located along the second contact surface, wherein the first contact surface can be aligned based on the first X-Y positions in the first alignment position and the second contact surface can be aligned based on the second X-Y positions in the second alignment position.

Abstract: Systems and methods for controlling wafer-breaker devices. In some embodiments, a controller for a semiconductor wafer singulation apparatus can be configured to receive an input signal having information about at least one singulation parameter. The controller can be further configured to generate an output signal based on the input signal to effectuate an operation associated with the singulation parameter. The controller can be further configured to disable manual control of the singulation parameter. In some embodiments, such a controller can be implemented, for example, in a control module, in a kit for modifying an existing singulation apparatus, as an integral part of a singulation apparatus, or any combination thereof.

Abstract: A system for and a method of bonding a first wafer to a second wafer are provided. A second wafer chuck has a second surface, a profile of the second surface being adjustable by a profile control layer. The first wafer is placed on a first surface of a first wafer chuck, and the second wafer is placed on the second surface of the second wafer chuck. The first wafer and the second wafer are warped prior to bonding to form a first warped wafer and a second warped wafer, respectively. The first warped wafer is bonded to the second warped wafer.

Abstract: The present disclosure provides a thermal treatment chamber. The thermal treatment chamber includes a wafer holder to hold a to-be-processed wafer; a heat reservoir located under the wafer holder, but being separated from the wafer holder, for adjusting a temperature of the wafer holder based on the to-be-processed wafer; and a first driving unit connected to the heat reservoir for adjusting a distance between the wafer holder and the heat reservoir to adjust the temperature of the wafer holder.

Abstract: According to an embodiment of the present disclosure, a process liquid supply apparatus operating method is provided. The method includes filling a filter unit with a process liquid from an upstream side of the filter unit to a downstream side of the filter unit after newly mounting or replacing the filter unit and repeating a depressurization filtering process and a pressurization filtering process for a predetermined number of times. The depressurization filtering process depressurizes the process liquid in the downstream side of the filter unit and thereby allows the process liquid to permeate through the filter unit. The pressurization filtering process pressurizes the process liquid from the upstream side of the filter unit and thereby allows the process liquid to permeate through the filter unit.

Abstract: A method for adjusting the warpage of a wafer, includes providing a wafer having a center portion and edge portions and providing a holding table having a holding area thereon for holding the wafer. The wafer is placed onto the holding table with the center portion higher than the edge portions and thereafter pressed onto the holding area such that the wafer is attracted to and held onto the holding table by self-suction force. The wafer is heated at a predetermined temperature and for a predetermined time in accordance with an amount of warpage of the wafer in order to achieve a substantially flat wafer or a predetermined wafer level.

Abstract: A substrate container includes a housing, rack members, housing-side support members for supporting ends of substrates, a moving mechanism for moving the substrates, a lid, and lid-side support members for supporting ends of the substrates. The housing-side support members have deepest portions for supporting the ends of the substrates to be immovable upward. In a state where the lid is attached to the housing, the housing-side support members and lid-side support members clamp the ends of the substrates in between, with lower surfaces of the substrates out of contact with the rack members, and the housing-side support members support the ends of the substrates in the deepest portions. When the lid detaches from the housing, the moving mechanism moves the substrates supported in the deepest portions to disengage the ends of the substrates from the deepest portions, and places the substrates in a substantially horizontal position on the rack members.

Abstract: An article transport vehicle is provided in which it is difficult for the transported article support portions to interfere with the supported portion of the transported article while reducing transmission of vibrations to the transported article, during a travel of the travel member or during a vertical movement of the vertically movable portion. A support unit which is vertically moved relative to a travel member is provided with a guiding supporting portion for guiding and supporting transported article support portions for supporting a supported portion of a transported article such that the transported article support portions can be moved to support positions and to retracted positions, and a damper element which is located between a vertically movable portion and the guiding supporting portion and receives load from the guiding supporting portion and which is elastically deformable in a vertical direction.

Abstract: A robot for a substrate processing system includes a first arm and a second arm each including a first arm portion connected to a base, a second arm portion connected to the first arm portion, and an end effector connected to the second arm portion. The first arm and the second arm are each configured to actuate between a fully retracted position and a plurality of extended positions. The end effector of the first arm is configured to support a first substrate and the end effector of the second arm is configured to support a second substrate. When the first arm and the second arm are in the respective fully retracted positions, the first substrate is spaced apart from and does not overlap the second substrate.

Abstract: A stocker includes a storage shelf, an output-relay shelf, a first crane, an output shelf, a second crane, and a controller. The storage shelf has a plurality of storage spaces. The output-relay shelf has a plurality of first output-relay spaces. The output shelf has an output space. The controller is configured to drive the first crane to preferentially transfer a first wafer carrier stored in one of the storage spaces to an empty one of the first output-relay spaces according to a delivery command defining a high priority of the first wafer carrier, and configured to drive the second crane to preferentially transfer the first wafer carrier from the first output-relay space storing the first wafer carrier to the output space according to the delivery command if the output space is empty.

Abstract: A method for processing a workpiece including: a supporting plate preparing step of preparing a supporting plate having, on a top surface side of the supporting plate, a recessed portion configured to house a projecting portion provided in a device region of the workpiece; a positioning step of mounting the workpiece on the supporting plate such that the recessed portion of the supporting plate and the device region of the workpiece correspond to each other; a bonding step of forming a welded region in which the workpiece is welded to the supporting plate by irradiating a peripheral surplus region of the workpiece mounted on the supporting plate with a laser beam, whereby the workpiece is fixed on the supporting plate; and a processing step of processing the workpiece after performing the bonding step.

Abstract: A first substrate, bonded to a second substrate by a material, is provided. The first substrate is transparent to at least some wavelengths of electromagnetic radiation. The first substrate is irradiated with the electromagnetic radiation to which the first substrate is transparent, such that the electromagnetic radiation impinges on the material causing a decomposition thereof at a location at an interface between the first substrate and the material. The decomposition results in, at the location, an interface of the first substrate and an atmosphere of the decomposition. The atmosphere of the decomposition has an optical property resulting in ceasing the decomposition of the material.

Abstract: A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a semiconductor substrate; forming an interfacial release layer on an exposed second surface of the semiconductor substrate; adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy; removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate; processing the semiconductor substrate; and removing the semiconductor substrate from the interfacial release layer to impart flexibility to the semiconductor substrate.

Abstract: Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed.

Abstract: A substrate carrier arrangement (10, 11) for a coating system (12) is provided, comprising a carrier (1) which comprises at least one support region (3) having a support surface (30), on which a substrate support (2) is arranged, and which support region comprises in the support surface (30) at least one first and one second gas inlet (4, 5), wherein the first gas inlet (4) is at a smaller distance from a center (M) of the support surface (30) than the second gas inlet (5) and wherein the first and second gas inlet (4, 5) comprise mutually independent gas feeds (40, 50) which are arranged to supply gases having mutually different thermal conductivities. A coating system comprising a substrate carrier arrangement and a method for performing a coating process are also provided.

Abstract: A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700.

Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench.

Abstract: A method of manufacturing a semiconductor device includes providing a first semiconductor substrate having a first main surface and an opposing second main surface, and forming a pattern into the first semiconductor substrate. The pattern includes a plurality of trenches defining a plurality of mesas. Each of the plurality of mesas has sidewalls and a free surface formed by material of the first semiconductor substrate. The method further includes forming a cavity in the first semiconductor substrate such that the pattern is recessed in the cavity, forming an oxide layer in the cavity and on the sidewalls and free surfaces of the plurality of mesas, and etching the oxide layer to remove the oxide layer from the free surfaces of the plurality of mesas and at least a portion of the sidewalls of the plurality of mesas.

Abstract: The present invention relates to a process for direct bonding two substrates, comprising at least: (a) bringing the surfaces to be bonded of said substrates in close contact; and (b) propagating a bonding wave between said substrates, characterised in that said substrates are kept, during step (b), in an atmosphere of a gas having a negative Joule-Thomson coefficient at the temperature and pressure of said atmosphere.

Abstract: A composite wafer is manufactured by providing a carrier wafer including graphite and a protective layer, forming a bonding layer, and bonding the carrier wafer to a semiconductor wafer through the bonding layer.

Abstract: A method for manufacturing a semiconductor device includes: forming a semiconductor element having an electrode on a main surface of a semiconductor substrate; forming a first resin film that encloses a side of the electrode while keeping a distance from the electrode of the semiconductor element on the main surface of the semiconductor substrate; and forming a hollow structure around the electrode of the semiconductor element by bonding a second resin film that covers over the electrode while keeping a distance from the electrode of the semiconductor element to a top surface of the first resin film.

Abstract: Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.

Abstract: Methods for forming integrated circuit structures are provided. The method includes providing a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The method further includes forming a gate structure over the substrate and forming an inter-layer dielectric (ILD) layer over the substrate. The method further includes forming a cutting mask over a portion of the gate structure over the isolation structure, and the cutting mask has an extending portion covering a portion of the ILD layer. The method further includes forming a photoresist layer having an opening, and a portion of the extending portion of the cutting mask is exposed by the opening. The method further includes etching the ILD layer through the opening to form a trench and filling the trench with a conductive material to form a contact.

Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.

Abstract: The semiconductor package includes semiconductor chips, each chip having one or more bonding pads. The semiconductor chips are stacked in a stepped configuration over the surface of the substrate without covering one or more bonding pads. An encapsulation member encapsulates the stacked semiconductor chips on the surface of the substrate. Via wirings in the encapsulation member electrically connect to a bonding pad of at least one of the semiconductor chips. Redistributions are formed over the encapsulation member such that the one or more redistributions are electrically coupled to the via wirings.

Abstract: When a recess is formed in a SiCOH film, C is removed from the film to form a damage layer. If the damage layer is removed by hydrofluoric acid or the like, the surface becomes hydrophobic. By supplying a boron compound gas, a silicon compound gas or a gas containing trimethyl aluminum to the SiCOH film, B, Si or Al is adsorbed on the SiCOH film. These atoms bond with Ru and a Ru film is easily formed on the SiCOH film. The Ru film is formed using, for example, Ru3(CO)12 gas and CO gas. Copper is filled in the recess and an upper side wiring structure is formed by carrying out CMP processing.

Abstract: A method of manufacturing a semiconductor interconnect structure may include forming a low-k dielectric layer over a substrate and forming an opening in the low-k dielectric layer, where the opening exposes a portion of the substrate. The method may also include filling the opening with a copper alloy and forming a copper-containing layer over the copper alloy and the low-k dielectric layer. An etch rate of the copper-containing layer may be greater than an etch rate of the copper alloy. The method may additionally include patterning the copper-containing layer to form interconnect features over the low-k dielectric layer and the copper alloy.

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect in a first interlayer dielectric. A first cap is formed overlying the first interlayer dielectric adjacent to the interconnect, and a second interlayer dielectric is formed overlying the first interlayer dielectric, the interconnect, and the cap. A contact is formed through the second interlayer dielectric, where the contact includes an overlap region and a connection region. The overlap region directly overlies the first interlayer dielectric adjacent to the interconnect, and the connection region directly contacts the interconnect. The first cap is positioned between the overlap region and the first interlayer dielectric.

Abstract: A magnetic trap is configured to arrange at least one diamagnetic rod. The magnetic trap includes first and second magnets on a substrate that forms the magnetic trap defining a template configured to self-assemble diamagnetic material. Each of the first and second magnets extends along a longitudinal direction to define a magnet length, and contact each other to define a contact line. The first magnet and the second magnet have a diametric magnetization in a direction perpendicular to the contact line and the longitudinal direction so as to generate a longitudinal energy potential that traps the diamagnetic rod along the longitudinal direction.

Abstract: Provided is a peeling apparatus configured to suppress damage to a substrate, by forming a peeling start point. The peeling apparatus separates a superimposed substrate made by joining first and second substrates into the first and second substrates, and includes a blade configured to form a notch as a peeling start point between the first and second substrates, and an inspection unit configured to inspect a state of a cutting edge of the blade. The inspection unit includes an imaging unit configured to image the cutting edge of the blade, and an image processing unit configured to process an image of the imaging unit.

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor, forming an oxide layer on the IO regions of the substrate, forming an interfacial layer on the substrate and the oxide layer, depositing a high-k (HK) dielectric layer on the interfacial layer, depositing a first capping layer of a first material on the HK dielectric layer, depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer, depositing a work function (WF) metal layer on the second capping layer, depositing a polysilicon layer on the WF metal layer, and forming gate stacks on the regions of the substrate.

Abstract: Methods are presented for facilitating fabrication of nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate; providing first material layers and second material layers above the substrate, the first material layers interleaved with the second material layers; removing portions of the first material layers and second material layers, the removing forming a plurality of nanowire stacks, including first material nanowires and second material nanowires; removing the first material nanowires from at least one nanowire stack; and removing the second material nanowires from at least one other nanowire stack, where the at least one nanowire stack and at least one other nanowire stack include a p-type nanowire stack(s) and a n-type nanowire stack(s), respectively.

Abstract: A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB.

Abstract: A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a first work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type.

Abstract: A method for fabricating a semiconductor device comprises: Firstly, a semiconductor fin comprising a first sub-fin and a second sub-fin protruding from a surface of a substrate is provided. An isolation structure having an opening extending therein is then provided in the semiconductor fin to electrically isolate the first sub-fin and the second sub-fin. Subsequently, a first dummy structure disposed on the first isolation structure and having at least one metal layer entirely overlapping on the first isolation structure along a long axis of the semiconductor fin is formed, wherein the metal layer laterally conformally extends downwards into the opening and extends upwards beyond the first isolation structure along the long axis of the semiconductor fin, so as to form a stepped structure overlapping on sidewalls and a bottom of the opening, a portion of the first sub-fin and a portion of the second sub-fin.

Abstract: A method and apparatus are disclosed which use a photoluminescent light intensity signature to characterize a processed photovoltaic substrate.

Abstract: Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool.

Abstract: A system and method for identifying one or more characteristics of a structure formed into a substrate is herein disclosed. Surface and bulk acoustic waves are induced in the substrate and travel past a structure of interest where the acoustic waves are sensed. Information concerning one or more characteristics of the structure is encoded in the wave. The encoded information is assessed to determine the characteristic of interest.

Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.

Abstract: The present invention provides a short-circuit unit comprising: a plurality of signal lines divided into a plurality of groups, each group comprising multiple signal lines, and the multiple signal lines in a same group are not adjacent to each other; a plurality of short-circuit lines, each group of the signal lines correspond to one short-circuit line, and the short-circuit line electrically connects all of the signal lines in the group corresponding to the short-circuit line, the plurality of short-circuit lines are disposed in different layers and the short-circuit lines in different layers are insulated from each other. The present invention also provides an array substrate. In the short-circuit unit of the present invention, the short-circuit lines are disposed in different layers. Compared to the existing solutions in which the short-circuit lines are provided in a same layer, the width occupied by the short-circuit unit of the present invention is smaller.

Abstract: A semiconductor package may include a first output test pad and a second output test pad disposed on a first surface of an insulating film, and a semiconductor chip disposed between the first output test pad and the second output test pad on a second surface opposing to the first surface of the insulating film.