Abstract: The present invention is a shielded anode having an anode with a surface facing an electron beam and a shield configured to encompass the anode surface. The shield has at least one aperture and an internal surface facing the anode surface. The shield internal surface and anode surface are separated by a gap in the range of 1 mm to 10 mm. The shield of the present invention is fabricated from a material, such as graphite, that is substantially transmissive to X-ray photons.

Abstract: A focused ion beam system is provided. The focused ion beam system includes a plasma generation chamber configured to contain a source gas that is radiated with microwaves to produce plasma. The plasma generation chamber includes a plasma confinement device configured to confine the plasma in radial and axial directions within the plasma generation chamber and to form a plasma meniscus at an extraction end of the plasma generation chamber. The focused ion beam system also includes a beam extraction chamber configured to extract a focused ion beam from the confined plasma and to focus the extracted focused ion beam on a workpiece.

Abstract: A multipole lens is provided which is for use in electron microscopy and which is simple in structure but capable of producing X- and Y-components of a quadrupole field and X- and Y-components of an octopole field. The multipole lens (100) comprises: first through twelfth polar elements (10-1 to 10-12); first through sixteenth coils (20-1 to 20-16); a first power supply (30-1) for supplying currents to the coils (20-1, 20-4, 20-9, 20-12); a second power supply (30-2) for supplying currents to the coils (20-3, 20-5, 20-11, 20-13); a third power supply (30-3) for supplying excitation currents to the coils (20-6, 20-8, 20-14, 20-16); and a fourth power supply (30-4) for supplying excitation currents to the coils (20-2, 20-7, 20-10, 20-15). The coils (20-1, 20-3, 20-6, 20-7, 20-9, 20-11, 20-14, 20-15) produce magnetic fields in a first direction. The coils (20-2, 20-4, 20-5, 20-8, 20-10, 20-12, 20-13, 20-16) produce magnetic fields in a direction opposite to the first direction.

Abstract: This weak signal detection system has: a statistical data acquisition unit which measures the average value or distribution of an input signal in which is noise superimposed on a desired signal, calculates parameters such as the amplitude or noise dispersion of the desired signal, and outputs the calculated data obtained thereby; a nonlinear characteristic unit which outputs a signal having a nonlinear response with respect to the magnitude of the voltage or the current of the input signal; a signal detection ratio evaluation unit which determines whether the output signal from the nonlinear characteristic unit is the desired signal, calculates the detection ratio in the event that the signal is the desired signal, and outputs detection ratio data; a parameter adjustment unit which, on the basis of detection ratio data obtained by the signal detection ratio evaluation unit and calculated data obtained by the statistical data acquisition unit, adjusts a control parameter pertaining to the responsiveness of the

Abstract: A low energy electron diffraction (LEED) detection module (100) includes: a first vacuum chamber for receiving diffracted electrons from a specimen (109); a larger second vacuum chamber connected to the first vacuum chamber to receive the diffracted electrons that have been transported through the first vacuum chamber; a two-dimensional electron detector disposed in the second vacuum chamber to detect the diffracted electrons; a potential shield (106) disposed generally along an inner surface of the first vacuum chamber and an inner surface of the second vacuum chamber; a magnetic lens (105) to expand a beam of the diffracted electrons that have been transported through the first vacuum chamber towards the two-dimensional electron detector; and a generally plane-shaped energy filter (103) to repel electrons having an energy lower than the probe beam (203) of electrons that impinges on the specimen (109).

Abstract: A beam current adjuster for an ion implanter includes a variable aperture device which is disposed at an ion beam focus point or a vicinity thereof. The variable aperture device is configured to adjust an ion beam width in a direction perpendicular to an ion beam focusing direction at the focus point in order to control an implanting beam current. The variable aperture device may be disposed immediately downstream of a mass analysis slit. The beam current adjuster may be provided with a high energy ion implanter including a high energy multistage linear acceleration unit.

Abstract: An improved process workflow and apparatus for S/TEM sample preparation and analysis is provided. Preferred embodiments provide improved methods for an automated recipe TEM sample creation, especially for small geometry TEM lamellae, employing CAD data to automatically align various stages of sample preparation. The process automatically verifies and aligns the position of FIB-created fiducials by masking off portions of acquired images, and then comparing them to synthesized images from CAD data. SEM beam positions are verified by comparison to images synthesized from CAD data. FIB beam position is also verified by comparison to already-aligned SEM images, or by synthesizing an FIB image from CAD using techniques for simulating FIB images. The automatic alignment techniques herein allow creation of sample lamellas at specified locations without operator intervention.

Abstract: A method or process is disclosed for etching deep, high-aspect ratio features into silicon dioxide material layers and substrates, including glass, fused silica, quartz, or similar materials, using a plasma etch technology. The method has application in the fabrication and manufacturing of MEMS, microelectronic, micro-mechanical, photonic and nanotechnology devices in which silicon dioxide material layers or substrates are used and must be patterned and etched. Devices that benefit from the method described in this invention include the fabrication of MEMS gyroscopes, resonators, oscillators, microbalances, accelerometers, for example. The etch method or process allows etch depths ranging from below 10 microns to over 1 millimeter and aspect ratios from less than 1 to 1 to over 10 to 1 with etched feature sidewalls having vertical or near vertical angles. Additionally, the disclosed method provides requirements of the etched substrates to reduce or eliminate undesired effects of an etch.

Abstract: In a magnetron and a plasma waveguide through which a microwave oscillated from the magnetron moves, there is provided a plasma waveguide including a plurality of step parts formed at any one side on an inner side surface of the waveguide, and a block part of a predetermined height formed at any other side on the inner side surface of the waveguide, wherein the block part is formed at a side opposite to a boundary part between the plurality of step parts.

Abstract: The invention relates to a plasma generation device comprising a plurality of plasma modules for generating a plasma. Each plasma module has a module housing with at least one gas inlet for supplying a process gas. Furthermore, a discharge device for generating the plasma from the process gas and a plasma outlet are provided. The plasma generation device has at least two plasma modules for generating a plasma. Each plasma module has at least one gas outlet for some of the process gas, wherein the at least one gas outlet of at least one plasma module issues into a respective gas inlet of another plasma module.

Abstract: The invention provides a charged particle sensor (10) for detecting and measuring ionic current generated by charged particles resulting from ionization processes, comprising: a housing (16), a detection electrode (14) enclosed within the housing for collecting the charged particles, and an electrometer (12) having an input connected to the detection electrode for receiving a DC input signal therefrom and an output (18) for supplying a DC measurement signal as output. The housing comprises an electrostatic screen (16) for screening the detection electrode from external electric fields, whereby to reduce the sensitivity of the detection electrode to such fields.

Abstract: A method of analyzing ions is disclosed comprising performing an initial multi-dimensional survey scan comprising separating parent ions according to a first physico-chemical property (e.g. ion mobility) and then separating the parent ions according to a second physico-chemical property (e.g. mass to charge ratio). A plurality of parent ions of interest are then determined from the initial multi-dimensional survey scan. Once parent ions of interest have been determined, the plurality of parent ions of interest are sequentially selected based upon the first and second physico-chemical properties during a single cycle of separation. The parent ions of interest may then be fragmented and corresponding fragment ions may then be mass analyzed.

Abstract: Multiplexed spectrometry, such as multiplexed ion mobility spectrometry (IMS), time-of-flight mass spectrometry (TOFMS), or hybrid IM-TOFMS, is carried out on a sample, and the resulting measurement data are deconvoluted. Noise may be removed from the measurement data prior to deconvolution. Alternatively or additionally, noise may be removed from the deconvoluted data.

Abstract: A method of operating a tandem mass spectrometer system is disclosed including accumulating ions in an ion trap, transmitting a plurality of ions out of the ion trap into a timed-ion selector, applying a pulsed DC voltage to the timed-ion selector, the pulsed DC voltage being modulated to match an ejection time for selecting a first portion of ions from the plurality of ions, corresponding to a specific m/z window, transmitting the first portion of selected ions out of the timed-ion selector into a reaction cell, transmitting dissociation product ions and the remaining ions of the first portion of selected ions out of the reaction cell into a mass analyzer, and mass-selectively transmitting at least some of the fragment ions and the remaining ions of the first portion of selected ions out of the mass analyzer into a detector.

Abstract: A mass spectrometer including chromatogram creation means for creating a chromatogram showing changes over time in an ion intensity within a predetermined mass range based on the MS analysis results, and timing determination means for determining a timing to perform MS/MS analysis based on the chromatogram. The timing determination means determines, as a timing to perform MS/MS analysis, a point in time at which a signal intensity in the chromatogram reaches a predetermined upper limit after exceeding a predetermined lower limit or a point in time at which a signal intensity in the chromatogram reaches a top of a peak without reaching the upper limit after exceeding the lower limit. It is thus possible to collect precursor ions at a timing at which the signal intensity of a peak originating from sample components is highest between the upper limit and lower limit, thereby obtaining a high quality MS/MS spectrum.

Abstract: A method of mass spectrometry is disclosed comprising transmitting ions and obtaining first mass spectral data and automatically determining during an acquisition whether the first mass spectral data suffers from saturation or is approaching saturation. If a determination is made during an acquisition that the first mass spectral data suffers from saturation or is approaching saturation then the method further comprises automatically changing or altering the intensity of ions which are detected by an ion detector and obtaining second mass spectral data. The method further comprises substituting one or more portions of the first mass spectral data with one or more corresponding portions of the second mass spectral data multiplied or scaled by an attenuation or scale factor and/or by an integer or other value so as to form a composite mass spectrum, wherein the composite mass spectrum comprises one or more ion peaks from the first mass spectral data and one or more ion peaks from the second mass spectral data.

Abstract: An orthogonal pulse accelerator for a Time-of-Flight mass analyzer includes an electrically-conductive first plate extending in a first plane, and a second plate spaced from the first plate. The second plate includes a grid that defines a plurality of apertures each having a first dimension extending in a first direction and a second dimension orthogonal to the first dimension, the first and second dimensions lying in the second plane and the second dimension begin larger than the first dimension. The first and second plates are positioned in the Time-of-Flight mass analyzer to receive, during operation of the mass analyzer, an ion beam propagating in the first direction in a region between the first and second plates, and the orthogonal pulse accelerator directs ions in the ion beam through the apertures.

Abstract: The invention relates to embodiments of high-resolution time-of-flight (TOF) mass spectrometers with special reflectors. The invention provides reflectors with ideal energy and solid angle focusing, based on Cassini ion traps, and proposes that a section of the flight path of the TOF mass spectrometers takes the form of a Cassini reflector. It is particularly favorable to make the ions fly through this Cassini reflector in a TOF mass spectrometer at relatively low energies, with kinetic energies of below one or two kiloelectronvolts. This results in a long, mass-dispersive passage time in addition to the time of flight of the other flight paths, without increasing the energy spread, angular spread or temporal distribution width of ions of the same mass. It is also possible to place several Cassini reflectors in series in order to extend the mass-dispersive time of flight. Several TOF mass spectrometers for axial as well as orthogonal ion injection with Cassini reflectors are presented.

Abstract: The present invention relates to an electrical gas-discharge lamp comprising an inner bulb (1) arranged within an outer bulb (2), said inner bulb (1) being filled with a discharge gas and comprising a first electrode (3) and an opposing second electrode (4) having a distance from the first electrode (3) which allows ignition of a gas-discharge by applying an ignition voltage between the electrodes (3, 4). At least one through hole (11) is formed in the feedthrough to the electrically conductive lead (5) to the first electrode (3). An electrically conductive member (10) extents within a space formed between the inner (1) and the outer bulb (2) from a position close to the through hole (11) to a distance from the second electrode (4) which is smaller than the distance between the two electrodes (3,4).

Abstract: An ignition facilitated electrodeless sealed high intensity illumination device is disclosed. The device is configured to receive a laser beam from a continuous wave (CW) laser light source. A sealed chamber is configured to contain an ionizable medium. The chamber has an ingress window disposed within a wall of a chamber interior surface configured to admit the laser beam into the chamber, a plasma sustaining region, and a high intensity light egress window configured to emit high intensity light from the chamber. A path of the CW laser beam from the laser light source through the ingress window to a focal region within the chamber is direct. The ingress window is configured to focus the laser beam to within a predetermined volume, and the plasma is configured to be ignited by the CW laser beam, optionally by heating of a non-electrode ignition agent located entirely within the chamber.

Abstract: The user of plasma light technology and remote lighting control techniques may enable a single master controller to control a large number of lighting fixtures. Multiple lighting fixtures may be equipped with control applications. Each control application may control the radio frequency driver of a lighting fixture that drives the plasma bulbs of the lighting fixture to produce light output for growing plants. The master controlled may execute on one or more computing devices. The master controller may send input instructions to the control applications of the lighting fixtures via a network. The instructions may be implemented by the control applications to command the radio frequency drivers to regulate a spectral distribution and/or intensity of the light output of the lighting fixtures.

Abstract: A substrate treatment method includes a substrate holding unit which horizontally holds a substrate; a rotating unit which rotates the substrate held by the substrate holding unit about a vertical axis; and a first nozzle having an opposing face to be opposed to a lower surface of the substrate inward of a peripheral portion of the substrate in spaced relation to the lower surface of the substrate during rotation of the substrate by the rotating unit and a treatment liquid spout provided in the opposing face for filling a space defined between the lower surface of the substrate and the opposing face with a treatment liquid spouted from the treatment liquid spout to keep the space in a liquid filled state; wherein the treatment liquid spreads outwardly over the lower surface of the substrate and further, flows around to a peripheral portion of an upper surface of the substrate.

Abstract: A method of removing an amorphous silicon/silicon oxide film stack from vias is described. The method may involve a remote plasma comprising fluorine and a local plasma comprising fluorine and a nitrogen-and-hydrogen-containing precursor unexcited in the remote plasma to remove the silicon oxide. The method may then involve a local plasma of inert species to potentially remove any thin carbon layer (leftover from the photoresist) and to treat the amorphous silicon layer in preparation for removal. The method may then involve removal of the treated amorphous silicon layer with several options possibly within the same substrate processing region. The bottom of the vias may then possess exposed single crystal silicon which is conducive to epitaxial single crystal silicon film growth. The methods presented herein may be particularly well suited for 3d NAND (e.g. VNAND) device formation.

Abstract: A wafer cleaning apparatus includes a polishing unit used in chemical mechanical polishing (CMP) of a wafer and a cleaning dispensing unit arranged to direct cleaning fluids toward a far edge of the wafer after the CMP of the wafer. A wafer cleaning method includes CMP of a wafer by a polishing unit and directing cleaning fluids toward a far edge of the wafer after the CMP of the wafer by a cleaning dispensing unit. Another method can include CMP, applying deionized water, and applying pH adjuster having a pH range from about 2 to about 13.

Abstract: Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B, C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. One or more of the boron and carbon containing films can have a thickness of less than about 30 angstroms. Methods of doping a semiconductor substrate are provided. Doping a semiconductor substrate can include depositing a boron and carbon film over the semiconductor substrate by exposing the substrate to a vapor phase boron precursor at a process temperature of about 300° C. to about 450° C., where the boron precursor includes boron, carbon and hydrogen, and annealing the boron and carbon film at a temperature of about 800° C. to about 1200° C.

Abstract: Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a semiconductor device includes a semiconductor structure. An electrically semi-insulating passivation layer overlies the semiconductor structure. An electrically substantially fully insulating passivation layer overlies the electrically semi-insulating passivation layer.

Abstract: Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment.

Abstract: An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a first material on the silicon wafer, and epitaxially growing a second layer of a second material on the first layer. For example, said first material may be monocrystalline silicon carbide, and said second material may be monocrystalline silicon.

Abstract: In some aspects, methods for forming a germanium thin film using a cyclical deposition process are provided. In some embodiments, the germanium thin film is formed on a substrate in a reaction chamber, and the process includes one or more deposition cycles of alternately and sequentially contacting the substrate with a vapor phase germanium precursor and a nitrogen reactant. In some embodiments, the process is repeated until a germanium thin film of desired thickness has been formed.

Abstract: An object is to manufacture a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (for dehydration or dehydrogenation) is performed to improve the purity of the oxide semiconductor film and reduce impurities including moisture or the like. After that, slow cooling is performed under an oxygen atmosphere. Besides impurities including moisture or the like exiting in the oxide semiconductor film, heat treatment causes reduction of impurities including moisture or the like exiting in a gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor and in contact therewith.

Abstract: A method of manufacturing a semiconductor device may include: forming an opening in an insulating layer to expose a portion of a major surface of a substrate, the substrate comprising a first semiconductor material; forming a protrusion in the opening using a first epitaxial growth process, the protrusion comprising a first portion disposed in the opening and a second portion extending out of the opening, the protrusion comprising a second semiconductor material different from the first semiconductor material; and forming the second semiconductor material on sidewalls of the second portion of the protrusion using a second epitaxial growth process different from the first epitaxial growth process.

Abstract: A method of fabricating a polysilicon layer includes forming a buffer layer on a substrate, forming a metal catalyst layer on the buffer layer, diffusing a metal catalyst into the metal catalyst layer to the buffer layer, removing the metal catalyst layer, forming an amorphous silicon layer on the buffer layer, and annealing the substrate to crystallize the amorphous silicon layer into a polysilicon layer. The thin film transistor includes a substrate, a buffer layer disposed on the substrate, a semiconductor layer disposed on the buffer layer, a gate insulating layer disposed above the substrate and on the semiconductor layer, a gate electrode disposed on the gate insulating layer, a source electrode and a drain electrode both electrically connected to the semiconductor layer, and a metal silicide disposed between the buffer layer and the semiconductor layer.

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract: Disclosed herein is a method for doping a substrate, comprising disposing a coating of a composition comprising a copolymer, a dopant precursor and a solvent on a substrate; where the copolymer is capable of phase segregating and embedding the dopant precursor while in solution; and annealing the substrate at a temperature of 750 to 1300° C. for 0.1 second to 24 hours to diffuse the dopant into the substrate. Disclosed herein too is a semiconductor substrate comprising embedded dopant domains of diameter 3 to 30 nanometers; where the domains comprise Group 13 or Group 15 atoms, wherein the embedded spherical domains are located within 30 nanometers of the substrate surface.

Abstract: Provided is an epitaxial silicon wafer free of epitaxial defects caused by dislocation clusters and COPs with reduced metal contamination achieved by higher gettering capability and a method of producing the epitaxial wafer. A method of producing an epitaxial silicon wafer includes a first step of irradiating a silicon wafer free of dislocation clusters and COPs with cluster ions to form a modifying layer formed from a constituent element of the cluster ions in a surface portion of the silicon wafer; and a second step of forming an epitaxial layer on the modifying layer of the silicon wafer.

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a nonvolatile memory device.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.

Abstract: The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S1) providing a substrate having a metal gate structure on a side of the substrate, (S2) forming a titanium nitride (TiN) layer on the side of the substrate, and (S3) performing a gate annealing to tune work function of the metal gate structure.

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract: Memories, systems, and methods for forming memory cells are disclosed. One such memory cell includes a charge storage node that includes nanodots over a tunnel dielectric and a protective film over the nanodots. In another memory cell, the charge storage node includes nanodots that include a ruthenium alloy. Memory cells can include an inter-gate dielectric over the protective film or ruthenium alloy nanodots and a control gate over the inter-gate dielectric. The protective film and ruthenium alloy can be configured to protect at least some of the nanodots from vaporizing during formation of the inter-gate dielectric.

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.

Abstract: Disclosed is a wafer processing apparatus. The wafer processing apparatus includes a first surface plate on which a plurality of carriers is arranged, a first gear arranged at the central region of the first surface plate and engaged with the plurality of carriers, a second gear arranged around the edge region of the first surface plate and engaged with the plurality of carriers, a motor rotating the first surface plate in a first direction, a fixing hanger arranged opposite the first surface plate, and a second surface plate hung on the fixing hanger such that a clearance between the first surface plate and the second surface plate may be varied.

Abstract: In a substrate processing apparatus, with an internal space of a chamber brought into a pressurized atmosphere, an etching process is performed by continuously supplying a first processing liquid onto an upper surface of a substrate while rotating the substrate. It is thereby possible to suppress vaporization of the first processing liquid on the substrate and further suppress a decrease in the temperature of the substrate due to the heat of vaporization as it goes from a center portion of the substrate toward a peripheral portion thereof as compared with under normal pressure. As a result, it is possible to improve the uniformity in the temperature of the upper surface of the substrate during the etching process using the first processing liquid and improve the uniformity of etching over the entire upper surface of the substrate.

Abstract: Methods of selectively etching silicon relative to silicon germanium are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and a hydrogen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the silicon. The plasmas effluents react with exposed surfaces and selectively remove silicon while very slowly removing other exposed materials. The methods are useful for removing Si(1-X)GeX faster than Si(1-Y)GeY, for X<Y. In some embodiments, the silicon germanium etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.

Abstract: An apparatus configured to remove metal etch byproducts from the surface of substrates and from the interior of a substrate processing chamber. A plasma is used in combination with a solid state light source, such as an LED, to desorb metal etch byproducts. The desorbed byproducts may then be removed from the chamber.

Abstract: Methods are provided for integrating atomic layer etch and atomic layer deposition by performing both processes in the same chamber or reactor. Methods involve sequentially alternating between atomic layer etch and atomic layer deposition processes to prevent feature degradation during etch, improve selectivity, and encapsulate sensitive layers of a semiconductor substrate.

Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.

Abstract: Provided is a method of fabricating a semiconductor device. In the method, a double patterning technology is used to form various patterns with different widths.

Abstract: A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.

Abstract: A method of etching silicon nitride on patterned heterogeneous structures is described and includes a gas phase etch using anhydrous vapor-phase HF. The HF may be combined with one or more of several precursors in the substrate processing region and near the substrate to increase the silicon nitride etch rate and/or the silicon nitride selectivity. The silicon nitride etch selectivity is increased most notably when compared with silicon of various forms. No precursors are excited in any plasma either outside or inside the substrate processing region according to embodiments. The HF may be flowed through one set of channels in a dual-channel showerhead while the other precursor is flowed through a second set of channels in the dual-channel showerhead.