Patents Issued in February 21, 2017
  • Patent number: 9576866
    Abstract: The present invention provides an array substrate, which includes a plurality of pixel units, each pixel unit includes a thin film transistor, a pixel electrode, a common electrode and a passivation layer, the thin film transistor includes an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode and the pixel electrode are connected, the passivation layer is disposed on the active layer, the source electrode, the drain electrode and the pixel electrode, the common electrode is disposed above the pixel electrode with the passivation layer therebetween, a test electrode is disposed on the active layer and under the passivation layer, the test electrode is electrically insulated from the gate electrode, the source electrode and the drain electrode. Correspondingly, a method for fabricating and a method for testing the array substrate, and a display device including the array substrate are provided.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: February 21, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Mi Zhang
  • Patent number: 9576867
    Abstract: Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Reinhard Pufall
  • Patent number: 9576868
    Abstract: A system includes a silicon carbide (SiC) semiconductor device and a hermetically sealed packaging enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: February 21, 2017
    Assignee: General Electric Company
    Inventors: Joseph Darryl Michael, Stephen Daley Arthur
  • Patent number: 9576870
    Abstract: The invention relates to a module package which comprises a module substrate 1, a chip 2, 3 applied using the flip chip process, and an encapsulation layer 8, and to a method for producing same. The chip 2, 3 has component structures on the top side 13, 14 thereof. Said top said 13, 14 faces the module carrier 1, wherein a gap 4, 5 is formed between the top side 13, 14 of the chip and the module carrier 1. A filler is added to the encapsulation layer 8. The encapsulation layer 8 partly fills underneath the chip 2, 3, wherein at most the part of the chip 2, 3, on which no component structures are present, is underfilled, and at a minimum the material of the encapsulation layer 8 completely encloses the sides of the chip 2, 3.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: February 21, 2017
    Assignee: EPCOS AG
    Inventors: Claus Reitlinger, Frank Rehme, Rudolf Bart
  • Patent number: 9576871
    Abstract: The present invention provides a composition of which viscosity does not cause the problem of use at high temperature in the mounting process of electronic device. The present invention relates to a composition for electronic device comprising (a) a (meth)acrylic compound and (c) a particle having a functional group having metal scavenging functionality.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: February 21, 2017
    Assignee: HENKEL AG & CO. KGAA
    Inventors: Yusuke Horiguchi, Kenichiro Sato, Mieko Sano
  • Patent number: 9576872
    Abstract: A method includes arranging multiple semiconductor chips over a first carrier and depositing a first material layer over surfaces of the multiple semiconductor chips, wherein depositing the first material layer includes a vapor deposition, and wherein the first material layer includes at least one of an organic material and a polymer.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies AG
    Inventors: Thomas Mueller, Horst Theuss
  • Patent number: 9576873
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: February 21, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 9576874
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Chen, Kai-Chiang Wu, Chun-Lin Lu, Hung-Jui Kuo
  • Patent number: 9576875
    Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: February 21, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Reinhard Hess, Katharina Umminger, Gabriel Maier, Markus Menath, Gunther Mackh, Hannes Eder, Alexander Heinrich
  • Patent number: 9576876
    Abstract: The present invention relates to an organic-inorganic hybrid thin film and a method for preparing the same and more specifically to an organic-inorganic hybrid thin film including a stable new functional group and a method for preparing the organic-inorganic hybrid thin film that is formed by the molecular layer deposition method alternately using inorganic precursor and organic precursor.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: February 21, 2017
    Assignees: BASF Coatings GmbH, IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Myung Mo Sung, Kyu Seok Han
  • Patent number: 9576877
    Abstract: A frame member includes a first portion, a second portion, and a third portion located between the first portion and the second portion, and wherein the lengths of the first portion and the second portion in a circumferential direction are longer than the length of the third portion in the circumferential direction, and a Young's modulus of the third portion is lower than the Young's moduli of the first portion and the second portion.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: February 21, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takanori Suzuki
  • Patent number: 9576878
    Abstract: A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Isabel De Sousa, Annique Lavoie, Eric Salvas, Michel Turgeon
  • Patent number: 9576879
    Abstract: A heat-dissipation structure includes a first carbon nanotube layer and a thermal interface material layer. The first carbon nanotube layer and the thermal interface material layer are stacked on each other. The first carbon nanotube layer includes at least one first carbon nanotube paper, and the density of the first carbon nanotube paper ranges from about 0.3 g/cm3 to about 1.4 g/cm3. An electronic device applying the heat-dissipation structure is also disclosed.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: February 21, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ling Zhang, Chang-Hong Liu, Shou-Shan Fan
  • Patent number: 9576880
    Abstract: A dual damascene structure with an embedded liner and methods of manufacture are disclosed. The method includes forming a dual damascene structure in a substrate. The method further includes reflowing a seed layer such that material of the seed layer flows into a via of the dual damascene structure. The method further includes forming a liner material on the material over or within the via of the dual damascene structure. The method further includes filling any remaining portions of the via and a trench of the dual damascene structure with additional material.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Baozhen Li, Chih-Chao Yang
  • Patent number: 9576881
    Abstract: According to one embodiment, a semiconductor device includes: a semiconductor substrate, the semiconductor substrate having first and second surfaces; conductive regions extending in a direction from the first surface side toward the second surface side of the semiconductor substrate, the conductive regions including first and second vias; a first semiconductor region surrounding a part of each of the conductive regions on the second surface side of the semiconductor substrate, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor substrate; a first electrode provided on the second surface side; second electrodes provided on the first surface side, one of the second electrodes being in contact with one of the conductive regions; and an insulating film provided between each of the conductive regions and the semiconductor substrate, and between each of the conductive regions and the first semiconductor region.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 21, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Akou, Norihisa Arai, Keisuke Murayama
  • Patent number: 9576882
    Abstract: Vias for three dimensional (3D) stacking, packaging and heterogeneous integration of semi-conductor layers and wafers and a process for the manufacture of a via, to a via, to a 3D circuit and to a semiconductor device. Vias are interconnects used to vertically interconnect chips, devices, interconnection layers and wafers, i.e., in an out-of-plane direction.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 21, 2017
    Assignee: TECHNISCHE UNIVERSITEIT DELFT
    Inventors: Regnerus Hermannus Poelma, Henk van Zeijl, Guoqi Zhang
  • Patent number: 9576883
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: February 21, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Roger M. Arbuthnot, Stephen St. Germain
  • Patent number: 9576884
    Abstract: In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: February 21, 2017
    Assignee: ADVENTIVE IPBANK
    Inventor: Richard K Williams
  • Patent number: 9576885
    Abstract: A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: February 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsuhiko Funatsu, Yukihiro Sato, Takamitsu Kanazawa, Masahiro Koido, Hiroyoshi Taya
  • Patent number: 9576886
    Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: February 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Reynaldo Corpuz Javier, Alok Kumar Lohia, Andy Quang Tran
  • Patent number: 9576887
    Abstract: In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: February 21, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Andrew N. Sawle, Mark Pavier, Daniel Cutler
  • Patent number: 9576888
    Abstract: A device comprises a bottom package comprising a plurality of metal bumps formed on a first side of the bottom package and a plurality of first bumps formed on a second side of the bottom package, a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps, and wherein second bumps and respective metal bumps form a joint structure and an underfill layer formed between the top package and the bottom package, wherein the metal bumps are embedded in the underfill layer.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chun-Cheng Lin, Wei-Yu Chen, Ai-Tee Ang, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9576889
    Abstract: An electronic package may be fabricated by forming a first layer of insulating material on a first substrate such that the first layer covers a contact pad; forming an opening through the first layer to expose the contact pad; forming an un-patterned second layer on the first layer, the second layer including an adhesive having a viscosity less than that of the first layer, wherein a region of the second layer obstructs the contact pad; removing the region to re-expose the contact pad; aligning a second substrate with the first substrate such that a via of the second substrate is aligned with the opening; bonding the first substrate and the second substrate together at the second layer; and forming an interconnect in contact with the contact pad by depositing a conductive material through the via and the opening.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 21, 2017
    Assignee: Research Triangle Institute
    Inventor: Erik Paul Vick
  • Patent number: 9576890
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: February 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
  • Patent number: 9576891
    Abstract: An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The plurality of metal layers have a topmost metal layer disposed furthest away from the substrate and a first interconnect metal layer formed nearest to the substrate. The first interconnect metal layer is disposed at a first distance away from the substrate, whereas the topmost metal layer is disposed at an isolation distance away from a first adjacent metal layer formed nearest to the topmost metal layer. A portion of the topmost metal layer forms a first plate. The first plate is configured to transmit the first signal from the first circuit to a second plate that is connected to the second circuit, but electrically isolated from the first plate.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: February 21, 2017
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Qian Tao, Richard Lum Kok Keong, Boon Keat Tan
  • Patent number: 9576892
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming the same. An embodiment is a method for of forming a semiconductor device, the method including forming a first conductive feature over a substrate, forming a dielectric layer over the conductive feature, and forming an opening through the dielectric layer to the first conductive feature. The method further includes selectively forming a first capping layer over the first conductive feature in the opening, and forming a second conductive feature on the first capping layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Chi, Huang-Yi Huang, Szu-Ping Tung, Ching-Hua Hsieh
  • Patent number: 9576893
    Abstract: A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee
  • Patent number: 9576894
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Sunil Kumar Singh, Ravi Prakash Srivastava, Xusheng Wu, Akshey Sehgal, Teck Jung Tang
  • Patent number: 9576895
    Abstract: A semiconductor device includes a substrate having a plurality of contact surfaces, an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact surfaces and a second open portion which exposes the other contact surfaces, a storage node contact (SNC) plug filling the first open portion, and a damascene structure filing the second open portion and including a bit line, a spacer formed on both sidewalls of the bit line, a capping layer formed over the bit line and the spacer, and an air gap formed between the bit line and the spacer. The bit line includes a conductive material of which the volume is contracted by a heat treatment to form the air gap.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: February 21, 2017
    Assignee: SK Hynix Inc.
    Inventor: Nam-Yeal Lee
  • Patent number: 9576896
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes an interconnect which includes an interconnect metal plug surrounded by a second metal layer. The interconnect is adjacent a sidewall of a dielectric, such that an air gap is between the interconnect and the sidewall of the dielectric. A protective barrier is over the interconnect and the air gap, and is over and in direct physical contact with a top surface of the dielectric. The interconnect metal plug surrounded by the second metal layer is less susceptible to damage than an interconnect metal plug that is not surrounded by a second metal layer. The protective barrier in direct physical contact with the dielectric reduces parasitic capacitance, which reduces an RC delay of the semiconductor arrangement, as compared to a semiconductor arrangement that does not have a protective barrier in direct physical contact with a dielectric.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Chieh Liao, Cheng-Chi Chuang, Tai-I Yang, Tien-Lu Lin, Yung-Hsu Wu
  • Patent number: 9576897
    Abstract: A method for forming an interconnect device is provided by the present disclosure. The method includes providing a dielectric layer on a substrate, forming openings in the dielectric layer to expose a portion of a surface of the substrate at a bottom of each opening and forming a metal layer to fill up the openings. The method also includes forming a semiconductor cover layer on the metal layer and on the dielectric layer, and performing a thermal annealing reaction to convert portions of the semiconductor cover layer that are on the metal layer into a metal capping layer. The method further includes performing a nitridation process on the metal capping layer and a remaining semiconductor cover layer to convert the metal capping layer into a metal nitride capping layer and the remaining semiconductor cover layer into a semiconductor nitride layer.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 21, 2017
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Hao Deng
  • Patent number: 9576898
    Abstract: A resistance structure including: a conductive layer provided at a surface layer portion of a semiconductor substrate; a first resistance element having long sides and short sides provided over the conductive layer with an insulating film interposed; a second resistance element having long sides and short sides provided over the conductive layer with the insulating film interposed and disposed such that one long side thereof opposes one long side of the first resistance element; first wiring that is connected to one end of the first resistance element; second wiring that is connected to one end of the second resistance element; third wiring that connects the other end of the first resistance element with the other end of the second resistance element; and a connection portion that connects any of the first wiring, the second wiring and the third wiring with the conductive layer.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: February 21, 2017
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hisao Ohtake
  • Patent number: 9576899
    Abstract: Electrical fuses and methods for forming an electrical fuse. A semiconductor substrate is implanted to define a modified region in the semiconductor substrate. Trenches that surround the modified region and that penetrate into the semiconductor substrate to a depth greater than a depth of the modified region are formed in the modified region so as to define a fuse link of the electrical fuse. The substrate is removed from beneath the fuse link with a selective etching process that removes the semiconductor substrate with a first etch rate that is higher than a second etch rate of the modified region.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Qizhi Liu, Ian A. McCallum-Cook
  • Patent number: 9576900
    Abstract: A scalable switching regulator architecture has an integrated inductor. In some embodiments an area and current drive capability of switches of the switching regulator is matched with an inductor built within an area above the switches. In some embodiments the combined switches and inductor are constructed as a unit cell and can be combined to form larger elements as required for higher current drive capability and multiphase operation.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: February 21, 2017
    Assignee: Endura Technologies LLC
    Inventor: Taner Dosluoglu
  • Patent number: 9576901
    Abstract: A method for manufacturing a semiconductor device includes forming a contact area opening in a dielectric structure, depositing a contact area metal in the contact area opening, forming a metal cap layer on the contact area metal, forming one or more dielectric layers on the metal cap layer, forming one or more hard mask layers on the one or more dielectric layers, forming a metallization opening through the one or more dielectric and hard mask layers, wherein the metallization opening exposes the metal cap layer, removing the one or more hard mask layers, and forming a metallization layer in the metallization opening on the metal cap layer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: February 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hsueh-Chung Chen, Su Chen Fan, Chih-Chao Yang
  • Patent number: 9576902
    Abstract: A semiconductor device includes conductive lines spaced from a substrate, and an insulating spacer structure between the conductive lines and defining a contact hole. The insulating spacer structure is adjacent a side wall of at least one of the conductive lines. The device also includes an insulating pattern on the conductive lines and insulating spacer structure, and another insulating pattern defining a landing pad hole connected to the contact hole. A contact plug is formed in the contact hole and connects to the active area. A landing pad is formed in the landing pad hole and connects to the contact plug. The landing pad vertically overlaps one of the pair of conductive line structures.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: February 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-min Park, Yoo-sang Hwang
  • Patent number: 9576903
    Abstract: Provided is a structure with a conductive plug including a substrate, a first dielectric layer, an etch stop layer, a second dielectric layer, a conductive plug and a liner. The substrate has a conductive region therein. The first dielectric layer, the etch stop layer and the second dielectric layer are sequentially formed on the substrate and have at least one opening therethrough. Besides, the opening has a substantially vertical sidewall. The conductive plug fills in the opening and is electrically connected to the conductive region. The liner surrounds the upper portion of the conductive plug. A method of forming a structure with a conductive plug is further provided.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: February 21, 2017
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ching-Hsiung Lee, Shih-Chang Tsai
  • Patent number: 9576904
    Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: February 21, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Nishant Sinha, John A. Smythe
  • Patent number: 9576905
    Abstract: A semiconductor device includes a first wiring comprising a first conductive material on a semiconductor layer, a second wiring comprising the first conductive material on the semiconductor layer, a third wiring comprising a second conductive material different from the first conductive material, and an insulation film on the semiconductor layer between the first wiring and the second wiring and between the second wiring and the third wiring. The second wiring is provided on at least two sides of the third wiring, and a mean free path of free electrons in the first conductive material is shorter than a mean free path of free electrons in the second conductive material, or the first conductive material shows quantized conduction and the second conductive material does not show quantized conduction. The first wiring, the second wiring, the third wiring, and the insulation film are in one wiring layer provided on the semiconductor layer.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: February 21, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taishi Ishikura, Atsunobu Isobayashi, Akihiro Kajita
  • Patent number: 9576906
    Abstract: Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a stack disposed over a compound semiconductor, with the stack including a barrier, a copper (Cu) layer disposed over the barrier, and a first titanium (Ti) layer disposed over the Cu layer. The metalized structure can further include a sputtered titanium tungsten (TiW) layer disposed over the first Ti layer. The barrier can include an assembly of titanium nitride (TiN) and Ti layers. The metalized structure can further include a second Ti layer disposed over the sputtered TiW layer.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: February 21, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventor: Kezia Cheng
  • Patent number: 9576907
    Abstract: A wiring structure is made up by electrically connecting a via part made up by forming CNTs in a via hole and a wiring part made up of multilayer graphene on an interlayer insulating film via a metal block such as Cu. In the wiring structure using the CNTs at the via part and the graphene at the wiring part, it is thereby possible to obtain the wiring structure with high reliability enabling a certain electrical connection between the CNTs and the graphene with a relatively simple configuration.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: February 21, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shintaro Sato, Daiyu Kondo, Motonobu Sato, Mizuhisa Nihei
  • Patent number: 9576908
    Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions are present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: February 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Patent number: 9576909
    Abstract: Embodiments of the present disclosure are directed towards bumpless interfaces to an embedded silicon die, in integrated circuit (IC) package assemblies. In one embodiment, a method includes forming a surrounding portion of dielectric material defining a cavity therein; placing at least one die in the cavity, the die including a contact; depositing a dielectric material on the die and the surrounding portion; etching the dielectric material to expose the contact; and depositing conductive material onto the contact. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 21, 2017
    Assignee: INTEL CORPORATION
    Inventors: Weng Hong Teh, John S. Guzek, Robert L. Sankman
  • Patent number: 9576910
    Abstract: A semiconductor structure includes a plurality of devices; a molding surrounding the plurality of devices and including a first surface adjacent to an active component of at least one of the plurality of devices and a second surface opposite to the first surface; and a shielding structure disposed within the molding and between two or more of the plurality of devices, wherein the shielding structure includes a first surface adjacent to the first surface of the molding and a second surface adjacent to the second surface of the molding, and the second surface of the shielding structure includes a recessed portion recessed towards the first surface of the molding.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: February 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Ming-Da Cheng, Jui-Pin Hung
  • Patent number: 9576911
    Abstract: A radio frequency (RF) module comprises an electrical reference, or ground, plane to which one or more RF devices disposed on the module are electrically coupled, and may be disposed beneath the RF devices. The reference plane may be segmented as to form one or more segments of the reference plane that are at least partially electrically isolated from surrounding segments or devices. A module may have a plurality of devices disposed thereon, wherein separate, at least partially isolated reference planes, correspond to different devices of the module. The reference plane may be etched or cut to achieve such segmentation.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: February 21, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Anthony James LoBianco, Hoang Mong Nguyen
  • Patent number: 9576912
    Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor substrate, a back end of line (BEOL) layer on the semiconductor substrate and having a peripheral edge recessed inwardly from an adjacent peripheral edge of the semiconductor substrate. A first dielectric layer is over the BEOL layer and wraps around the peripheral edge of the BEOL layer. A redistribution layer is over the first dielectric layer and a second dielectric layer is over the redistribution layer.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: February 21, 2017
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Yiyi Ma, Kim-Yong Goh, Xueren Zhang
  • Patent number: 9576913
    Abstract: A semiconductor device that improves noise performance includes a circuit substrate, an enclosing case, and a metal part. A control circuit is mounted on the front surface of the circuit substrate. The enclosing case is a resin case in which semiconductor elements are installed. The metal part, included inside the enclosing case, includes a first mounting portion, a second mounting portion, and a bus bar. The first mounting portion mounts the circuit substrate on the enclosing case, and is connected to a ground pattern of the circuit substrate when mounting. The second mounting portion mounts an external instrument on the enclosing case, and is grounded when mounting. The bus bar connects the first mounting portion and second mounting portion.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: February 21, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: 9576914
    Abstract: A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang
  • Patent number: 9576915
    Abstract: Consistent with an example embodiment, a System on Chip (SoC) device operates in millimeter wave frequencies. The SoC device comprises, a silicon device having at least one differential pair pad, the at least one differential pair pad having a shunt inductor coupled thereon. A parasitic capacitance on at least one differential pair pads is tuned out by resonance of the shunt inductor. A package has a redistribution layer (RDL), with an array of contact areas to which the silicon device is mounted and then encapsulated. A connection corresponds to the at least one differential pair pad and the connection is located about an outer row or column of the array of contact areas.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: February 21, 2017
    Assignee: NXP B.V.
    Inventors: Mingda Huang, Markus Carolus Antonius van Schie
  • Patent number: 9576916
    Abstract: A high frequency circuit includes a first electronic device, a second electronic device, and a graphene interconnection unit, where at least one of a trench and a via is defined under the graphene interconnection unit.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: February 21, 2017
    Assignees: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Hyeon-jin Shin, Jae-young Choi, Seong-chan Jun, Whan-kyun Kim, Hyung-seo Yoon, Ju-yeong Oh, Ju-hwan Lim