Patents Issued in February 21, 2017
  • Patent number: 9577169
    Abstract: Techniques are disclosed for integrating the LED lead frame into the LED circuit fabrication process. The LED packages within the lead frame may be spaced according to the final spacing of the LED packages on the finished circuit board, such that multiple LED packages may be attached to a circuit board at a time by applying the lead frame to circuit board and then removing portions of the lead frame, leaving the LED packages attached to the board. The LED packages may be attached using solder or conductive epoxy, in some embodiments. Alternatively, part of the lead frame may include conductive wires forming one or more strings of LED packages. An entire string of LED packages may then be removed from the lead frame in a single motion and placement may be performed for a string of LED packages all at once rather than for individual LED packages.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: February 21, 2017
    Assignee: OSRAM SYLVANIA Inc.
    Inventor: Richard Speer
  • Patent number: 9577170
    Abstract: A light-emitting device is disclosed. The light-emitting device comprises a supportive substrate; a first light-emitting element and a second light-emitting element on the supportive substrate, wherein the first light-emitting element comprises a transparent layer on the supportive substrate, a first light-emitting stacked layer on the transparent layer, and a plurality of contact parts between the transparent layer and the first light-emitting stacked layer; and the second light-emitting element comprises an electrode and a second light-emitting stacked layer between the electrode and the supportive substrate; and a metal line on the supportive substrate and electrically connecting the electrode and one of the contact parts.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: February 21, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-I Chen, Chia-Liang Hsu, Tzu-Chieh Hsu, Han-Min Wu, Ye-Ming Hsu, Chien-Fu Huang, Chao-Hsing Chen, Chiu-Lin Yao, Hsin-Mao Liu, Chien-Kai Chung
  • Patent number: 9577171
    Abstract: Disclosed herein is a light emitting device. The light emitting device is provided to include a light emitting structure, a first electrode pad, a second electrode pad and a heat dissipation pad, and a substrate on which the light emitting diode is mounted. The substrate includes a base; an insulation pattern formed on the base; and a conductive pattern disposed on the insulation pattern. The base includes a post and a groove separating the post from the conductive pattern. An upper surface of the post is placed lower than an upper surface of the conductive pattern, the heat dissipation pad contacts the upper surface of the post, and the first electrode pad and the second electrode pad contact the conductive pattern. With this structure, the light emitting device has excellent properties in terms of electrical stability and heat dissipation efficiency.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: February 21, 2017
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: So Ra Lee, Chang Yeon Kim, Ju Yong Park, Sung Su Son
  • Patent number: 9577172
    Abstract: The present invention relates to a light emitting die component formed by multilayer structures.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: February 21, 2017
    Assignee: Koninklijke Philips N.V.
    Inventor: Toni Lopez
  • Patent number: 9577173
    Abstract: Nanoscale thermocouples are made of a single material and are shape-engineered to contain one or more variations in their width along their length. The mono-metallic nanowire junctions resulting from the width variation(s) exploit a difference in the Seebeck coefficient that is present at these size scales. Such devices have a wide variety of uses and can be coupled with an antenna in order to serve as an infrared detector.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: February 21, 2017
    Assignee: University of Notre Dame du Lac
    Inventors: Wolfgang Porod, Gary H. Bernstein, Alexei Orlov, Gergo P. Szakmany
  • Patent number: 9577174
    Abstract: A process for forming a doped nc-Si thin film thermoelectric material. A nc-Si thin film is slowly deposited on a substrate, either by hot-wire CVD (HWCVD) with a controlled H2:SiH4 ratio R=6-10 or by plasma-enhanced (PECVD) with a controlled R=80-100, followed by ion implantation of an n- or p-type dopant and a final annealing step to activate the implanted dopants and to remove amorphous regions. A doped nc-Si thin film thermoelectric material so formed has both a controllable grain size of from a few tens of nm to 3 nm and a controllable dopant distribution and thus can be configured to provide a thermoelectric material having predetermined desired thermal and/or electrical properties. A final annealing step is used to activate the dopants and remove any residual amorphous regions.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: February 21, 2017
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Xiao Liu, Thomas H. Metcalf, Daniel R. Queen, Battogtokh Jugdersuren, Qi Wang, William Nemeth
  • Patent number: 9577175
    Abstract: An apparatus includes a base layer; and a superconducting nanowire disposed on the base layer in a continuous meander pattern and including an amorphous metal-metalloid alloy such that the apparatus is configured to detect single photons, and the continuous meander pattern includes: a plurality of parallel line segments; and a plurality of curved segments, wherein adjacent parallel line segments are joined by a curved segment.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: February 21, 2017
    Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventors: Sae Woo Nam, Burm Baek, Francesco Marsili, Varun Verma
  • Patent number: 9577176
    Abstract: A detector for detecting single photons of infrared radiation. In one embodiment a waveguide configured to transmit infrared radiation is arranged to be adjacent a graphene sheet and configured so that evanescent waves from the waveguide overlap the graphene sheet. An infrared photon absorbed by the graphene sheet from the evanescent waves heats the graphene sheet. The graphene sheet is coupled to the weak link of a Josephson junction, and a constant bias current is driven through the Josephson junction, so that an increase in the temperature of the graphene sheet results in a decrease in the critical current of the Josephson junction and a voltage pulse in the voltage across the Josephson junction. The voltage pulse is detected by the pulse detector.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: February 21, 2017
    Assignee: RAYTHEON BBN TECHNOLOGIES CORP.
    Inventors: Kin Chung Fong, Thomas A. Ohki
  • Patent number: 9577177
    Abstract: A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: February 21, 2017
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Ari D. Brown, Vilem Mikula
  • Patent number: 9577178
    Abstract: A piezoelectric device that prevents defects due to pyroelectric charge without limiting how the piezoelectric device can be used includes a first metal layer located on a bonding surface of a piezoelectric single crystal substrate. A second metal layer is located on a bonding surface of a support substrate. The first and second metal layers are overlaid on each other to define a metal bonded layer. Subsequently, by oxidizing the metal bonded layer, a semi-conducting layer is formed.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: February 21, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Iwamoto
  • Patent number: 9577179
    Abstract: A magnetic logic cell includes a first electrode portion, a magnetic portion arranged on the first electrode, the magnetic portion including an anti-ferromagnetic material or a ferrimagnetic material, a dielectric portion arranged on the magnetic portion, and a second electrode portion arranged on the dielectric portion.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 21, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ALABAMA
    Inventors: Marcin J. Gajek, Daniel C. Worledge, William H. Butler
  • Patent number: 9577180
    Abstract: A magnetic logic cell includes a first electrode portion, a magnetic portion arranged on the first electrode, the magnetic portion including an anti-ferromagnetic material or a ferrimagnetic material, a dielectric portion arranged on the magnetic portion, and a second electrode portion arranged on the dielectric portion.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 21, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ALABAMA
    Inventors: Marcin J. Gajek, Daniel C. Worledge, William H. Butler
  • Patent number: 9577181
    Abstract: A magnetic junction usable in a magnetic device is described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, an asymmetric free layer and a perpendicular magnetic anisotropy (PMA) inducing layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer is between the nonmagnetic spacer layer and the PMA inducing layer. The asymmetric free layer includes a first ferromagnetic layer having a first boron content and a second ferromagnetic layer having a second boron content. The second boron content is less than the first boron content. The first boron content and the second boron content are each greater than zero atomic percent. The first and second ferromagnetic layers each contain at least one of Co and CoFe. The magnetic junction is configured such that the asymmetric free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: February 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Xueti Tang, Jangeun Lee
  • Patent number: 9577182
    Abstract: A magnetoresistance effect element and a magnetic memory having thermal stability expressed by a thermal stability factor of 70 or more even with a fine junction size. The magnetoresistance effect element includes a first magnetic layer of an invariable magnetization direction forming a reference layer, a second magnetic layer of a variable magnetization direction forming a recording layer, and a first non-magnetic layer disposed between the first and second magnetic layers in a thickness direction of the first and second magnetic layers. At least one of the first and second magnetic layers has the following relationship between D (nm) and t (nm): D<0.9t+13, where D is a junction size corresponding to the length of a longest straight line on an end surface perpendicular to the thickness direction, and t is a layer thickness. The junction size is 30 nm or less.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: February 21, 2017
    Assignee: TOHOKU UNIVERSITY
    Inventors: Shoji Ikeda, Hideo Sato, Shunsuke Fukami, Michihiko Yamanouchi, Fumihiro Matsukura, Hideo Ohno, Shinya Ishikawa
  • Patent number: 9577183
    Abstract: In a method of manufacturing a MRAM device, a lower electrode is formed on a substrate. A first magnetic layer, a tunnel barrier layer, and a second magnetic layer are sequentially formed on the lower electrode layer. An etching mask is formed on the second magnetic layer. An ion beam etching process in which a first ion beam and a second ion beam are simultaneously emitted onto the substrate is performed to form a MTJ structure including a first magnetic layer pattern, a tunnel layer pattern, and a second magnetic layer pattern from the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, respectively, the MTJ structure has no by-products remaining after the ion beam etching process is performed.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: February 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-Sun Kim, Woo-Jin Kim, Ken Tokashiki
  • Patent number: 9577184
    Abstract: A TMR sensor that includes a free layer having at least one B-containing (BC) layer made of CoFeB, CoFeBM, CoB, CoBM, or CoBLM, and a plurality of non-B containing (NBC) layers made of CoFe, CoFeM, or CoFeLM is disclosed where L and M are one of Ni, Ta, Ti, W, Zr, Hf, Tb, or Nb. One embodiment is represented by (NBC/BC)n where n?2. A second embodiment is represented by (NBC/BC)n/NBC where n?1. In every embodiment, a NBC layer contacts the tunnel barrier and NBC layers each with a thickness from 2 to 8 Angstroms are formed in alternating fashion with one or more BC layers each 10 to 80 Angstroms thick. Total free layer thickness is <100 Angstroms. The free layer configuration described herein enables a significant noise reduction (SNR enhancement) while realizing a high TMR ratio, low magnetostriction, low RA, and low Hc values.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 21, 2017
    Assignee: Headway Technologies, Inc.
    Inventors: Tong Zhao, Hui-Chuan Wang, Yu-Chen Zhou, Min Li, Kunliang Zhang
  • Patent number: 9577185
    Abstract: An integrated fluxgate device, which includes a magnetic core, an excitation coil, and a sense coil. The magnetic core has a longitudinal edge and a terminal edge. The excitation coil coils around the longitudinal edge of the magnetic core, and the excitation coil has a first number of excitation coil members within a proximity of the terminal edge. The sense coil coils around the longitudinal edge of the magnetic core, and the sense coil has a second number of sense coil members within the proximity of the terminal edge. For reducing fluxgate noise, the second number of sense coil members may be less than the first number of excitation coil members within the proximity of the terminal edge.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: February 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dok Won Lee, Sudtida Lavangkul, Erika Lynn Mazotti, William David French
  • Patent number: 9577186
    Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 21, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Bhaskar Srinivasan, Gurtej Sandhu, John Smythe
  • Patent number: 9577187
    Abstract: The present invention provides a memory element and a memory device realizing reduced variations in resistance values in an initial state or erase state of a plurality of memory elements and capable of retaining the resistance value in a write/erase state for writing/erasing operations of a plurality of times. The memory element includes a first electrode, a memory layer, and a second electrode in order. The memory layer has: an ion source layer containing at least one of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and at least one metal element selected from copper (Cu), silver (Ag), zinc (Zn), and zirconium (Zr); and two or more high-resistance layers having a resistance value higher than that of the ion source layer and having different compositions.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: February 21, 2017
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Akihiro Maesaka, Kazuhiro Ohba, Tetsuya Mizuguchi, Koji Miyata, Motonari Honda, Katsuhisa Aratani
  • Patent number: 9577188
    Abstract: Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: February 21, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Carmela Cupeta, Andrea Redaelli, Paolo Giuseppe Cappelletti
  • Patent number: 9577189
    Abstract: A method of forming an RRAM cell structure is provided. The method includes forming dummy features over a substrate, and the dummy features have a gap therebetween. The method also includes depositing an oxide layer over the dummy features while forming a first V-shaped valley on the oxide layer. The method further includes partially planarizing the oxide layer while leaving the first V-shaped valley. In addition, the method includes forming a first electrode over the oxide layer while forming a second V-shaped valley on the first electrode. The method further includes forming a resistance variable layer over the first electrode in a conformal manner. The method still includes forming a second electrode over the resistance variable layer.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Hsing-Chih Lin
  • Patent number: 9577190
    Abstract: Heat-trapping bulk layers or thermal-boundary film stacks are formed between a heat-assisted active layer and an associated electrode to confine such transient heat to the active layer in a heat-assisted device (e.g., certain types of resistance-switching and selector elements used in non-volatile memory. Preferably, the heat-trapping layers or thermal-boundary stacks are electrically conductive while being thermally insulating or reflective. Heat-trapping layers use bulk absorption and re-radiation to trap heat. Materials may include, without limitation, chalcogenides with Group 6 elements. Thermal-boundary stacks use reflection from interfaces to trap heat and may include film layers as thin as 1-5 monolayers. Effectiveness of a thermal-boundary stack depends on the thermal impedance mismatch between layers of the stack, rendering thermally insulating bulk materials optional for thermal-boundary stack components.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: February 21, 2017
    Assignee: INTEL CORPORATION
    Inventors: Elijah V. Karpov, Prashant Majhi, Niloy Mukherjee, Ravi Pillarisetty, Uday Shah, Brian S. Doyle, Robert S. Chau
  • Patent number: 9577191
    Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Trinh Hai Dang, Hsing-Lien Lin, Kai-Wen Cheng, Cheng-Yuan Tsai, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 9577192
    Abstract: Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: February 21, 2017
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Muralikrishnan Balakrishnan, Zailong Bian, Gowrisankar Damarla, Hongqi Li, Jin Lu, Shyam Ramalingam, Xiaoyun Zhu
  • Patent number: 9577193
    Abstract: A method of forming a thin film, the method including: disposing a resist portion on a substrate, the resist portion including: a first region including a first upper surface; and a second region including a second upper surface, the first upper surface disposed higher than the second upper surface and forming a step; disposing a first protection layer covering the resist portion; exposing the first upper surface; removing the first region; disposing a first thin film on the substrate; disposing a second protection layer covering the first thin film; exposing the second upper surface; removing the second region; disposing a second thin film on the substrate; and removing the first protection layer and the second protection layer.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: February 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hanjun Kim
  • Patent number: 9577194
    Abstract: A composition comprising: at least one compound comprising a hole transporting core, wherein the core is covalently bonded to a first arylamine group and also covalently bonded to a second arylamine group different from the first, and wherein the compound is covalently bonded to at least one intractability group, wherein the intractability group is covalently bonded to the hole transporting core, the first arylamine group, the second arylamine group, or a combination thereof, and wherein the compound has a molecular weight of about 5,000 g/mole or less. Blended mixtures of arylamine compounds, including fluorene core compounds, can provide good film formation and stability when coated onto hole injection layers. Solution processing of OLEDs is a particularly important application.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: February 21, 2017
    Assignee: NISSAN CHEMICAL INDUSTRIES, LTD.
    Inventors: Christopher T. Brown, Neetu Chopra, Christopher R. Knittel, Mathew Mathai, Venkataramanan Seshadri, Jing Wang, Brian Woodworth
  • Patent number: 9577195
    Abstract: A method of manufacturing a substrate of an organic light-emitting display device, the method including: forming, on a first surface of a transparent substrate, a photothermal conversion layer configured to covert incident light into thermal energy; forming partition walls on the first surface in a first region of the photothermal conversion layer, the partition walls including a photosensitive compound including a resorcinarene, the resorcinarene including a perfluorocarbon group; forming an organic material layer on the first surface in a second region of the photothermal conversion layer, the second region being defined by the partition walls; removing the partition walls; placing a target substrate over the organic material layer; and applying light to a second surface of the transparent substrate, the second surface being opposite the first surface of the transparent substrate.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: February 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Young Gil Kwon
  • Patent number: 9577196
    Abstract: A method for fabricating an optoelectronic device includes forming an adhesion layer on a substrate, forming a material layer on the adhesion layer and applying release tape to the material layer. The substrate is removed at the adhesion layer by mechanically yielding the adhesion layer. A conductive layer is applied to the material layer on a side opposite the release tape to form a transfer substrate. The transfer substrate is transferred to a target substrate to join the target substrate to the conductive layer of the transfer substrate. The release tape is removed from the material layer to form a top emission optoelectronic device.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Tze-bin Song
  • Patent number: 9577197
    Abstract: The invention relates to novel polymers containing one or more 3,7-dialkyl-benzo[1,2-b:4,5-b?]dithiophene repeating units, methods for their preparation and monomers used therein, blends, mixtures and formulations containing them, the use of the polymers, blends, mixtures and formulations as semiconductor in organic electronic (OE) devices, especially in organic photovoltaic (OPV) devices, and to OE and OPV devices comprising these polymers, blends, mixtures or formulations.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: February 21, 2017
    Assignee: MERCK PATENT GmbH
    Inventors: Amy Phillips, Nicolas Blouin, William Mitchell, Steven Tierney
  • Patent number: 9577198
    Abstract: Compounds according to Formulas 1-33 may be useful in electronic devices such as light-emitting devices. For example, they may be used as hole-transport materials.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: February 21, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventor: Shijun Zheng
  • Patent number: 9577199
    Abstract: This invention relates to deuterated aryl-anthracene compounds that are useful in electronic applications. It also relates to electronic devices in which the active layer includes such a deuterated compound.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: February 21, 2017
    Assignee: E I DU PONT NEMOURS AND COMPANY
    Inventors: Daniel David Lecloux, Adam Fennimore, Weiying Gao, Nora Sabina Radu, Weishi Wu, Vsevolod Rostovtsev, Michael Henry Howard, Jr., Hong Meng, Yulong Shen, Jeffrey A Merlo, Eric Maurice Smith
  • Patent number: 9577200
    Abstract: Triphenylene containing benzo-fused thiophene compounds are provided. Additionally, triphenylene containing benzo-fused furan compounds are provided. The compounds may be useful in organic light emitting devices, particularly as hosts in the emissive layer of such devices, or as materials for enhancement layers in such devices, or both.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: February 21, 2017
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Bin Ma, Yonggang Wu, Chun Lin, Raymond Kwong
  • Patent number: 9577201
    Abstract: A compound including a ligand having the formula: is disclosed. In these formulas, each R1, R2, and R3 is independently selected from hydrogen, alkyl, and aryl; at least one of R1 and R2 is a branched alkyl containing at least 4 carbon atoms, where the branching occurs at a position further than the benzylic position; where R1 and R3 are mono-, di-, tri-, tetra-, or no substitutions; and R2 is mono-, di-, or no substitutions. Heteroleptic iridium complexes including such compounds, and devices including such compounds are also disclosed.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: February 21, 2017
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Raymond Kwong, Bin Ma, Chuanjun Xia, Bert Alleyne, Jason Brooks
  • Patent number: 9577202
    Abstract: A flexible display substrate mother board and a method of manufacturing a flexible display substrate are provided. The method includes: forming a heating pattern layer on a support substrate, wherein the heating pattern layer includes a plurality of regional blocks spaced apart from each other; forming a flexible substrate on the substrate provided with the heating pattern layer, and forming display elements on the flexible substrate; and heating the flexible substrate by utilization of the heating pattern layer, cutting the flexible substrate, stripping the flexible substrate corresponding to the regional block from the support substrate, and forming flexible display substrates. The method can avoid the damage of the display elements on the flexible substrate when the flexible substrate and the support substrate are separated from each other, and avoid uneven separation.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: February 21, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Ming Che Hsieh, Chunyan Xie, Lu Liu
  • Patent number: 9577203
    Abstract: An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate including a bending area and a non-bending area and a plurality of thin-film transistors (TFTs) formed in the non-bending area. The display also includes a plurality of first pixel electrodes and a plurality of second pixel electrodes formed over the TFTs and electrically connected to the TFTs, the first pixel electrodes formed in the bending area and the second pixel electrodes formed in the non-bending area.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: February 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Younjoon Kim, Yunmo Chung, Sangjo Lee
  • Patent number: 9577204
    Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the dielectric layer. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. Metal contacts are formed on the channel material in the openings in the patterned resist layer and over portions of the patterned resist layer to protect sidewalls of the metal contacts to prevent degradation of the metal contacts.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shu-Jen Han, Jianshi Tang
  • Patent number: 9577205
    Abstract: An organic light-emitting device including a first light-emitting region, a second light-emitting region, and a third light-emitting region. The organic light-emitting device includes a substrate; a first electrode layer on the substrate; a hole injection layer on the first electrode layer; a common emission layer on the hole injection layer; a first resonance assistance layer on the common emission layer in the first light-emitting region and a second resonance assistance layer on the common emission layer in the second light-emitting region.
    Type: Grant
    Filed: September 14, 2013
    Date of Patent: February 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byeong-Wook Yoo, Sang-Woo Pyo, Ha-Jin Song, Hyo-Yeon Kim, Hye-Yeon Shim, Ji-Young Kwon, Heun-Seung Lee, Ji-Hwan Yoon
  • Patent number: 9577206
    Abstract: The present disclosure relates to an organic electroluminescence element including: a substrate having a light transmissive property; a light diffusion layer; a light transmissive electrode; a light reflective electrode; and multiple light emitting layers spaced from each other. With regard to the m-th light emitting layer being the m-th closest light emitting layer to the light reflective electrode, relations defined by following expressions (2) and (3) are satisfied. In the following expressions, ?m represents the weighted average emission wavelength, Ø(?m) represents the phase shift, nm(?m) represents the average refractive index of a medium filling a space between the light reflective electrode and the m-th light emitting layer, and dm represents the distance from the light reflective electrode to the m-th light emitting layer. l is an integer equal to or more than 0. ? [ FORMULA ? ? 1 ] ? ? ( ? m ) × ? m 4 ? ? ? + l + 0.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: February 21, 2017
    Assignee: PANASONIC CORPORATION
    Inventors: Kazuyuki Yamae, Nobuhiro Ide, Hitomichi Takano
  • Patent number: 9577207
    Abstract: Disclosed is an organic light emitting display device. The organic light emitting display device includes a substrate, a pixel electrode disposed on the substrate, an organic emission layer disposed on the pixel electrode, a common electrode including a metal layer disposed on the organic emission layer, a conductive organic layer disposed on the metal layer, and a first metal oxide layer disposed on the conductive organic layer, and an insulating part formed in a part of an area of a surface of the metal layer which is exposed to a foreign material. The insulating part insulates the pixel electrode from the common electrode.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: February 21, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Young Mi Kim, Joon Young Heo, Yeon Kyeong Lee
  • Patent number: 9577208
    Abstract: An organic light emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a substrate, a plurality of transistors formed over the substrate and a passivation layer covering the transistors. The OLED display also includes an OLED formed over the passivation layer and including a pixel electrode, an organic emission layer, and a common electrode. The pixel electrode includes a first curved portion that does not overlap the organic emission layer in the depth dimension of the OLED display.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: February 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Kyu Lee, Chae Han Hyun
  • Patent number: 9577209
    Abstract: The present invention focuses on a structure in which an auxiliary wiring for increasing the conductivity of an upper electrode is provided on the substrate side. The conductive auxiliary wiring of a light-emitting device is provided over a substrate, and an upper portion of the auxiliary wiring protrudes in a direction parallel to the substrate. Further, an EL layer formed in a region including a lower electrode layer and the auxiliary wiring is physically divided by the auxiliary wiring. An upper electrode layer formed in a manner similar to that of the lower electrode layer may be electrically connected to at least part of a side surface of the auxiliary wiring. Such an auxiliary wiring may be used in a lighting device and a display device.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: February 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshifumi Tanada, Naoya Sakamoto, Hiroki Adachi, Shingo Eguchi, Koji Ono, Kensuke Yoshizumi, Hiroto Shinoda
  • Patent number: 9577210
    Abstract: A method for producing top-emission organic EL display device, in which, using cover material having flexibility such as resin film, space between organic EL layer-side substrate and cover material is made into decompressed state, thereafter, adhesion properties between organic EL layer-side substrate and cover material is maintained by retaining decompressed state in the space between organic EL layer-side substrate and cover material when adhering organic EL layer-side substrate and cover material by adjusting pressure of space on opposite side to the organic EL layer-side substrate, in relation to cover material so that deterioration in display properties can be restrained by preventing organic layer on auxiliary electrode removed by laser light from being scattered on pixel area. In the method for producing top-emission organic EL display device described above, resin film including barrier property with oxygen permeability of 100 cc/m2·day or less is used as the cover material.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: February 21, 2017
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Takayoshi Nirengi, Toshihiko Takeda
  • Patent number: 9577211
    Abstract: Provided are an organic electronic element equipped with a sealing layer having excellent gas barrier properties, transparency and the like, and a method for efficiently manufacturing such an organic electronic element. Disclosed are an organic electronic element including, on a substrate, a first electrode and a second electrode facing each other, with at least one organic functional layer being interposed therebetween, and a method for manufacturing such an organic electronic element, characterized in that a sealing layer is directly provided along the top surface and the lateral surface of the organic electronic element, and the sealing layer is obtained by implanting plasma ions into a coating film containing a silicon compound as a main component.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: February 21, 2017
    Assignee: LINTEC CORPORATION
    Inventor: Satoshi Naganawa
  • Patent number: 9577212
    Abstract: A display device includes a substrate, a display unit formed on the substrate, a sealing substrate bonded to the substrate by a bonding layer surrounding the display unit, the sealing substrate comprising a complex member and an insulating member, wherein the complex member has a resin matrix and a plurality of carbon fibers and the insulator is connected to an edge of the complex member and comprises a penetration hole, a metal layer disposed at one side of the sealing substrate wherein the one side faces the substrate, and a conductive connection unit filling in the penetration hole and contacting the metal layer. The complex member and the insulator may be coupled by tongue and groove coupling along a thickness direction of the sealing substrate where the protrusion-groove coupling structure is top-to-bottom symmetric and the insulator may have a thickness identical to that of the complex member.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: February 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung-Min Lee, Choong-Ho Lee, Kie Hyun Nam
  • Patent number: 9577213
    Abstract: An organic electroluminescence display device includes: a lower electrode that is made of a conductive inorganic material and formed in each of pixels arranged in a matrix in a display area; a light-emitting organic layer that is in contact with the lower electrode and made of a plurality of different organic material layers including a light-emitting layer emitting light; an upper electrode that is in contact with the light-emitting organic layer, formed so as to cover the whole of the display area, and made of a conductive inorganic material; and a conductive organic layer that is in contact with the upper electrode, formed so as to cover the whole of the display area, and made of a conductive organic material.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: February 21, 2017
    Assignee: Japan Display Inc.
    Inventors: Toshihiro Sato, Hironori Toyoda
  • Patent number: 9577214
    Abstract: Provided are an adhesive film, an encapsulated product of an organic electronic device using the same, and a method of encapsulating an organic electronic device. Particularly, the adhesive film encapsulating the organic electronic device to cover an entire surface of the organic electronic device includes an adhesive layer including a curable resin and a moisture adsorbent. The adhesive layer has a viscosity in a temperature range of 30 to 130° C. of 101 to 106 Pa·s and a viscosity at room temperature of 106 Pa·s or more in an uncured state, and when the adhesive layer has a multilayered structure, a difference in melting viscosity between layers is less than 30 Pa·s. In addition, the method of encapsulating an organic electronic device using the adhesive film is provided.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: February 21, 2017
    Assignee: LG Chem, Ltd.
    Inventors: Hyun Jee Yoo, Yoon Gyung Cho, Seung Min Lee, Suk Ky Chang, Jung Sup Shim
  • Patent number: 9577215
    Abstract: A display device includes: a substrate on which a display is formed; an encapsulation portion covering the substrate; and a sealing portion arranged between the substrate and the encapsulation portion and surrounding the display, wherein at least one power wire passes between the substrate and the encapsulation portion, and wherein a metal layer is formed between the sealing portion and the at least one power wire.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sangmin Hong
  • Patent number: 9577216
    Abstract: The present disclosure relates to the field of organic electroluminescence and provides an OLED display device, a non-contact IC card and a flexible display device. The OLED display device includes a substrate, an encapsulation structure arranged above the substrate, and an OLED arranged between the substrate and the encapsulation structure. A region where an integrated circuit of the display device is bonded is arranged between the substrate and the OLED.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: February 21, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Seiji Fujino, Guodong Huang, Xiaohu Wang
  • Patent number: 9577217
    Abstract: The present invention provides an organic electroluminescent element containing: a first gas barrier layer; an intermediate layer; a second gas barrier layer; a third gas barrier layer; a first electrode; an organic functional layer; and a second electrode, in that order, wherein the intermediate layer contains a resin and has a thickness of 10 ?m to 250 ?m; the second gas barrier layer contains silicon, carbon and oxygen, wherein a composition of silicon, carbon and oxygen contained in the second gas barrier layer is continuously changed in a thickness direction of the second gas barrier layer, and distribution curves of silicon, carbon and oxygen each have an extremum point; and the third gas barrier layer is a polysilazane reforming layer.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: February 21, 2017
    Assignee: KONICA MINOLTA, INC.
    Inventor: Shota Hirosawa
  • Patent number: 9577218
    Abstract: When attaching a substrate with an EL element formed thereon and a transparent sealing substrate, the periphery of a pixel portion is surrounded with a first sealing agent that maintains a gap between the two pieces of substrates, an entire surface of the pixel portion is covered with a second transparent sealing agent so that the two pieces of substrate is fixed with the first sealing agent and the second sealing agent. Consequently, the EL element can be encapsulated by curing the first sealing agent and the second sealing agent without enclosing a drying agent and doing damage to the EL element due to UV irradiation even when a sealing device only having a function of UV irradiation is used.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: February 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tomoyuki Kurihara