Abstract: Memory openings and support openings are formed through an alternating stack of insulating layers and spacer material layers over a semiconductor substrate. Deposition of a semiconductor material in the support openings during formation of epitaxial channel portions in the memory openings is prevented by Portions of the semiconductor substrate that underlie the support openings are converted into impurity-doped semiconductor material portions. During selective growth of epitaxial channel portions from the semiconductor substrate within the memory openings, growth of a semiconductor material in the support openings is suppressed due to the impurity species in the impurity-doped semiconductor material portions. Memory stack structures and support pillar structures are subsequently formed over the epitaxial channel portions and in the support openings, respectively.

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Abstract: An IC device includes a polycrystalline silicon thin film interposed between a first level semiconductor circuit and a second level semiconductor circuit which are formed on a substrate and disposed to vertically overlap each other. The polycrystalline silicon thin film includes at least one silicon single crystal. The at least one silicon single crystal includes a flat horizontal portion, which provides an active region of the second level semiconductor device, and a pin-shaped protruding portion protruding from the flat horizontal portion toward the first level semiconductor device.

Abstract: A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer.

Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.

Abstract: A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two stacked structures are formed a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer. A charge trapping structure and a channel layer are formed. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched and part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the first dielectric layers and the second dielectric layers to connect the channel layer.

Abstract: Disclosed is a semiconductor device, including: stack structures including interlayer insulating patterns and conductive line patterns, which are alternately stacked, and separated by a first slit; string pillars passing through the stack structures; and dummy holes passing through top portions of the stack structures to be spaced apart from bottom surface of the stack structures and disposed between the string pillars.

Abstract: A method of manufacturing a semiconductor device includes forming on a lower structure, a first stack structure in which first material layers and second material layers are alternately stacked, forming, on the first stack structure, a second stack structure in which third material layers and fourth material layers are alternately stacked, forming preliminary holes penetrating the second stack structure, forming a fifth material layer covering the preliminary holes on the second stack structure to define a first air-gap inside the preliminary holes, and forming through holes connected to the preliminary holes by penetrating from the fifth material layer overlapping the preliminary holes to the first stack structure.

Abstract: A vertically repeating stack of a unit layer stack is formed over a substrate. The unit layer stack includes a sacrificial material layer, a lower silicon oxide material layer, a first silicon oxide material layer, and an upper silicon oxide material layer. A memory opening can be formed through the vertically repeating stack, and a layer stack including a blocking dielectric layer, a memory material layer, a tunneling dielectric, and a semiconductor channel can be formed in the memory opening. The sacrificial material layers are replaced with electrically conductive layers. The first silicon oxide material layer can be removed to form backside recesses. Optionally, portions of the memory material layer can be removed to from discrete charge storage regions. The backside recesses can be filled with a low-k dielectric material and/or can include cavities within a dielectric material to provide reduced coupling between electrically conductive layers.

Abstract: A 3D memory device includes a multi-layer stacks structure having a plurality of conductive strips and a first, a second, a third and a fourth ridge stack; a first SSL switch, a first GSL switch, a second SSL switch and a second GSL switch respectively disposed on the first, the second the third and the fourth ridge stack; a first U-shaped memory cells string connecting the first SSL switch with the first GSL switch; a second U-shaped memory cells string connecting the second SSL switch with the second GSL switch; a first word lines contact in contact with the conductive strips disposed in the first ridge stack; a second word lines contact in contact with the conductive strips disposed in the second ridge stack; and a third word lines contact in contact with the conductive strips disposed in the third ridge stack and the fourth ridge stack.

Abstract: A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.

Abstract: A semiconductor integrated circuit (IC) may comprise at least one cell comprising at least one fin field-effect transistor (FET). The at least one cell may comprise a plurality of fins that extend in a first direction and are arranged in parallel to each other in a second direction that is perpendicular to the first direction. A size of the at least one cell in the second direction may correspond to a number and a pitch of the plurality of fins.

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

Abstract: FinFET devices are formed on the same semiconductor structure wherein at least one finFET device has a gate dielectric structure that is different in thickness relative to a gate dielectric structure of at least one other finFET device. The finFET devices are formed as part of the same fabrication process.

Abstract: By providing appropriate TFT structures arranged in various circuits of the semiconductor device in response to the functions required by the circuits, it is made possible to improve the operating performances and the reliability of a semiconductor device, reduce power consumption as well as realizing reduced manufacturing cost and increase in yield by lessening the number of processing steps. An LDD region of a TFT is formed to have a concentration gradient of an impurity element for controlling conductivity which becomes higher as the distance from a drain region decreases. In order to form such an LDD region having a concentration gradient of an impurity element, the present invention uses a method in which a gate electrode having a taper portion is provided to thereby dope an ionized impurity element for controlling conductivity accelerated in the electric field so that it penetrates through the gate electrode and a gate insulating film into a semiconductor layer.

Abstract: A display device is manufactured with five photolithography steps: a step of forming a gate electrode, a step of forming a protective layer for reducing damage due to an etching step or the like, a step of forming a source electrode and a drain electrode, a step of forming a contact hole, and a step of forming a pixel electrode. The display device includes a groove portion which is formed in the step of forming the contact hole and separates the semiconductor layer.

Abstract: A driver circuit includes a circuit 200, a transistor 101_1, and a transistor 101_2. A signal is selectively input from the circuit 200 to a gate of the transistor 101_1 and the transistor 101_2, so that the transistor 101_1 and the transistor 101_2 are controlled to be on or off. The transistor 101_1 and the transistor 101_2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.

Abstract: A conductive layer for a thin film transistor (TFT) array panel includes a multi-layered portion defining a source electrode and a drain electrode of a TFT device, and includes a first sub-layer, a second sub-layer, a third sub-layer, and at least one additional sub-layer. The third and the first sub-layers include indium and zinc oxide materials. An indium to zinc content ratio in the first sub-layer is greater than that in the third sub-layer. An indium to zinc content ratio in the additional sub-layer is formulated between that in the first and the third sub-layers. The content ratio differentiation between the first and the third sub-layers affects a lateral etch profile associated with a gap generated in the second conductive layer between the source and the drain electrodes, where the associated gap width in the third sub-layer is wider than that that in the first sub-layer.

Abstract: A liquid crystal display device includes a TFT substrate having a display region with first and second electrodes, TFTs, scanning signal lines connected to the TFTs, a counter substrate, a liquid crystal layer sandwiched between the TFT substrate and counter substrates, and sealed by a sealant, scanning line leads connected to the scanning signal lines and formed outside of the display region, video signal line leads connected to the video signal lines and formed outside of the display region and a shield electrode formed on the TFT substrate covering the scanning line leads but not the video signal line leads. The second electrode is connected to a TFT, and liquid crystal molecules of the liquid crystal layer are driven by an electric field, which is generated between the first and second electrodes. The shield electrode is electrically connected to the first electrode and overlapped with the sealant in plan view.

Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.

Abstract: A display substrate includes a substrate having a first region and a second region, a conductive pattern is provided in the first region of the substrate and includes a first conductive pattern and a second conductive pattern, the first conductive pattern has a gate electrode and a source electrode, the second conductive pattern has a source electrode and a drain electrode, an insulation layer pattern is positioned on the conductive pattern and exposes an outer sidewall of the conductive pattern, an organic layer is provided in the first region and the second region of the substrate and covers the insulation layer pattern, and a pixel electrode is provided on the organic layer and is electrically connected to the drain electrode through a contact hole in the organic layer.

Abstract: A supporting device includes a main body and a ring-shaped glue layer. The main body includes a top surface and a bottom surface opposite to the top surface. The top surface defines a first groove. The first groove is substantially ring-shaped. The glue layer is arranged in the top surface and surrounds the first groove. A plurality of glass-frits is distributed in the glue layer.

Abstract: An array substrate and the method for making the same, and a display device are provided. The method includes step 1, forming a pattern comprising a gate electrode and a gate line on a substrate, and providing photoresist at a position reserved for a first via hole above the gate line in a non-display area; step 2, forming a pattern of functional layers of a thin film transistor (TFT) and a data line on the substrate after the above step; step 3, forming a pattern comprising a first pixel electrode on the substrate after the above steps, and then forming a passivation layer; step 4, removing the photoresist provided above the position reserved for the first via hole and film layer thereabove from the substrate after the above steps, so as to form the first via hole.

Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, an electrically insulating layer formed on the substrate and covering the gate electrode, a channel layer made of semiconductor material and formed on the electrically insulating layer, an etch stop pattern formed on the channel layer and defining a first through hole and a second through hole; and a source electrode and a drain electrode formed on the etch stop pattern. The source electrode extends into the first through hole to electrically couple to the channel layer. The drain electrode extends into the second through hole to electrically couple to the channel layer. Both the channel layer and the etch stop pattern are formed by using a single mask and a single photoresist layer.

Abstract: The present disclosure relates to a photo sensor module. The thickness and size of an IC chip may be reduced by manufacturing a photo sensor based on a semiconductor substrate and improving the structure to place a UV sensor on the upper section of an active device or a passive device. The photo sensor module includes a semiconductor substrate, a field oxide layer, formed on the semiconductor substrate, and a photo sensor comprising a photo diode formed on the field oxide layer.

Abstract: Light-sensing apparatuses may include a light sensor transistor and a switching transistor in a light-sensing pixel, the transistors being oxide semiconductor transistors. In the light-sensing apparatus, the light sensor transistor and the switching transistor in the light-sensing pixel may be adjacently formed on one substrate, the switching transistor including a channel material that is relatively less light-sensitive than the light sensor transistor and is stable, and the light sensor transistor includes a channel material that is relatively light-sensitive. The light sensor transistor may include a transparent upper electrode on a surface of a channel, and a negative voltage may be applied to the transparent upper electrode, whereby a threshold voltage shift in a negative voltage direction may be prevented or reduced.

Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.

Abstract: An imaging device capable of obtaining high-quality imaging data is provided. The imaging device includes a first circuit and a second circuit. The first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a third capacitor. The second circuit includes an eighth transistor. Variation in threshold voltage of an amplifier transistor (the fifth transistor) included in the first circuit can be compensated.

Abstract: An imaging device capable of obtaining high-quality imaging data is provided. The imaging device includes a first circuit, a second circuit and a third circuit. The first circuit includes a photoelectric conversion element, a plurality of transistors including an amplifier transistor, and a plurality of capacitors. The second circuit includes a transistor. The third circuit includes a resistor and a transistor for controlling a current flowing in the resistor. The output signal of the imaging device is determined in accordance with the current flowing in the resistor. Variations in electrical characteristics of the amplifier transistor included in the first circuit can be compensated.

Abstract: A solid-state imaging device includes a plurality of photoelectric conversion portions each provided in a semiconductor substrate and receives incident light through a light sensing surface, and a pixel separation portion provided to electrically separate a plurality of pixels. At least a pinning layer and a light shielding layer are provided in an inner portion of a trench provided on a side portion of each of the photoelectric conversion portions in an incident surface side, the trench includes a first trench and a second trench formed to be wider than the first trench in a portion shallower than the first trench, the pinning layer is formed in an inner portion of the first trench to cover an inside surface of the second trench, and the light shielding layer is formed to bury an inner portion of the second trench at least via the pinning layer.

Abstract: An imager module for a camera includes: a lens holder; a lens system which is accommodated in the lens holder and has a lens mount and at least one lens accommodated in the lens mount; and an image sensor; a rear lens area being formed between the image sensor and the at least one lens of the lens system; and an optically transparent, flexible coupling element provided in the rear lens area.

Abstract: A back-illuminated type solid-state image pickup unit in which a pad wiring line is provided on a light reception surface and which is capable of improving light reception characteristics in a photoelectric conversion section by having a thinner insulating film in a pixel region. The solid-state image pickup unit includes a sensor substrate having a pixel region in which photoelectric conversion sections are formed in an array, and a drive circuit is provided on a surface opposed to a light reception surface for the photoelectric conversion sections of the sensor substrate. A through hole via reaching the drive circuit from the light reception surface of the sensor substrate is provided in a peripheral region located outside the pixel region. A pad wiring line directly laminated on the through hole via is provided on the light reception surface in the peripheral region.

Abstract: BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.

Abstract: An image sensor can include a photoelectric conversion part of an active region of a substrate and a trench in the substrate. A transfer transistor gate electrode can extend from outside the trench into the trench and terminate in the trench to provide an exposed portion of the trench in the photoelectric conversion part.

Abstract: The integrated imaging device comprises a substrate (1) with an integrated circuit (4), a cover (2), a cavity (6) enclosed between the substrate (1) and the cover (2), and a sensor (5) or an array of sensors (5) arranged in the cavity (6). A surface (11, 12) of the substrate (1) or the cover (2) opposite the cavity (6) has a structure (8) directing incident radiation. The surface structure (8) may be a plate zone or a Fresnel lens focusing infrared radiation and may be etched into the surface of the substrate or cover, respectively.

Abstract: A solid-state imaging device includes a plurality of photoelectric conversion portions each provided in a semiconductor substrate and receives incident light through a light sensing surface, and a pixel separation portion provided to electrically separate a plurality of pixels. At least a pinning layer and a light shielding layer are provided in an inner portion of a trench provided on a side portion of each of the photoelectric conversion portions in an incident surface side, the trench includes a first trench and a second trench formed to be wider than the first trench in a portion shallower than the first trench, the pinning layer is formed in an inner portion of the first trench to cover an inside surface of the second trench, and the light shielding layer is formed to bury an inner portion of the second trench at least via the pinning layer.

Abstract: A solid-state image pickup device includes a semiconductor substrate in which photoelectric conversion units are arranged. An insulator is disposed on the semiconductor substrate. The insulator has holes associated with the respective photoelectric conversion units. Members are arranged in the respective holes. A light-shielding member is disposed on the opposite side of one of the members from the semiconductor substrate, such that only the associated photoelectric conversion unit is shielded from light. In the solid-state image pickup device, the holes are simultaneously formed and the members are simultaneously formed.

Abstract: One embodiment according to the present disclosure is an imaging apparatus including pixels. The pixel includes a junction type field effect transistor (JFET) provided in a semiconductor substrate. The JFET includes a gate region and a channel region. An orthogonal projection of the gate region onto a plane parallel to a surface of the semiconductor substrate intersects an orthogonal projection of the channel region onto the plane. Each of a source-side portion of the orthogonal projection of the channel region and a drain-side portion of the orthogonal projection of the channel region protrudes out of the orthogonal projection of the gate region.

Abstract: There is provided a semiconductor device including a semiconductor layer that includes an active region, semiconductor elements that are formed using the active region, connection regions that are obtained by metalizing parts of the semiconductor layer in an island shape isolated from the active region, an insulation film that is formed to cover one main surface side of the semiconductor layer, electrodes that are disposed to face the semiconductor elements and the connection regions via the insulation film, and contacts that penetrate through the insulation film to be selectively formed in portions according to necessity among portions that connect the semiconductor elements or the connection regions to the electrodes.

Abstract: A solid-state imaging device includes a layout in which one sharing unit includes an array of photodiodes of 2 pixels by 4×n pixels (where, n is a positive integer), respectively, in horizontal and vertical directions.

Abstract: An LED module is disclosed containing an integrated driver transistor (e.g, a MOSFET) in series with an LED. In one embodiment, LED layers are grown over a substrate. The transistor regions are formed over the same substrate. After the LED layers, such as GaN layers, are grown to form the LED portion, a central area of the LED is etched away to expose a semiconductor surface in which the transistor regions are formed. A conductor connects the transistor in series with the LED. Another node of the transistor is electrically coupled to an electrode on the bottom surface of the substrate. In one embodiment, an anode of the LED is connected to one terminal of the module, one current carrying node of the transistor is connected to a second terminal of the module, and the control terminal of the transistor is connected to a third terminal of the module.

Abstract: A problem in that a light emitting element slightly emits light is solved by an off current of a thin film transistor connected in series to the light emitting element, thereby a display device which can perform a clear display by increasing contrast, and a driving method thereof are provided. When the thin film transistor connected in series to the light emitting element is turned off, a charge held in the capacitance of the light emitting element itself is discharged. Even when an off current is generated at the thin film transistor connected in series to the light emitting element, this off current charges this capacitance until the capacitance of the light emitting element itself holds a predetermined voltage again. Accordingly, the off current of the thin film transistor does not contribute to light emission. In this manner, a slight light emission of the light emitting element can be reduced.

Abstract: The present disclosure relates to an integrated chip comprising an RRAM cell that is driven by a PMOS transistor, and an associated method of formation. In some embodiments, the integrated chip has a PMOS transistor arranged within a semiconductor substrate. A resistive RRAM cell is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. The RRAM cell has a first conductive electrode separated from a second conductive electrode by a dielectric data storage layer having a variable resistance. The first conductive electrode is connected to a drain terminal of the PMOS transistor by one or more metal interconnect layers. The use of a PMOS transistor to drive the RRAM cell allows for impact of the body effect to be reduced and therefore allows for a reset operation to be performed at a low power and in a short amount of time.

Abstract: The disclosed technology relates generally to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. In one aspect, a memory device of the memory array comprises a substrate and a memory cell stack formed between and electrically connected to first and second conductive lines. The memory cell stack comprises a first memory element over the substrate and a second memory element formed over the first element, wherein one of the first and second memory elements comprises a storage element and the other of the first and second memory elements comprises a selector element. The memory cell stack additionally comprises a first pair of sidewalls opposing each other and a second pair of sidewalls opposing each other and intersecting the first pair of sidewalls.

Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.

Abstract: The present disclosure relates to an imaging element, an electronic device, and an information processing device capable of more easily providing a wider variety of photoelectric conversion outputs. An imaging element of the present disclosure includes: a photoelectric conversion element layer containing a photoelectric conversion element that photoelectrically converts incident light; a wiring layer formed in the photoelectric conversion element layer on the side opposite to a light entering plane of the incident light, and containing a wire for reading charges from the photoelectric conversion element; and a support substrate laminated on the photoelectric conversion element layer and the wiring layer, and containing another photoelectric conversion element. The present disclosure is applicable to an imaging element, an electronic device, and an information processing device.

Abstract: An organic light-emitting diode (OLED) display capable of controlling light transmittance is disclosed. In one aspect, the OLED display includes a plurality of pixels, each including a first region configured to emit light and a second region configured to transmit light therethrough and a plurality of first electrodes respectively formed in the first regions of the pixels. The OLED display also includes a plurality of organic layers respectively formed over the first electrodes, a second electrode formed over all of the organic layers, and a plurality of third electrodes each formed in the second regions of the pixels. The OLED display further includes a plurality of solvents respectively placed over the third electrodes, wherein each of the solvents is configured to selectively block light and a fourth electrode formed over the solvents for all of the pixels.

Abstract: A manufacturing method of an organic electroluminescence display device including a device substrate provided with a plurality of pixel electrodes which have a gap part therebetween, a common electrode disposed opposite to the plurality of pixel electrodes, a light emitting layer provided over the plurality of pixel electrodes, and a bank layer provided in the gap part of the plurality of pixel electrodes, the method comprising forming a cover layer including a concave region to fit into a convex shaped part of the bank layer at a support substrate, forming a color filter layer facing the pixel electrode to the concave region, disposing a surface of the color filter layer on the device substrate so that the concave region fits into a convex shaped part, and attaching the cover layer and the color filter layer on the device substrate by peeling the cover layer from the support substrate.

Abstract: A method for producing a display device includes forming a resin film on a substrate, forming a plurality of light emitting elements above the resin film, forming a plurality of first grooves in a surface of the resin film, the plurality of first grooves enclosing the plurality of light emitting elements individually in a multiple-fold manner, cutting the substrate at a position overlapping any one of the plurality of first grooves other than the first groove closest to one of the plurality of light emitting elements, and peeling off the substrate from the resin layer.

Abstract: The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced.