Abstract: Embodiments include methods of forming a semiconductor device having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within area of the substrate contained by the isolation structure, and a diode circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a source region of the first conductivity type, and the diode circuit is connected between the isolation structure and the source region. The diode circuit may include one or more Schottky diodes and/or PN junction diodes. In further embodiments, the diode circuit may include one or more resistive networks in series and/or parallel with the Schottky and/or PN diode(s).

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a bipolar junction transistor (BJT) is formed on the substrate, a metal-oxide semiconductor (MOS) transistor is formed on the substrate and electrically connected to the BJT, a resistor is formed on the substrate and electrically connected to the MOS transistor, a dielectric layer is formed on the substrate to cover the BJT, the MOS transistor, and the resistor, and an oxide-semiconductor field-effect transistor (OS-FET) is formed on the dielectric layer and electrically connected to the MOS transistor and the resistor.

Abstract: A semiconductor device is formed, the semiconductor device including: an SOI substrate; field insulating films that are formed on the SOI substrate and that separate a plurality of element formation regions; first and second HV pMOSs, and first and second LV pMOSs that are formed in the plurality of element formation regions; a first interlayer insulating film and a second interlayer insulating film formed on the SOI substrate; a mold resin formed on the second interlayer insulating film; and conductive films that are formed on the first interlayer insulating film and that are interposed between the plurality of element formation regions, and the field insulating films and mold resin.

Abstract: In one embodiment, a common drain semiconductor device includes a substrate, having two transistors integrated therein. The substrate also includes a plurality of active regions on a major surface of the substrate. The active regions of each transistor may be interleaved.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a plurality of fin shaped structures, a first trench and at least one bump. The substrate has a base. The fin shaped structures protrude from the base of the substrate. The first trench recesses from the base of the substrate and has a depth being smaller than a width of each of the fin shaped structures. The at least one bump is disposed on a surface of the first trench.

Abstract: A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer.

Abstract: Methods are disclosed for forming fins in transistors. In one embodiment, a method of fabricating a device includes forming silicon fins on a substrate and forming a dielectric layer on the substrate and adjacent to the silicon fins such that an upper region of each silicon fin is exposed. Germanium may then be epitaxially grown germanium on the upper regions of the silicon fins to form germanium fins.

Abstract: A semiconductor device includes a diffusion area, a gate structure coupled to the diffusion area, and a dummy gate structure coupled to the diffusion area. The gate structure extends a first distance beyond the diffusion area, and the dummy gate structure extends a second distance beyond the diffusion area.

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.

Abstract: A semiconductor is provided that includes an nFET gate structure straddling over a first nanowire stack and a portion of a first SiGe layer having a first Ge content. The first nanowire stack comprises alternating layers of a tensily strained silicon layer, and a second SiGe layer having a second Ge content that is greater than the first Ge content and being compressively strained. Portions of the tensily strained silicon layers extend beyond sidewalls surfaces of the nFET gate structure and are suspended. The structure further includes a pFET gate structure straddling over a second nanowire stack and another portion of the first SiGe layer. The second nanowire stack comprises alternating layers of the tensily strained silicon layer, and the second SiGe layer. Portions of the second SiGe layers extend beyond sidewalls surfaces of the pFET gate structure and are suspended.

Abstract: To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell.

Abstract: Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.

Abstract: Capacitor strap connections for a memory cell and device structures for making such capacitor strap connections. A deep trench capacitor is formed in a substrate. A collar comprised of an electrical insulator is formed at least partially inside an upper section of a deep trench in which the deep trench capacitor is formed. A portion of the collar is removed to define a notch extending through the collar, and a connection strap is formed in the notch. A fin is formed from a portion of the substrate, and is coupled by the connection strap with an electrode of the deep trench capacitor that is located inside the deep trench.

Abstract: Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed.

Abstract: A method for forming a semiconductor having a plurality of FinFETs. The method includes providing a semiconductor substrate having a surface; and forming a plurality of first fins and a plurality of second fins on the surface of the semiconductor substrate. Further, the method also includes forming a mask layer on top surfaces of the plurality of first fins and the plurality of second fins; and forming an insulation material layer covering side surfaces of the first fins, the second fins and the mask layer. Further, the method includes removing a portion of the mask layer on the first fins; and forming a continuous first gate structure covering side and top surfaces of a plurality of first fins and a discontinuous second gate structure covering only the side surfaces of the second fins and the side surfaces of the mask layer.

Abstract: A semiconductor device includes a memory transistor (10A) which is capable of being irreversibly changed from a semiconductor state where drain current Ids depends on gate voltage Vg to a resistor state where drain current Ids does not depend on gate voltage Vg. The memory transistor (10A) includes a gate electrode (3), a metal oxide layer (7), a gate insulating film (5), and source and drain electrodes. The drain electrode (9d) has a multilayer structure which includes a first drain metal layer (9d1) and a second drain metal layer (9d2), the first drain metal layer (9d1) being made of a first metal whose melting point is not less than 1200° C., the second drain metal layer (9d2) being made of a second metal whose melting point is lower than that of the first metal. Part P of the drain electrode 9d extends over both the metal oxide layer (7) and the gate electrode (3) when viewed in a direction normal to a surface of the substrate.

Abstract: A wide trench having a width W1 and narrow trenches having a width W2 that is less than W1 are formed in a dielectric layer, the wide trench extending deeper in outer regions than in a central region. A trench modification step changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench.

Abstract: A semiconductor storage device includes an insulating layer. A ferroelectric capacitor is on the insulating layer and includes a lower electrode, a ferroelectric film, and an upper electrode. An interlayer insulating film is formed on the insulating layer, and has an opening where the ferroelectric capacitor is disposed. A first metal plug is formed in the insulating layer and connected to the lower electrode via the opening. A second metal plug is embedded in the insulating layer outside the ferroelectric capacitor. A hydrogen barrier film covers the ferroelectric capacitor and the interlayer insulating film. An upper surface of the interlayer insulating film is higher than an upper surface of the first metal plug so that a step is therebetween. The lower electrode is formed on the upper surface of the interlayer insulating film, the upper surface of the first metal plug and the step.

Abstract: A method of forming a semiconductor memory storage device that includes forming first and second doped regions of a first type in a semiconductor substrate and laterally spaced from one another, forming a gate dielectric extends over the semiconductor substrate between the first and second doped regions, forming a floating gate on the gate dielectric, and forming an ultraviolet (UV) light blocking material vertically disposed above the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light.

Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a first stacked body provided on the substrate, the first stacked body including a plurality of electrode layers and a plurality of insulating layers, each of the plurality of insulating layers being provided between the plurality of electrode layers; a semiconductor film provided in the first stacked body and extending in a stacking direction of the first stacked body; and a second stacked body provided on the substrate and separately from the first stacked body, the second stacked body including a same layer structure as the first stacked body. The second stacked body includes a first contact portion electrically connected to an external portion; and a second contact portion electrically connected to an external portion different from the first contact portion.

Abstract: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.

Abstract: An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.

Abstract: The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500° C. or more in temperature is carried out, it can be easily and clearly separated in the layer or on the interface with the oxide layer 12 by the physical means.

Abstract: To provide a semiconductor device with excellent charge retention characteristics, an OS transistor is used as a transistor whose gate is connected to a node for retaining charge. Charge is stored in a first capacitor, and data at the node for retaining charge is read based on whether the stored charge is transferred to a second capacitor. Since a Si transistor, in which leakage current through a gate insulating film occurs, is not used as a transistor connected to the node for retaining charge, charge retention characteristics of the node are improved. In addition, the semiconductor device operates in data reading without requiring transistor performance equivalent to that of a Si transistor.

Abstract: A touch panel whose power consumption can be reduced is provided, and an increase in the manufacturing cost of the touch panel is prevented. A photosensor which includes a light-receiving element including a non-single-crystal semiconductor layer between a pair of electrodes and a transistor including an oxide semiconductor layer in a channel formation region is provided. A touch panel which includes a plurality of pixels and the photosensor adjacent to at least one of the plurality of pixels is provided. Each of the plurality of pixels includes a pair of terminals. One of the pair of terminals is a reflective conductive film. Alternatively, each of the pair of terminals is a light-transmitting conductive film.

Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

Abstract: Each pixel region of an active matrix substrate includes a thin-film transistor, an interlayer insulating layer that includes an organic insulating layer, a transparent connection layer formed on the interlayer insulating layer, an inorganic insulating layer formed on the transparent connection layer, and a pixel electrode formed on the inorganic insulating layer. The transparent connection layer contacts a drain electrode inside of a first contact hole formed in the interlayer insulating layer. The pixel electrode contacts the transparent connection layer inside of a second contact hole formed in the inorganic insulating layer. The first contact hole and the second contact hole do not overlap with one another when a substrate is viewed from a normal direction. Inside the first contact hole, a bottom surface and sidewalls of the first contact hole are covered by the transparent connection layer, the inorganic insulating layer, and the pixel electrode.

Abstract: A disclosed display device includes a first oxide semiconductor layer and an oxide semiconductor connection wire both formed from an oxide semiconductor material layer over a substrate. The oxide semiconductor connection wire is integrally connected to the first oxide semiconductor layer and has a lower sheet resistance than the first oxide semiconductor layer. The display device also includes a first gate electrode either over the first oxide semiconductor layer or between the first oxide semiconductor layer and the substrate. The display device further includes a first gate insulation layer between the first oxide semiconductor layer and the first gate electrode.

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

Abstract: The present invention discloses a thin-film transistor and a fabricating method thereof, an array substrate and a display apparatus. An active layer in the thin-film transistor comprises a first active layer and a second active layer which are stacked; wherein, an orthographic projection of the first active layer on the substrate covers orthographic projections of the source electrode, the drain electrode as well as a gap located between the source electrode and the drain electrode on the substrate, and covers an orthographic projection of the gate electrode on the substrate; the second active layer is located at the gap between the source electrode and the drain electrode, and an orthographic projection of the second active layer on the substrate is located in a region where the orthographic projection of the gate electrode on the substrate is located.

Abstract: A display panel is disclosed, comprising: a first substrate; a thin film transistor layer disposed on the first substrate; an insulating layer disposed on the thin film transistor layer; at least one pixel electrode disposed on the insulating layer and exposing an exposure region of the insulating layer; and an alignment layer disposed on the pixel electrode and the exposure region; wherein a surface roughness of the alignment layer disposed on the exposure region is larger than a surface roughness of the alignment layer disposed on the pixel electrode.

Abstract: The present disclosure provides an array substrate, a liquid crystal panel, and a manufacturing method of the array substrate. In the present disclosure, the first discharging elements and the second discharging elements are arranged on the array substrate, the first discharging elements are electrically connected to the common electrode line, and the second discharging elements are respectively electrically connected to the data lines, and the first discharging elements and the second discharging elements are simultaneously formed with the scanning lines and the data lines or are formed after the scanning lines and the data lines are formed, thus, electrostatic protection is provided to the components in the subsequent manufacturing process of the array substrate after the scanning line and the data lines are formed on the array substrate.

Abstract: A display device includes a first substrate, a second substrate disposed opposite to the first substrate, and a gate drive circuit having at least one first capacitor and a gate drive element. The first capacitor is located on the first substrate, and the gate drive element is disposed on the second substrate. The display device can reduce the wiring width of the gate drive circuit, narrow the frame edge and improve the transmissivity of sealant on the gate drive circuit.

Abstract: Exemplary embodiments of the present disclosure provide a thin film transistor array panel including a first insulating substrate; a gate line and a data line disposed on the first insulating substrate, intersecting with each other, and being insulated from each other; a first passivation layer disposed on the gate line and the data line and comprising a plurality of first openings; a first electrode disposed on the first passivation layer; and a second electrode disposed in the first opening, thereby simplifying a manufacturing process of the thin film transistor array panel.

Abstract: A method according to embodiments of the invention includes providing a wafer comprising a semiconductor structure grown on a growth substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. The wafer includes trenches defining individual semiconductor devices. The trenches extend through an entire thickness of the semiconductor structure to reveal the growth substrate. The method further includes forming a thick conductive layer on the semiconductor structure. The thick conductive layer is configured to support the semiconductor structure when the growth substrate is removed. The method further includes removing the growth substrate.

Abstract: The process of fabricating a flexible TFT back-panel includes depositing etch stop material on a glass support. A matrix of contact pads, gate electrodes and gate dielectric are deposited overlying the etch stop material. Vias are formed through the dielectric in communication with each pad. A matrix of TFTs is formed by depositing and patterning metal oxide semiconductor material to form an active layer of each TFT overlying the gate electrode. Source/drain metal is deposited on the active layer and in the vias in contact with the pads, the source/drain metal defining source/drain terminals of each TFT. Passivation material is deposited in overlying relationship to the TFTs. A color filter layer is formed on the passivation material and a flexible plastic carrier is affixed to the color filter. The glass support member and the etch stop material are then etched away to expose a surface of each of the pads.

Abstract: Disclosed are an LCD device and a method of manufacturing the same, which reduce a capacitance deviation between pixels without any change in a viewing angle and a high transmittance. The LCD device includes a plurality of gate lines formed in a first direction on a substrate, a plurality of data lines formed in a second direction to intersect the plurality of gate lines, a thin film transistor (TFT) formed in each of a plurality of pixel areas defined by the plurality of gate lines and the plurality of data lines, a pixel electrode formed in a tetragonal shape in each of the plurality of pixel areas, and a common electrode formed on the pixel electrode, and configured to include a plurality of finger patterns. Each of the plurality of pixel areas is formed in a tetragonal shape.

Abstract: An image sensor pixel for use in a high dynamic range image sensor includes a first photodiode and a second photodiode. The first photodiode include a first doped region, a first lightly doped region, and a first highly doped region disposed between the first doped region and the first lightly doped region. The second photodiode disposed in has a second full well capacity substantially equal to a first full well capacity of the first photodiode. The second photodiode includes a second doped region, a second lightly doped region, and a second highly doped region disposed between the second doped region and the second lightly doped region. A first aperture sizer is disposed above the second photodiode to limit image light received by the second photodiode to a second amount that is less than a first amount of image light received by the first photodiode.

Abstract: An imaging element mounting substrate includes: an insulating base comprising insulating layers, the insulating base surface comprising an opening which is located at a center thereof; a connection electrode disposed at a lower surface of the insulating base around the opening; and light-transmission control layers between the insulating layers, and comprising inner edges located on an outside of the opening. An inner edge of one light-transmission control layer lies closer to the opening than an inner edge of another light-transmission control layer as seen in a transparent plan view, and the insulating base has, in an inner periphery of the opening of an insulating layer constituting a lower surface of the insulating base, an inclined portion which is inclined such that the opening becomes smaller in size from the lower surface as approaching an upper surface of the insulating base.

Abstract: An image sensor is provided including a substrate, an array of photosensitive units, a grid, a light-tight layer and a plurality of color filters. In the image sensor, the grid has a top surface, and the light-tight layer is disposed on the top surface of the grid. Due to the light-tight layer on the grid, an incident light entering into the grid can be blocked by the light-tight layer, so that the crosstalk effect is reduced significantly. Further, a method for manufacturing the image sensor also provides herein.

Abstract: A color filter array, for an image sensing device, includes a plurality of filter patterns. Each filter pattern includes at least one first filter, corresponding to a first wavelength range of a first color; at least one second filter, corresponding to a second wavelength range of a second color; at least one third filter, corresponding to a third wavelength range of a third color; at least one fourth filter, corresponding to a first infrared wavelength range, wherein the first infrared wavelength range is an intersection of the first wavelength range and the second wavelength range; and at least one fifth filter, corresponding to a second infrared wavelength range, wherein the second infrared wavelength range is an intersection of the first wavelength range and the third wavelength range.

Abstract: An image sensor package includes an image sensor with a pixel array disposed in a semiconductor material, and a transparent shield adhered to the semiconductor material. The pixel array is disposed between the semiconductor material and the transparent shield. A light blocking layer is disposed in recessed regions of the transparent shield, and the recessed regions are disposed on an illuminated side of the transparent shield. The light blocking layer is disposed to prevent light from reflecting off edges of the transparent shield into the image sensor.

Abstract: An image sensor such as a complementary metal-oxide-semiconductor (CMOS) image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes: a semiconductor substrate including a first surface and a third surface formed by removing a part of the semiconductor substrate from a second surface opposite to the first surface; a plurality of active regions which are formed between the first surface and the third surface and each of which includes a photoelectric conversion element generating charges in response to light input through the third surface; and an isolation region vertically formed from either of the first and third surfaces to isolate the active regions from one another. When the CMOS image sensor is viewed from the above of the third surface, each of the active regions may have round corners and concave sides.

Abstract: Provided is an imaging apparatus includes: a substrate; a photoelectric conversion unit configured to generate a signal charge by photoelectric conversion; a contact wiring of a conductor electrically connected to the photoelectric conversion unit; a transistor including a control electrode, a first main electrode electrically connected to the contact wiring, and a second main electrode; a charge accumulating unit provided in the substrate and electrically connected to the second main electrode of the transistor; and a first switching unit configured to switch connection and disconnection between the control electrode and the first main electrode of the transistor.

Abstract: Methods of manufacturing an integrated circuit device including a through via structure are provided. The methods may include forming an isolation trench through a substrate to form an inner substrate, which is enclosed by the isolation trench and forming an insulating layer in the isolation trench and on a surface of the substrate. The methods may also include forming a hole, which is spaced apart from the isolation trench and passes through a portion of the insulating layer formed on the surface of the substrate and the inner substrate and forming a conductive layer in the hole and on the insulating layer formed on the surface of the substrate. The methods may be used to manufacture image sensors.

Abstract: A pixel array includes a plurality of visible light pixels arranged in the pixel array. Each one of the plurality of visible light pixels includes a photosensitive element arranged in a first semiconductor die to detect visible light. Each one of the plurality of visible light pixels is coupled to provide color image data to visible light readout circuitry disposed in a second semiconductor die stacked with and coupled to the first semiconductor die in a stacked chip scheme. A plurality of infrared (IR) pixels arranged in the pixel array. Each one of the plurality of IR pixels includes a single photon avalanche photodiode (SPAD) arranged in the first semiconductor die to detect IR light. Each one of the plurality of visible light pixels is coupled to provide IR image data to IR light readout circuitry disposed in the second semiconductor die.

Abstract: Disclosed is an image sensor, which is characterized by increased strength of adhesion between a photoconductive layer and a front electrode made of aluminum, and which includes a first electrode composed of aluminum, copper or an aluminum-copper alloy on a substrate, a buffer layer formed on the first electrode, a photoconductive layer formed on the buffer layer, and a second electrode formed on the photoconductive layer, wherein the buffer layer includes a material having higher strength of adhesion than the photoconductive layer to the first electrode.

Abstract: Embodiments of the present invention are directed to optical packages having a cover made of transparent material with a recess formed therein and methods of forming same. The recess may be formed in a periphery portion of the transparent material and may have various shapes and configurations. Adhesive is provided in at least a portion of the recess of the transparent material, which secures the transparent material to an image sensor.

Abstract: A solid-state imaging apparatus includes an imaging region in which pixels are arranged, a connection region that surrounds the imaging region and includes an electrode pad, and an in-layer lens that is formed in the imaging region for each of the pixels. The in-layer lens is formed of a coating-type high-refractive-index material. The connection region includes an opening that is formed such that an upper surface of the electrode pad is exposed from the high-refractive-index material applied to the electrode pad.