Abstract: A mass spectrometer is disclosed comprising an ion guide. The ion guide comprises a hollow tubular conductor having a wall. One or more electrodes are provided in the wall of the tubular conductor. An exit aperture is provided in the wall of the tubular conductor downstream of the one or more electrodes. An AC or RF voltage is applied to the one or more electrodes and a DC potential difference is maintained between the wall of the tubular conductor and the one or more electrodes. The combination of a DC voltage gradient and applying an AC or RF voltage to the electrodes is that ions are confined radially to a region which is preferably close to the one or more electrodes. Ions are preferably extracted from the ion guide via the exit aperture.

Abstract: The present invention relates to an ion guide device and an ion guiding method. The ion guide device comprises: a plurality of electrode sets distributed along a central axis longitudinally, wherein each electrode set has a ring shape and consists of at least 2 segmented electrodes (for example, 1, 2 and 3, 4 for 2 sets respectively); the power supply system which provides radio-frequency with different phases applied to the adjacent electrode sets (for example, between 1,3 and 2,4) along the central axis, and provides DC Voltages on each segmented electrode (1,2,3,4), wherein, distribution of DC potential drives ions to move in the radial direction while driving said ions to move along the central axis. The ion guide can be used to guide and focus ions under relatively high gas pressure; especially it can be used for off-axis transmission of ions with the purpose to reduce the neutral noise.

Abstract: An integrated mass spectrometer electrospray emitter and fluorescence detector allows improved volumetric measurements of separate components from a liquid chromatography column by improving correlation between the readings of these instruments and reducing dead volume and sample size requirements.

Abstract: An ICR cell (01) operates with a duplexer (08), which is an integral part of a transmission and receiving device (09) of an FT-ICR mass spectrometry device. The device transmits a transmitter (03) voltage to at least one electrode (11) of the ICR cell during an ion excitation phase and protects a preamplifier (04) from overvoltage. An ion received signal passes through a reception path (12) to the preamplifier during an ion detection phase. The duplexer has at least one active serial switch (07) with two switchable states, each with different series impedances, which is inserted in the reception path (12). As a result, a duplexer for an ICR cell of an FT-ICR mass spectrometry device is provided in which at least one electrode can be used for both ion excitation and for subsequent ion detection.

Abstract: A method of reflecting ions in a multireflection time of flight mass spectrometer is disclosed. The method includes guiding ions toward an ion mirror having multiple electrodes, and applying a voltage to the ion mirror electrodes to create an electric field that causes the mean trajectory of the ions to intersect a plane of symmetry of the ion mirror and to exit the ion mirror, wherein the ion are spatially focussed by the mirror to a first location and temporally focused to a second location different from the first location. Apparatus for carrying out the method is also disclosed.

Abstract: Mass spectrometry systems or assemblies therefore include an ionizer that includes at least one planar conductor, a mass analyzer with a planar electrode assembly, and a detector comprising at least one planar conductor. The ionizer, the mass analyzer and the detector are attached together in a compact stack assembly. The stack assembly has a perimeter that bounds an area that is between about 0.01 mm2 to about 25 cm2 and the stack assembly has a thickness that is between about 0.1 mm to about 25 mm.

Abstract: An electrodeless lighting device and methods for manufacturing the same are provided. The method includes inserting a dose into the bulb and at least one of heating a vacuum line for applying a vacuum to the bulb at first predetermined temperature and heating the bulb containing the dose at a second predetermined temperature for a predetermined time.

Abstract: A method of manufacturing a semiconductor device including attaching, by a liquid treatment, a first liquid to a surface of a semiconductor substrate having a fine pattern formed therein; substituting the first liquid attached to the surface of the semiconductor substrate with a solution, the solution comprising a sublimate dissolved in a second liquid; vaporizing the second liquid and precipitating the sublimate to the surface of the semiconductor substrate to form a solid precipitate comprising the sublimate; and removing the precipitate by sublimation. For example, the sublimate may be a material having at least two carboxyl groups bonded to cyclohexane or a material formed of two carboxyl groups bonded to benzene with the bonding sites of the two carboxyl groups being adjacent to one another.

Abstract: A method for manufacturing a semiconductor substrate. An impurity diffusion ingredient can be diffused well and uniformly from a coating film into a semiconductor substrate by forming a coating film having a thickness of not more than 30 nm on a surface of a semiconductor substrate with a diffusion agent composition containing an impurity diffusion ingredient and a silicon compound that can be hydrolyzed to produce a silanol group.

Abstract: A wafer processing method includes a wafer holding step of holding a wafer having devices formed on the front side, a protective film forming step of forming a water-soluble protective film on the front side of the wafer, a laser beam applying step of applying a laser beam to the wafer along streets, a cleaning step of cleaning the wafer to then remove the protective film, and a foreign matter removing step of removing foreign matter from the wafer when a predetermined period of time has elapsed after cleaning. This period of time is set as a period of time until a phosphorus containing reaction product produced at a laser processed portion is evaporated to react with water in the air, thereby producing the foreign matter containing phosphorus on bumps formed on each device.

Abstract: Methods and apparatuses for filling an epitaxial layer into a trench/via/structure formed in a substrate with good deposition profile control and film uniformity across the substrate are provided. In one embodiment, a method of depositing a epitaxial layer on the substrate includes supplying a gas mixture having a first ratio of a dichlorosilane gas to a chlorine containing gas into the processing chamber, altering the gas mixture to have a second ratio of the dichlorosilane gas to the chlorine containing gas into the processing chamber, maintaining a substrate temperature of between about 600 degrees Celsius and about 1000 degrees Celsius, and filling an opening formed in a substrate.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate having an oxide film; performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate, supplying a carbon-containing gas to the substrate, and supplying a nitrogen-containing gas to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas to the substrate and supplying a gas containing carbon and nitrogen to the substrate, or performing, a predetermined number of times, a cycle of non-simultaneously performing supplying a precursor gas containing carbon to the substrate and supplying a nitrogen-containing gas to the substrate, the oxide film being used as an oxygen source to form a nitride layer containing oxygen and carbon as a seed layer; and forming a nitride film containing no oxygen and carbon as a first film on the seed layer.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. There is prepared a first silicon carbide layer having a first main surface and a second main surface. A first recess including a side portion and a bottom portion is formed in the first main surface of the first silicon carbide layer. A second silicon carbide layer is formed in contact with the first main surface, the side portion, and the bottom portion. An image of a second recess formed at a position facing the first recess of the fourth main surface is obtained. Alignment is performed based on the image of the second recess. The first main surface corresponds to a plane angled off relative to a {0001} plane. A ratio obtained by dividing a depth of the first recess by a thickness of the second silicon carbide layer is more than 0.2.

Abstract: The Siemens process for deposition of polycrystalline silicon in the form of rods in a sealed reactor is improved by, after introduction of deposition gas has ceased, introducing a ventilating gas into the partially sealed reactor, withdrawing a gas stream from the reactor, and monitoring the components in the gas stream withdrawn until a desired concentration of one or more components is reached, and opening the reactor to remove the rods.

Abstract: A method comprises providing a cavity structure on the substrate comprising a first growth channel extending in a first direction, a second growth channel extending in a second direction, wherein the second direction is different from the first direction and the second channel is connected to the first channel at a channel junction, a first seed surface in the first channel, at least one opening for supplying precursor materials to the cavity structure, selectively growing from the first seed surface a first semiconductor structure substantially only in the first direction and in the first channel, thereby forming a second seed surface for a second semiconductor structure at the channel junction, growing in the second channel the second semiconductor structure in the second direction from the second seed surface, thereby forming the semiconductor junction comprising the first and the second semiconductor structure.

Abstract: An apparatus for crystallizing an active layer of a thin film transistor, the apparatus includes a first laser irradiating a first beam toward a substrate, an amorphous layer on the substrate being crystallizable into the active layer of the thin film transistor by the first beam, and a second laser irradiating a second beam toward the substrate to heat the active layer, the second beam having an asymmetric intensity profile in a scanning direction of the first and second beams.

Abstract: The present disclosure relates to a structure and method of forming a GaN film on a Si substrate that includes an additional or second high temperature (HT) AlN seed layer, introduced for reducing the tensile stress of GaN on a Si substrate. The second HT AlN seed layer is disposed over a first HT AlN seed layer, and has a low V/III ratio compared to the first HT AlN seed layer. The second HT AlN seed layer has better lattice matching between Si and GaN and this reduces the tensile stress on GaN. The additional HT AlN seed layer further acts as a capping layer and helps annihilate or terminate threading dislocations (TDs) originating from a LT AlN seed layer. The second HT AlN seed layer also helps prevent Si diffusion from the substrate to the GaN film.

Abstract: In lithography, a composition comprising a novolak resin comprising recurring units of hydroxycoumarin is used to form a photoresist underlayer film. The underlayer film is strippable in alkaline water, without causing damage to ion-implanted Si substrates or SiO2 substrates.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a molding layer and a supporter layer on a semiconductor substrate, forming a multiple mask layer including a first mask layer and a second mask layer formed on the first mask layer, on the supporter layer. The first mask layer is formed of a material having an etch selectivity with respect to the molding layer and the second mask layer is formed of a material having an etch selectivity with respect to the supporter layer. The method includes forming a first mask pattern and a second mask pattern formed on the first mask pattern by patterning the multiple mask layer, etching the supporter layer by performing a first etching process using the second mask pattern as an etch mask, etching the molding layer, and forming a hole by performing a second etching process using the first mask pattern as an etch mask.

Abstract: Sub-50-nm structures are formed using sequential top-down and bottom up lithographies in conjunction with selective etching. The preferred rendition of the method involves: (a) rough lithographic patterning, (b) size/shape selected nanostructure deposition, (c) resist reflow around the nanostructures, and (d) selective removal/etching of the nanostructure.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched. The mask layer contains at least one type of a metal, boron, and carbon. The metal is selected from a group including tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium and iridium. A composition ratio of the metal is higher than a composition ratio of the boron and a composition ratio of the carbon. The method includes making a hole or a slit in the layer to be etched by performing a dry etching to the layer to be etched using the mask layer being patterned.

Abstract: A diffusion agent composition including an impurity-diffusing component (A); a binder resin (B) that thermally decomposes and disappears below a temperature at which the impurity-diffusing component (A) begins to thermally diffuse; SiO2 fine particles (C); and an organic solvent (D) that contains an organic solvent (D1) having a boiling point of at least 100° C.

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first gate layer and a first dielectric layer thereon is provided. A shallow trench isolation (STI) is formed in the substrate and surrounds the first gate layer and the first dielectric layer. The first dielectric layer is removed. A first spacer is formed on the sidewall of the STI above the first gate layer. Using the first spacer as mask, part of the first gate layer and part of the substrate are removed for forming a first opening while defining a first gate structure and a second gate structure.

Abstract: A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed.

Abstract: A method of forming a Ti film on a substrate disposed in a chamber by introducing a processing gas containing a TiCl4 gas as a Ti source and a H2 gas as a reducing gas and by generating plasma in the chamber, includes introducing an Ar gas as a plasma generation gas into the chamber, converting the Ar gas into plasma to generate Ar ions, and acting the Ar ions on the Ti film to promote desorption of Cl from the Ti film.

Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

Abstract: A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device.

Abstract: Methods for fabricating semiconductor or micromachined devices with metal structures and methods for forming self-aligned deep cavity metal structures are provided. A method for fabricating a device with a metal structure includes patterning a mask with an opening perimeter bounding an opening over a substrate. The method includes performing an isotropic etch to etch a shallow portion of the substrate exposed by the opening and a shallow portion of the substrate underlying the opening perimeter of the mask. The method also includes performing an anisotropic etch to etch a deep portion of the substrate exposed by the mask opening and a deep portion of the substrate underlying the opening perimeter of the mask to form a cavity having a bottom surface. Further, the method includes depositing metal over the mask, into the mask opening and onto the bottom surface, wherein the metal on the bottom surface forms the metal structure.

Abstract: A surface machining method for a single crystal SiC substrate, including: a step of mounting a grinding plate which includes a soft pad and a hard pad sequentially attached onto a base metal having a flat surface, a step of generating an oxidation product by using the grinding plate, and a step of grinding the surface while removing the oxidation product, wherein abrasive grains made of at least one metallic oxide that is softer than single crystal SiC and has a bandgap are fixed to the surface of the hard pad.

Abstract: A production methods includes providing a substrate including a lattice plane that extends in a non-symmetrical manner and such that it is offset at an angle ? from at least a first or second main surface region of the substrate, the first and second main surface regions extending parallel to each other; anisotropic etching, starting from the first main surface region, into the substrate so as to obtain an etching structure which includes, in a plane extending perpendicularly to the first main surface region, two different etching angles relative to the first main surface region; arranging a cover layer on the first main surface region, so that the cover layer lies against the etching structure in at least some sections; and removing, section-by-section, the material of the substrate starting from the second main surface region in the area of the deformed cover layer, so that the cover layer is exposed in at least one window region.

Abstract: Methods of and apparatuses for laterally etching semiconductor substrates using an atomic layer etch process involving exposing an oxidized surface of a semiconductor substrate to a fluorine-containing etch gas and heating the substrate to remove non-volatile etch byproducts by a sublimation mechanism are provided herein. Methods also including additionally pulsing a hydrogen-containing gas when pulsing the fluorine-containing etch gas. Apparatuses also include an ammonia mixing manifold suitable for separately preparing and mixing ammonia for use in various tools.

Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation.

Abstract: A composition comprises: a compound having one partial structure represented by formula (1), and a solvent. n1 and n2 are each independently an integer of 0 to 2; and k1 and k2 are each independently an integer of 0 to 9. The compound preferably has an intermolecular bond-forming group. The compound is preferably represented by formula (2). Z represents the partial structure represented by the formula (1); Ar1 and Ar2 represent a substituted or unsubstituted arenediyl group having 6 to 20 carbon atoms; Ar3 and Ar4 represent a substituted or unsubstituted aryl group having 6 to 20 carbon atoms; and p1 and p2 are each independently an integer of 0 to 3.

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a laser energy absorbing, non-photodefinable topcoat disposed over a water-soluble base layer disposed over the semiconductor substrate. Because the laser light absorbing material layer is non-photodefinable, material costs associated with conventional photo resist formulations may be avoided. The mask is direct-write patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. Absorption of the mask layer within the laser emission band (e.g., UV band and/or green band) promotes good scribe line quality. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the mask protecting the ICs during the plasma etch. The soluble base layer of the mask may then be dissolved subsequent to singulation, facilitating removal of the layer.

Abstract: A method for fabricating an integrated circuit includes providing an semiconductor wafer includes forming in an upper mandrel layer a first upper mandrel having a first critical dimension and a second upper mandrel having a second critical dimension; forming upper sidewall spacers along sidewalls of the first upper mandrel while leaving the second upper mandrel without sidewall spacers; removing the first upper mandrel from between the upper sidewall spacers; transferring a pattern of the upper sidewall spacers and of the second upper mandrel into a lower mandrel layer to form first lower mandrels according to the pattern of the upper sidewall spacers and a second lower mandrel according to the pattern of the second upper mandrel; and forming lower sidewall spacers along sidewalls of the first and second lower mandrels.

Abstract: Methods of facilitating fabrication of circuit structures are provided which include, for instance: providing a structure with a film layer; modifying an etch property of the film layer by implanting at least one species of element or molecule into the upper portion of the film layer, the etch property of the film layer remaining unmodified beneath the upper portion; and subjecting the structure and film layer with the modified etch property to an etching process, the modified etch property of the film layer facilitating the etching process. Modifying the etch property of the upper portion of the film layer may include making the upper portion of the film layer preferentially susceptible or preferentially resistant to the etching process depending on the circuit fabrication approach being facilitated.

Abstract: Plasma-based atomic layer etching of materials may be of benefit to various semiconductor manufacturing and related technologies. For example, plasma-based atomic layer etching of materials may be beneficial for adding and/or removing angstrom thick layers from a surface in advanced semiconductor manufacturing and related technologies that increasingly demand atomistic surface engineering. A method may include depositing a controlled amount of a chemical precursor on an unmodified surface layer of a substrate to create a chemical precursor layer and a modified surface layer. The method may also include selectively removing a portion of the chemical precursor layer, a portion of the modified surface layer and a controlled portion of the substrate. Further, the controlled portion may be removed to a depth ranging from about 1/10 of an angstrom to about 1 nm. Additionally, the deposition and selective removal may be performed under a plasma environment.

Abstract: Techniques disclosed herein include methods and systems for clearing out films or materials that may be covering alignment marks on substrates such as semiconductor wafers. Such films include photoresist layers, polymer films, thin films, and other layers that may be opaque or semi-opaque to optical alignment systems. A solvent composition is printed directly on resist films or other patterning films at specified points or regions on a substrate. The solvent composition printed or deposited on a resist film then begins to dissolve portions of the resist film that are directly underneath the solvent composition. The solvent composition and dissolved film material is then removed or washed from the substrate without causing other portions of the resist film to be dissolved, thereby uncovering alignment patterns or marks.

Abstract: A method of manufacturing a semiconductor structure, by depositing a dielectric layer is a dummy gate, or an existing gate structure, prior to the formation of gate spacers. Following the formation of spacers, and in some embodiments replacing a dummy gate with a final gate structure, oxygen is introduced to a gate dielectric through a diffusion process, using the deposited dielectric layer as a diffusion pathway.

Abstract: A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer filling at least the recesses. The structure is planarized by: a) chemical-mechanical polishing of the copper, such a polishing being selective with respect to the barrier layer so that copper remains in the recesses and is set back with respect to the upper surface of the substrate; b) depositing on the exposed surface of the structure a material covering at least the copper at the level of the recesses; and c) chemical-mechanical planarizing of the structure to expose the substrate with the copper remaining buried under the material. Two such structures are then direct bonded to each other with opposite areas of material having a same topology.

Abstract: A method of fabricating a gate structure includes depositing a high dielectric constant (high-k) dielectric layer over a substrate. The method further includes performing a multi-stage preheat high-temperature anneal. Performing the multi-stage preheat high-temperature anneal includes performing a first stage preheat at a temperature in a range from about 400° C. to about 600° C., performing a second stage preheat at a temperature in a range from about 700° C. to about 900° C., and performing a high temperature anneal at a peak temperature in a range from 875° C. to about 1200° C.

Abstract: A method of making an integrated circuit package. A leadframe having a die attach paddle surrounded by lead portions is formed. Middle channels underlying in said die attach paddle portion in a region thereof adapted to receive a first die are formed.

Abstract: A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer.

Abstract: The invention relates to an electronic component including a leadframe, composed of a platform, and possibly at least one electrical connecting piece, wherein at least one electronic member is located on the platform, and including a housing that encloses the electronic member and the platform, wherein at least one support region is provided to support the platform during the fabrication process for the housing, and wherein at least a section of the at least one support region projects from the housing.

Abstract: An apparatus for drying a substrate may include a spin chuck, a drying chamber and a drying fluid line. The spin chuck may be configured to support the substrate. The spin chuck may rotate the substrate. The drying chamber may be configured to receive the spin chuck. The drying chamber may have an inlet, an outlet and a vortex exhaust. A drying fluid may be supplied through the inlet into the drying chamber. The drying fluid may be drained through the outlet. A vortex of the drying fluid may be drained through the vortex exhaust. The drying fluid line may be connected to the inlet.

Abstract: A substrate treatment apparatus includes: a nozzle having an opposing surface to be opposed to and spaced from a front surface of a substrate rotated by a substrate rotating unit, the nozzle further having an outlet port provided in the opposing surface to be opposed to a rotation center of the substrate; a second liquid supply control unit which controls the second liquid supplying unit to fill a space defined between the front surface and the opposing surface with the second liquid in a liquid filled state, and then stop supplying the second liquid to form a liquid puddle in the space; and a first liquid supply control unit which controls a first liquid supplying unit to spout a first liquid from the outlet port after the formation of the liquid puddle.

Abstract: In one embodiment, a cleaning member has an annular part and an opening positioned radially inside the annular part, and can be moved up and down between a first position and a second position relative to a cleaning nozzle. For cleaning of the back surface of the wafer, the cleaning member is placed at its first position that allows a cleaning liquid to reach the back surface of the substrate through the opening of the cleaning member. For cleaning of the cup structure, the cleaning member placed at its second position higher than the first position is being rotated, and a cleaning liquid discharged from the cleaning nozzle collides with an annular part of the cleaning member and is guided to the inner surface of a cup structure.

Abstract: Provided is a substrate processing apparatus. The substrate processing apparatus in which processes with respect to substrates are performed includes a lower chamber having an opened upper side, the lower chamber including a passage allowing the substrates to pass therethrough in a side thereof, an external reaction tube closing the opened upper side of the lower chamber to provide a process space in which the processes are performed, a substrate holder on which the one ore more substrates are vertically stacked, the substrate holder being movable between a stacking position in which the substrates are stacked within the substrate holder and a process position in which the processes with respect to the substrates are performed, and a gas supply unit disposed inside the external reaction tube to supply a reaction gas into the process space, the gas supply unit forming a flow of the reaction gas having different phase differences in a vertical direction.

Abstract: Disclosed is a process of annealing through silicon vias (TSVs) or other deeply buried metallic interconnects using a back side laser annealing process. The process provides several advantages including sufficient grain growth and strain relief of the metal such that subsequent thermal processes do not cause further grain growth; shorter anneal times thereby reducing cycle time of 3D device fabrication; and reduced pattern sensitivity of laser absorption.