Abstract: A method for determining an optimal voltage pulse for programming a flash memory cell, the optimal voltage pulse being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, wherein the method takes into account a set of parameters including a programming window target value and a drain current target value of the memory cell.

Abstract: A semiconductor memory device may include: a memory cell array comprising a plurality of memory cells coupled to a plurality of bit line pairs and a plurality of word lines; and an operation circuit suitable for setting a parameter corresponding to an input command, and performing an operation corresponding to the input command on the memory cell array based on the set parameter, wherein, when the input command is of the same type as a previous input command, the operation circuit skips setting the parameter for each of preset word line groups.

Abstract: According to example embodiments, a nonvolatile memory device includes a lower filling insulating layer covering a peripheral logic structure on a substrate, a horizontal semiconductor layer on the lower filling insulating layer, and a three-dimensional memory cell array including a plurality of memory blocks on the horizontal semiconductor layer. The horizontal semiconductor layer includes a plurality of doped regions spaced apart from each other in a first direction and a plurality of well regions between the doped regions. Each of the memory blocks includes sub-blocks on corresponding ones of the well regions. The non-volatile memory device is configured to perform an erase operation in units of the sub-blocks. The non-volatile memory device is configured to independently apply an erase voltage to a selected one of the well regions during the erase operation.

Abstract: A semiconductor memory device includes a memory cell array that is capable of storing data in a nonvolatile manner, and a control section that controls data access to the memory cell array. The memory cell array stores the same data redundantly in a plurality of pages. The control section executes a reading operation on the plurality of pages that store the same data redundantly to read the data. The data that is stored redundantly may be management data or user data.

Abstract: A semiconductor device includes a memory array including memory blocks; and an operation circuit suitable for performing a program loop and an erase loop on memory cells and selection transistors included in a selected memory block, wherein the program loop is performed by controlling a target threshold voltage value of the selection transistors based on a difference between a cell current value of the selected memory block and a reference cell current value.

Abstract: There are provided a storage device, a memory system having the same, and an operating method thereof. A storage device includes a plurality of memory blocks for storing data, a peripheral circuit for selecting multiple memory blocks from among the plurality of memory blocks and simultaneously performing an erase operation on the multiple memory blocks, and a control circuit for controlling the peripheral circuit so that the multiple memory blocks are simultaneously erased, and an erase operation and an erase verification operation of a selected memory block from among the multiple memory bocks are performed.

Abstract: A semiconductor memory device has a memory block including memory strings with first and second selection transistors at opposite ends of the memory strings. A bit line is connected to the first selection transistor of each memory string and a sense amplifier is connected to the bit line. The memory block includes word lines connected to each memory cell transistor in the memory strings. The memory device also includes a controller to control an erase operation that includes applying an erase voltage to the word lines, addressing a first memory string by applying a selection voltage to a gate electrode of first and second selection transistors of the first memory string, then applying an erase verify voltage to the word lines and using the sense amplifier to read data of memory cell transistors in the first memory string, then addressing a second memory string without first discharging the word lines.

Abstract: Upon initialization or startup of an electronic device, the device checks a predetermined section of non-volatile memory, referred to as the signature byte or lock byte, and allows either the manufacturing mode which allows for installation of the final or production version of firmware to be loaded into non-volatile memory, or the production mode which write-protects certain portions of non-volatile memory before giving operating control of the electronic device to another program, for example, an operating system. By only allowing execution of operating system or other executable code after write-protecting certain portions of non-volatile memory, system security, integrity, and robustness are substantially increased.

Abstract: Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities.

Abstract: A nonvolatile memory device may include a nonvolatile memory cell and a sensing circuit. The sensing circuit is coupled to a bit line of the nonvolatile memory cell. The sensing circuit may be realized using an inverter comprised of a P-channel transistor coupled to a supply voltage line and an N-channel transistor coupled to a ground voltage. The gate of the P-channel transistor is coupled to the ground voltage.

Abstract: A storage device includes a nonvolatile memory device including memory blocks and a controller configured to control the nonvolatile memory device. Each of the memory blocks includes a plurality of cell strings each including at least one selection transistor and a plurality of memory cells stacked on a substrate in a direction perpendicular to the substrate. The controller controls the nonvolatile memory device to perform a read operation on some of selection transistors of a selected one of the memory blocks and to perform a program operation on the selection transistors of the selected memory block according to a result of the read operation.

Abstract: A refresh method for a flash memory includes at least the following steps: performing a write operation to store an input data into a storage space in the flash memory; checking reliability of the storage space with the input data already stored therein; and when the reliability of the storage space meets a predetermined criterion, performing a refresh operation upon the storage space based on the input data. For example, the write operation stores the input data into the storage space through an initial program operation and at least one reprogram operation following the initial program operation; and the refresh operation is an additional reprogram operation applied to the storage space for programming the input data recovered from the storage space into original storage locations in the storage space.

Abstract: A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a plurality of string selection lines (SSLs), the memory cells associated with the plurality of SSLs constituting a memory block, and verifying the erasing operation to second memory cells associated with a second SSL after verifying the erasing operation to first memory cells associated with a first SSL.

Abstract: According to one embodiment, a memory device includes a string unit including a plurality of memory cell transistors which are connected in series, a first select transistor connected to a first end of the plurality of memory cell transistors, and a second select transistor connected to a second end of the plurality of memory cell transistors; and a bit line connected to the first select transistor.

Abstract: A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. The read sensing method includes following steps. Firstly, the plural bit lines are precharged to a precharge voltage. Then, a selected memory cell of the memory array is determined, wherein the selected memory cell is connected with a first bit line of the plural bit lines. Then, the bit line corresponding to the selected memory cell is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to a result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.

Abstract: The present invention provides a shift register, a gate driving circuit and a display device. The shift register comprises a precharge and reset module, a pull-up module, a pull-down module and a cut-off module, the cut-off module, the pull-up module and the pull-down module are connected at a first node, and the cut-off module is connected between the first node and the precharge and reset module. In the present invention, the cut-off module is provided to disconnect electric connection between the precharge and reset module and the pull-up module, such that the first node cannot discharge through the precharge and reset module, which effectively avoids internal discharge of the shift register, and further ensures normal output of the signal output from the output terminal of the shift register, and improves stability of the shift register.

Abstract: Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.

Abstract: A memory device includes a memory cell array and a control unit. The memory cell array includes a plurality of memory cells arranged in rows and columns, a plurality of word lines extending in a row direction and coupled to respective rows of the memory cells, and a plurality of local bit lines extending in a column direction and coupled to respective columns of the memory cells. The control unit is configured to program a selected one of the rows of memory cells to have a predetermined pattern of digital states, couple selected ones of the local bit lines to a global bit line and couple unselected ones of the local bit lines to ground based on the predetermined pattern, apply a stress voltage to the global bit line, and after a predetermined period of time, sense the digital states of the selected row of memory cells.

Abstract: A semiconductor device may include a memory core including a data cell region and a parity cell region, a parity calculation logic configured for generating a parity from data received by the parity calculation logic, and an error correcting logic configured for outputting error-corrected data by using data that is output from the data cell region and a parity that is output from the parity cell region.

Abstract: A device includes a storage region, and a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array is disclosed herein. The storage region includes a first storage array and a second storage array. The first storage array includes a plurality of first storage cells. The second storage array includes a plurality of second storage cells. The second storage cells are configured to be in place of the first storage cells. The RRAM-based non-volatile storage array is configured to record at least one corresponding relationship between the first storage cells and the second storage cells.

Abstract: A method for repairing of the invention includes steps as follows: storing redundant information including an address of the bad column, identification information for identifying a failure in which one of an even column or an odd column of the bad column and an address of a redundant column of a redundant memory region for repairing the bad column; determining whether a column address of a selected column is consistent with the address of the bad column based on the redundant information; when consistent, converting a column of the bad column having the failure into a column of the redundant column based on the identification information; and not converting another column of the bad column without the failure into another column of the redundant column.

Abstract: A memory system may include a memory module comprising a plurality of memory chips mounted therein each memory chip comprising a plurality of banks, the memory chips being simultaneously accessible based on the same command and address; and a memory controller suitable for mapping the banks of the memory chips to each other while rearranging an order of the banks of each of the memory chips based on repair information of the memory chips.

Abstract: A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.

Abstract: Systems, apparatus and methods are provided through which an injector system automates a process of injecting an individual dose from a multiple dose of a radiotracer material. In some embodiments, the injector system includes a first dose calibrator system that receives a multidose vial of a radiotracer, a second dose calibrator system, an injection pump and an intravenous needle. In some embodiments, the first dose calibrator system and the multidose vial have an integrated shape. In some embodiments, the first dose calibrator system includes a pneumatic arm that receives the multidose vial.

Abstract: An apparatus includes an x-ray source operable to generate x-ray beams, a collimator comprising one or more leaves configured to modify the x-ray beams, a motorized system operable to move the one or more leaves of the collimator independently in or out of the x-ray beams, and a controller configured to synchronize operation of the x-ray source and the motorized system, allowing modification of the x-ray beams substantially in real time with generation of the x-ray beams. At least one leaf or each of the leaves of the collimator may be configured to modulate a beam quality of the x-ray beams.

Abstract: A crosslinkable halogen-free resin composition includes a polymer blend, and a metal hydroxide mixed in an amount of 120 to 200 parts by mass per 100 parts by mass of the polymer blend. The polymer blend includes a maleic anhydride-modified high-density polyethylene, 30 to 50 parts by mass of an ethylene-acrylic ester-maleic anhydride terpolymer, 5 to 20 parts by mass of a maleic anhydride modified ethylene-?-olefin copolymer and 10 to 30 parts by mass of an ethylene-acrylic ester copolymer.

Abstract: A high-power low-resistance electromechanical cable constructed of a conductor core comprising a plurality of conductors surrounded by an outer insulating jacket and with each conductor having a plurality of wires that are surrounded by an insulating jacket. The wires can be copper or other conductive wires. The insulating jacket surrounding each set of wires or each conductor can be comprised of ethylene tetrafluoroethylene, polytetrafluoroethylene, polytetrafluoroethylene tape, perfluoroalkoxyalkane, fluorinated ethylene propylene or a combination of materials. A first layer of a plurality of strength members is wrapped around the outer insulating jacket. A second layer of a plurality of strength members may be wrapped around the first layer of a plurality of strength members. The first and/or second layer of strength members can be made of single wires, synthetic fiber strands multi-wire strands, or rope.

Abstract: A cover assembly for covering an elongate substrate includes a holdout device and a resilient, elastically radially expanded sleeve member. The holdout device includes a core having an axially extending slit defined therein and defining a core passage to receive the substrate, and a designated target region. The sleeve member defines an axially extending sleeve passage. The sleeve member is mounted on the core such that the core is disposed in the sleeve passage and the sleeve member exerts a radially compressive recovery force on the core. When the substrate is disposed in the core passage and a radially directed release force is applied to the target region, the core will reduce in circumference and collapse around the substrate under the recovery force of the sleeve member to a collapsed position.

Abstract: An outer cover includes a flexible tube portion having flexibility and an inflexible tube portion. The flexible tube portion has a corrugated tubular shape in which concave portions and convex portions both extending in a circumferential direction are alternately formed side by side in an axial direction and in which intervals of the adjacent concave portions or intervals between the adjacent convex portions are partially changed.

Abstract: A wire harness includes a terminated covered electric wire. The terminated covered electric wire includes a terminal fitting, an electric wire conductor, and an electrical connection portion in which the terminal fitting and the electric wire conductor are electrically connected to each other. The terminal fitting has a surface to which processing oil adheres, and the electrical connection portion is covered with an anticorrosive agent containing an adhesive resin and an oil-adsorbing organic macromolecule to configure a terminated covered electric wire.

Abstract: A harness exterior protection member with an electric wire bundle inserted therein includes a bent portion and a straight portion which are formed in a cylindrical shape in an integrated manner formed of a flame-retardant polyamide resin composition. A thickness of the straight portion is set to be twice to four times of a thickness of the bent portion. A bending radius of the bent portion is 10 mm or larger, and a bending strength of the straight portion is 15 to 25 N.

Abstract: The invention relates to a coaxial cable for electrical transmission of a high-frequency and/or high-speed data signal, in particular for medical-engineering applications, comprising a arranged radially inside and a plurality of shields which surround the core radially outside, the core exhibiting a litz with a plurality of individual wires. The invention further relates to a rotary coupling with two coaxial cables of such a type, and also to a holding device, in particular a ceiling support, with such a rotary coupling.

Abstract: A shielded cable includes adjacent first and second conductor sets. Each conductor set includes two or more insulated conductors. The first conductor set also includes a ground conductor that generally lies in the plane of the insulated conductors of the first conductor set. At least 90% of the periphery of each conductor set is encompassed by a shielding film. First and second non-conductive polymeric films are disposed on opposite sides of the cable and form cover portions substantially surrounding each conductor set, and pinched portions on each side of the cable. When the cable is laid flat, the distance between the center of the ground conductor of the first conductor set and the center of the nearest insulated conductor of the second conductor set is ?1, the center-to-center spacing of the insulated conductors of the second conductor set is ?2, and ?1/?2 is greater than 0.7.

Abstract: A method for operating a superconducting device (1; 1a, 1b), having a coated conductor (2) with a substrate (3) and a quenchable superconducting film (4), wherein the coated conductor (2) has a width W and a length L, is characterized in that 0.5?L/W?10, in particular 0.5?L/W?8, and that the coated conductor (2) has an engineering resistivity ?eng shunting the superconducting film (4) in a quenched state, with ?eng>2.5 ?, wherein RIntShunt=?eng*L/W, with RIntShunt: internal shunt resistance of the coated conductor (2). The risk of a burnout of a superconducting device in case of a quench in its superconducting film is thereby further reduced to such an extent that the device can be operated without use of an additional external shunt.

Abstract: The present invention provides a method for manufacturing a metal material. The method comprises a temperature increasing step of increasing the temperature of a silver material having undergone final plastic working to 700° C. or more and less than a melting point of the silver material in a vacuum or a helium gas atmosphere, a heating step of maintaining the silver material at 700° C. or more and less than the melting point, and a cooling step of cooling the silver material to room temperature in a vacuum or a helium gas atmosphere. For a part of the period of the heating step, the silver material is heated in a mixed atmosphere in which hydrogen gas is mixed with helium gas.

Abstract: A feed-through element for harsh environments is provided that includes a support body with at least one access opening, in which at least one functional element is arranged in an electrically insulating fixing material. The electrically insulating fixing material contains a glass or a glass ceramic with a volume resistivity of greater than 1.0×1010 ? cm at the temperature of 350° C. The glass or a glass ceramic has a defined composition range in the system SiO2—B2O3-MO.

Abstract: [Problem] There is demand for chip resistors that are compact and that have high resistivity. [Solution] A chip resistor (100) has a substrate (11), a first connection electrode (12) and a second connection electrode (13) that are formed on the substrate (11), and a resistor network that is formed on the substrate (11) and that has ends one of which is connected to the first connection electrode (12) and the other one of which is connected to the second connection electrode (13). The resistor network is provided with a resistive circuit. The resistive circuit has a resistive element film line (103) that is provided along inner wall surfaces of trenches (101). The resistive element film line (103) extending along the inner wall surfaces of the trenches (101) is long and has a high resistivity as a unit resistive element. [Effect] The resistivity of the chip resistor (100) as a whole can be increased.

Abstract: A magnetic member includes a plurality of superparamagnetic particles held by the magnetic member. Each of the plurality of superparamagnetic particles is formed with a particle size which is set at least such that a Neel relaxation time ?n in the each of the superparamagnetic particles becomes shorter than a cycle P of an alternating current magnetic field applied to the magnetic member (?n<P) when the magnetic member is used as an electronic component.

Abstract: A sintered ferrite magnet comprises a main phase of an M type Sr ferrite having a hexagonal crystal structure. An amount of Zn is 0.05 to 1.35 mass % in terms of ZnO and M1/M2 is 0.43 or less when an amount of a rare-earth element (R) is M1 in terms of mol and the amount of Zn is M2 in terms of mol.

Abstract: The present invention provides a permanent magnet with a coercivity that will not be significantly decreased and a light weight compared to conventional R-T-B based permanent magnets. A core-shell structure is formed for the major phase grain by adding Cu to the R-T-B based magnet which is the raw material. When the mass concentration of Y in the core portion is set as EY, the mass concentration of Y in the shell portion is set as LY and the mass concentration of Y in the R2—Fe14—B crystal grain calculated from the ratio R1:Y in the total composition is set as SY, the ratio ? of EY to SY (EY/SY) is 1.1 or more. Thus, the magnetic insulation among the crystal grains becomes better which prevents the coercivity from decreasing due to the addition of Y. Further, the addition of Y makes the magnet lighter in weight.

Abstract: Described embodiments include a system, method, and apparatus. The apparatus includes a magnetic substrate at least partially covered by a first negative-permittivity layer comprising a first plasmonic outer surface. The apparatus includes a plasmonic nanoparticle having a magnetic element at least partially covered by a second negative-permittivity layer comprising a second plasmonic outer surface. The apparatus includes a dielectric-filled gap between the first plasmonic outer surface and the second outer surface. The first plasmonic outer surface, the dielectric-filled gap, and the second plasmonic outer surface are configured to support one or more mutually coupled plasmonic excitations.

Abstract: Described embodiments include a system, method, and apparatus. The apparatus includes a plasmonic nanoparticle dimer. The dimer includes a first plasmonic nanoparticle having a first magnetic element covered by a first negative-permittivity layer comprising a first plasmonic outer surface. The dimer includes a second plasmonic nanoparticle having a second magnetic element covered by a second negative-permittivity layer comprising a second plasmonic outer surface. The dimer includes a separation control structure configured to establish a dielectric-filled gap between the first plasmonic outer surface and the second plasmonic outer surface. A magnetic attraction between the first magnetic element and the second magnetic element binds the first plasmonic nanoparticle and the second plasmonic nanoparticle together, separated by the dielectric-filled gap established by the separation control structure.

Abstract: A method for producing a higher-strength, non-grain-oriented electrical strip, according to which a slab is cast from a molten mass, the slab is hot-rolled and then cold-rolled—optionally a hot-strip annealing can be carried out between the hot-rolling and the cold-rolling—and the cold strip is annealed in order to produce a partially recrystallized structure so that the mechanical strength values ReH can be set within the range of 450 MPa to 850 MPa at an annealing temperature of between 600° C. and 800° C. for 60 s to 300 s.

Abstract: Forming a ferrite thin film laminate includes heating a layered assembly to form a laminate. The layered assembly includes a first coated substrate having a first ferrite layer opposite a first thermoplastic surface and a second coated substrate having a second ferrite layer opposite a second thermoplastic surface to form a laminate. Each coated substrate is formed by forming a ferrite layer on a surface of a thermoplastic substrate. The coated substrates are arranged such that the first ferrite layer contacts the second thermoplastic surface. Heating the layered assembly includes bonding the first coated substrate to the second coated substrate such that the first ferrite layer is sandwiched between a first thermoplastic substrate and a second thermoplastic substrate. The ferrite thin film laminate may include a multiplicity of coated substrates.

Abstract: A gapped core leg for a shunt reactor, comprising magnetic core elements separated by spacers cast directly between the core elements. Accordingly, a rigid core leg construction is achieved.

Abstract: A superconducting magnet and method for making a superconducting magnet, are presented. The superconducting magnet is made by forming a coil from windings of a first wire comprising a reacted MgB2 monofilament, filling a cavity of a stainless steel billet with a Mg+B powder. Monofilament ends of the first wire and a similar second wire are sheared at an acute angle and inserted into the billet. A copper plug configured to partially fill the billet cavity is inserted into the billet cavity. A portion of the billet adjacent to the plug and the wires is sealed with a ceramic paste.

Abstract: Apparatuses and systems for enabling electrical communication with a device positionable within a body cavity of a patient. Apparatuses and systems for magnetically positioning a device within a body cavity of a patient. Medical devices. Methods of use.

Abstract: An electromagnetic solenoid is disclosed. The solenoid includes a coil, a bobbin, a flux sleeve, an armature, and a pole piece, arranged in such a way that the solenoid is robust against misalignment of the pole piece with the flux sleeve. The configuration facilitates the integration of either the pole piece or the flux sleeve into a hydraulic circuit.

Abstract: A solenoid actuator includes a housing, a bobbin assembly, a coil, and a washer. The bobbin assembly is disposed at least partially within the housing, and includes a return pole and an armature. The return pole is fixedly coupled to the housing, and the armature is axially movable within the housing. The coil is disposed within the housing and is wound around at least a portion of the bobbin assembly. The washer is disposed between the coil and a portion of the bobbin assembly and surrounds a portion of the return pole. The washer is formed of an electrical insulator material.

Abstract: A solenoid includes: a coil wound around a bobbin; a case section accommodating the coil; a tubular yoke arranged on an inner circumferential portion of the coil; and a plunger arranged on an inner circumferential portion of the yoke, and moving from a start position along an axial direction of the yoke by magnetic attraction force generated in the yoke, wherein a diameter increasing portion whose diameter is increased from the start position toward a lower part in the axial direction is formed on an outer circumferential surface of the yoke, and the diameter increasing portion overlaps at least a part of a moving region of a lower-part side end portion of the plunger, and wherein an inner circumferential surface of the yoke guides the movement of the plunger and the yoke includes a contact member that regulates the movement of the plunger on the inner circumferential surface.