Abstract: The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.

Abstract: A method for manufacturing a chip package structure having a coating layer is provided. At least one chip package structure is mounted onto a terminal-protection film. The chip package structure has a top side, a back side opposite to the top side and a plurality of lateral sides. A plurality of terminals is disposed on the back side. The terminal-protection film at least partially seals the back side. A coating layer is formed over the top side, the lateral sides and a periphery region of the chip package structure, wherein the coating layer is not formed on the back side and the terminals. The terminal-protection film is debonded from the chip package structure.

Abstract: A semiconductor device has a substrate including an opening. A trench is formed over the substrate around the opening. An interconnect structure is formed in the trench. An underfill material is disposed over the interconnect structure. A first semiconductor die is disposed over the underfill material prior to curing the underfill material. An active region of the first semiconductor die is disposed over the opening in the substrate. The trench contains the outward flow of underfill material. Underfill material is blocked from flowing over unintended areas on the surface of substrate, into the opening in the substrate, and over sensors of the first semiconductor die. A second semiconductor die is disposed over the substrate. The trench is formed by a first and second dam or a first insulating layer. A second insulating layer is formed over the first insulating layer. A dam is formed over the second insulating layer.

Abstract: Shielded electronic packages may have metallic lead frames to connect an electromagnetic shield to ground. In one embodiment, a metallic lead frame of the electronic package and a surface of the metallic lead frame defines a component area for attaching an electronic component. The metallic lead frame includes a metallic structure associated with the component area that may have a grounding element for connecting to ground and one or more signal connection elements, such as signal leads, for transmitting input and output signals. The electromagnetic shield connects to the metallic lead frame to safely connect to ground while maintaining the signal connection elements isolated from the shield.

Abstract: Methods for bonding substrates, forming assemblies using the same, along with improved methods for refurbishing said assemblies are disclosed that take advantage of at least one channel formed in an adhesive utilized to join two substrates to improve fabrication, performance and refurbishment of the assemblies. In one embodiment an assembly includes a first substrate secured to a second substrate by an adhesive layer. The assembly includes a channel having at least one side bounded by the adhesive layer and having an outlet exposed to an exterior of the assembly.

Abstract: There is provided a substrate processing method including: supplying a developing liquid to a surface of an exposed substrate to form a resist pattern; supplying a cleaning liquid to the surface of the substrate to remove a residue generated in the developing step from the substrate; supplying a replacing liquid to the surface of the substrate to replace the cleaning liquid existing on the substrate with the replacing liquid, the replacing liquid having a surface tension of 50 mN/m or less and containing a percolation inhibitor for restraining the replacing liquid from percolating into a resist wall portion constituting the resist pattern; and forming a dry region by supplying a gas to a central portion of the substrate while rotating the substrate so as to dry the surface of the substrate by expanding the dry region to a peripheral edge portion of the substrate with a centrifugal force.

Abstract: Provided is a substrate treating apparatus including a housing; a plurality of opening-and-closing members configured to provide a driving force for opening and closing the housing; a fluid storing member supplying a fluid to the opening-and-closing members; and a fluid distribution unit connected to the fluid storing member via a supply conduit to distribute the fluid supplied from the fluid storing member to the opening-and-closing members. The fluid distribution unit includes a distribution conduit diverging from the supply conduit and connected to a corresponding one of the opening-and-closing members; and a fluid distribution member provided at a junction between the supply conduit and the distribution conduit.

Abstract: A method and a system that include providing a localized dispensing apparatus. A substrate having a material disposed on its top surface is oriented above the localized dispensing apparatus. A chemical is then dispensed from the localized dispensing apparatus onto the top surface of the oriented substrate. The chemical removes the material. The path for the material removal may be determined and the localized dispensing apparatus programmed to provide chemical according to the path.

Abstract: A supporting member separation method for separating a laminate which is formed by laminating a substrate and a support plate through an adhesive layer and in which a release layer is provided on at least a part of the peripheral portion on the surface of the side of the substrate facing the support plate or the peripheral portion on the surface of the side of the support plate facing the substrate, the method including reducing the adhesive force of at least a part of the release layer which is provided on the peripheral portion of the substrate or the support, and fixing a part in the substrate and the support plate and separating the support plate from the substrate by applying a force to another part, after the preliminary treatment.

Abstract: A substrate treating apparatus is provided which includes housing and a door assembly. The housing provides a process space for treating a substrate therein and has an opening formed at a sidewall thereof. The door assembly opens and closes the opening. The door assembly includes a shutter, a driving member, and a gap maintaining unit. The driving member transfers the shutter to an open position where the shutter faces to the opening and to a blocking position where the shutter gets out of the open position. The gap maintaining unit maintains a constant gap between the shutter and the sidewall.

Abstract: A substrate accommodating and processing apparatus is provided with a cassette mounting table, a processing part, a substrate transfer mechanism, a partition wall, a cassette stage, and a lid attaching/detaching mechanism. The lid attaching/detaching mechanism is provided with a key configured to be engaged with a key hole installed in the lid, and configured to switch a latch between locking and unlocking positions. The mechanism is also provided with a lid abnormality detecting sensor, a lid attaching/detaching mechanism closing sensor, a lid attaching/detaching mechanism opening sensor, a pressure sensor and a control part.

Abstract: A substrate transfer apparatus unloads a substrate from a transfer container in which a cover body airtightly closes a substrate unloading opening formed at a front surface of a container main body and multiple substrates are accommodated in the form of shelves. The substrate transfer apparatus includes a load port to which the transfer container is loaded; a detection unit configured to detect an accommodation status of the substrate in the container main body that is loaded to the load port and separated from the cover body; a substrate transfer device configured to enter the container main body and unload the substrate; and a correction device configured to correct the accommodation status of the substrate in the container main body before the substrate is unloaded from the container main body by the substrate transfer device when the detection unit detects abnormality in the accommodation status.

Abstract: The surface topography of at least one wafer can be determined in-situ based on deflectometer measurements of surface tilt. The deflectometer is re-positioned by a scanning positioner to facilitate tilt mapping of the wafer surface for each of the at least one wafer. A surface height mapping engine is configured to generate a three-dimensional topographic mapping of the surface of each of the at least one wafer based on the mapping of the tilt.

Abstract: According to an aspect of the invention, there is provided an electrostatic chuck including: a ceramic dielectric substrate having a first major surface, a second major surface, and a through-hole; a metallic base plate which has a gas introduction path that communicates with the through-hole; and a bonding layer which is provided between the ceramic dielectric substrate and the base plate and includes a resin material, the bonding layer having a space which is provided between an opening of the through-hole in the second major surface and the gas introduction path and is larger than the opening in a horizontal direction, and a first area in which an end face of the bonding layer on a side of the space intersects with the second major surface being recessed from the opening further than another second area of the end face which is different from the first area.

Abstract: A resin sheet attaching method of attaching a resin sheet to a workpiece. The resin sheet attaching method includes a molecular weight reducing step of applying vacuum ultraviolet radiation to the front side of the resin sheet, thereby cutting an intermolecular bond in a surface region having a depth of tens of nanometers from the front side of the resin sheet to thereby reduce the molecular weight of the surface region and produce an adhesive force, and a resin sheet attaching step of attaching the front side of the resin sheet to the workpiece after performing the molecular weight reducing step.

Abstract: In a wafer processing method, a protective film is formed by applying a liquid resin to the front side of a wafer. A protective tape is adhered to a surface of the protective film. A modified layer is formed by applying a laser beam having such a wavelength as to be transmitted through the wafer along each of division lines, with a focal point positioned inside the wafer. The modified layer is formed inside the wafer along each of the division lines. The back side of the wafer is ground while supplying grinding water to thin the wafer to a predetermined thickness and to crack the wafer along the division lines using the modified layers as crack starting points so as to divide the wafer into individual device chips, after the protective film is formed, the protective tape is adhered, and the modified layer is formed.

Abstract: Provided is an apparatus and a method of holding a device. The apparatus includes a wafer chuck having first and second holes that extend therethrough, and a pressure control structure that can independently and selectively vary a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure. The method includes providing a wafer chuck having first and second holes that extend therethrough, and independently and selectively varying a fluid pressure in each of the first and second holes between pressures above and below an ambient pressure.

Abstract: Apparatuses and methods for supporting a workpiece such as a semiconductor wafer. A support system is configured to support the workpiece while allowing thermally-induced motion of the workpiece, which may include thermal bowing or thermal bending. The system may include a support member having a moveable engagement portion engageable with the workpiece, the engagement portion being moveable to allow the thermally-induced motion of the workpiece while supporting the workpiece. The moveable engagement portion may include a plurality of moveable engagement portions of a plurality of respective support members, which may be resiliently engageable with the workpiece. The support members may include flexible support members each having an unconstrained portion and a constrained portion, and the moveable engagement portions may include the unconstrained portions.

Abstract: One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure.

Abstract: A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.

Abstract: Provided is a method of fabricating a semiconductor device, including the following. A first material layer, a second material layer and a mask layer are formed on a substrate. A portion of the second material layer is removed by performing a first etching process with the mask layer as a mask, so as to expose the first material layer and form a first pattern layer and a second pattern layer. A portion of the first material layer is removed by performing a second etching process with the mask layer as a mask, so as to expose a portion of the substrate. A portion of the substrate is removed by performing a third etching process with the mask layer as a mask, so as to form first trenches and second trenches. Sidewalls of the second trenches and a surface of the substrate form at least two different angles.

Abstract: An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.

Abstract: A method for manufacturing a semiconductor structure includes at least following steps. A device layer is formed on a first semiconductor substrate. The device layer is separated from the first semiconductor substrate. A dielectric layer is formed on a second semiconductor substrate. The device layer is bonded onto the dielectric layer.

Abstract: A via opening comprising an etch stop layer (ESL) opening and methods of forming the same are provided which can be used in the back end of line (BEOL) process of IC fabrication. A metal feature is provided with a first part within a dielectric layer and with a top surface. An ESL is formed with a bottom surface of the ESL above and in contact with the dielectric layer, and a top surface of the ESL above the bottom surface of the ESL. An opening at the ESL is formed exposing the top surface of the metal feature; wherein the opening at the ESL has a bottom edge of the opening above the bottom surface of the ESL, a first sidewall of the opening at a first side of the metal feature, and a second sidewall of the opening at a second side of the metal feature.

Abstract: Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.

Abstract: A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts.

Abstract: A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure.

Abstract: An exemplary method includes forming a vertical pillar overlying or laterally displaced from a bond pad overlying a semiconductor substrate, and applying a discrete solder sphere in combination with one of a solder paste or flux on a top surface of the pillar, wherein the one of the solder paste or flux is defined by at least one photoresist layer. The method may include applying a solder sphere and/or solder flux in different combinations on top surfaces of different first and second pillars.

Abstract: A method for forming a semiconductor device package substrate including a fiducial mark is provided. The method of forming the package substrate includes forming a dielectric layer over a lower portion of the package substrate. A metal layer is formed over a fiducial region of the package substrate. The metal layer is etched to form a first signal line in the fiducial region. A passivation layer is formed over the first signal line. The passivation layer is etched over the first signal line to form a fiducial mark.

Abstract: A dielectric layer is formed on a substrate and patterned to form an opening. The opening is filled and the dielectric layer is covered with a metal layer. The metal layer is thereafter planarized so that the metal layer is co-planar with the top of the dielectric layer. The metal layer is etched back a predetermined thickness from the top of the dielectric layer to expose the inside sidewalls thereof. A sidewall barrier layer is formed on the sidewalls of the dielectric layer. A copper-containing layer is formed over the metal layer, the dielectric layer, and the sidewall barrier layers. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the sidewall barrier layers at approximately the juncture of the sidewall of the dielectric layer and the copper-containing layer and does not etch into the underlying metal layer.

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

Abstract: A device manufacturing method according to an embodiment includes forming a film on the second surface side of a substrate having a first surface and the second surface, forming a trench in part of the substrate from the first surface side, while leaving the film to remain, and injecting a substance onto the film from the second surface side, to remove the film at the portion on the second surface side of the trench.

Abstract: A workpiece cutting method of cutting a workpiece having a front side on which a plurality of crossing division lines are formed to define a plurality of separate regions where a plurality of devices are each formed is disclosed. The workpiece cutting method includes a workpiece cutting step of cutting the workpiece held on a first chuck table along the division lines by using a cutting blade, a dummy wafer cutting step of cutting a dummy wafer held on a second chuck table by using the cutting blade, a dummy wafer imaging step of imaging a cut groove formed on the dummy wafer in the dummy wafer cutting step, by using an imaging unit to thereby obtain a detected image, and a determining step of determining the condition of the cutting blade from the condition of chippings formed on both sides of the cut groove in the detected image.

Abstract: An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.

Abstract: A method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.

Abstract: A process for etching a bulk integrated circuit substrate to form features on the substrate, such as fins, having substantially vertical walls comprises forming an etch stop layer beneath the surface of the substrate by ion implantation, e.g., carbon, oxygen, or boron ions or combinations thereof, masking the surface with a patterned etching mask that defines the features by openings in the mask to produce a masked substrate and etching the masked substrate to a level of the etch stop layer to form the features. In silicon substrates, ion implantation takes place along a silicon crystalline lattice beneath the surface of the substrate. The etchant comprises a halogen material that etches undoped silicon faster than the implants-rich silicon layer. This produces a circuit where the fins do not taper away from the vertical where they meet the substrate, and corresponding products and articles of manufacture having these features.

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a doped region, in some embodiments. The semiconductor device includes a gate over a channel portion of the fin. The gate including a gate electrode over a gate dielectric between a first sidewall spacer and a second sidewall spacer. The first sidewall spacer includes an initial first sidewall spacer over a first portion of a dielectric material. The second sidewall spacer includes an initial second sidewall spacer over a second portion of the dielectric material.

Abstract: A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second epitaxial layer having a first conductivity type, forming a trench in the first epitaxial layer and the second epitaxial layer, forming a gate electrode in the trench, applying an ion implantation process using first gate electrode as an ion implantation mask to form a drain-drift region, forming a field plate in the trench, forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type and forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.

Abstract: A method of forming an active device on a semiconductor wafer includes the steps of: forming a plurality of semiconductor fins on at least a portion of a semiconductor substrate; forming a dielectric layer on at least a portion of the semiconductor substrate, the dielectric layer filling gaps between adjacent fins; forming a plurality of gate structures on an upper surface of the dielectric layer; forming a channel region on the dielectric layer and under at least a portion of the gate structures, the channel region comprising a first crystalline semiconductor material; forming source and drain epitaxy regions on an upper surface of the dielectric layer and between adjacent gate structures, the source and rain regions being spaced laterally from one another; and replacing the channel region with a second crystalline semiconductor material after high-temperature processing used in fabricating the active device has been completed.

Abstract: A method includes forming a set of fins composed of a first semiconductor material. The method further heats the set of fins to condense the fins and cause growth of a layer of oxide on vertical sidewalls thereof, masking a first sub-set of the fins, forming a plurality of voids in the oxide by removing a second sub-set of fins, where each void has a three-dimensional shape and dimensions that correspond to a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set, and epitaxially growing in the voids a third sub-set of fins. The third sub-set of fins is composed of a second semiconductor material that differs from the first semiconductor material. Each fin of the third subset has a three dimensional shape and dimensions of a corresponding removed fin from the second sub-set. At least one structure formed by the method is also disclosed.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

Abstract: A method for forming transistors is provided. The method includes providing a substrate having a base and at least a fin on the base; and forming a gate layer on the fin, the gate layer has first side surfaces parallel to a longitudinal direction of the fin and second side surfaces perpendicular to the fin. The method also includes forming a protective layer on the first side surfaces of the gate layer to protect a vertex of the top of the gate layer from having EPI particles; and forming sidewall spacers on side surfaces of the protective layer and the second side surfaces of the gate layer. Further, the method includes forming a stress layer in the fin at both sides of the sidewall spacers and the gate layer.

Abstract: A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a first work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type.

Abstract: A method is provided in which a III-V compound semiconductor channel material is grown from at least one exposed sidewall of a semiconductor mandrel that is present in an NFET device region. The III-V compound semiconductor channel material is grown after formation of any PFET devices and after formation of a middle-of-the-line (MOL) dielectric material within the NFET device region.

Abstract: A patterning scheme to minimize dry/wet strip induced device degradation and resultant devices are provided. The method includes removing a workfunction material over a first device area of a structure, while protecting the workfunction material over a second device area of the structure with a first masking material. The method further includes applying a second masking material over the first device area and the first masking material. The method further includes removing the first masking material and the second masking material until the workfunction material is exposed over the second device area.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different.

Abstract: One illustrative method disclosed herein includes, among other things, forming a first sacrificial layer comprising amorphous silicon or polysilicon material around a fin in a lateral space between a plurality of laterally spaced apart gate structures that are positioned around the fin, performing a first selective etching process to remove a first sacrificial layer selectively relative to surrounding material so as to expose the fin in the lateral space, forming an epi material on the exposed portion of the fin, and forming a second layer of a sacrificial material above the epi material. The method also includes selectively removing the second layer of sacrificial material relative to at least the first layer of material to thereby define a source/drain contact opening that exposes the epi material and forming a self-aligned trench conductive source/drain contact structure that is conductively coupled to the epi material.

Abstract: A semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.

Abstract: A method includes forming one or more fin structures on a substrate, the one or more fin structures comprising a first material comprising a first lattice structure and the substrate comprising a second material comprising a second lattice structure. Forming the one or more fin structures on the substrate includes forming one or more trenches in the substrate, and growing the first material in the one or more trenches. The first lattice structure is different from the second lattice structure. The one or more fin structures are self-aligned by the one or more trenches.