Abstract: An electron microscope includes an acquisition section that acquires an electron microscope image of a specimen that includes a plurality of identical patterns, and a spectrum at each pixel of the electron microscope image, and an elemental map generation section that adds up the spectrum at each pixel of each of a plurality of areas that are included in the electron microscope image and have an identical size to generate an elemental mapping image of the specimen.

Abstract: Provided are methods to improve tomography by creating fiducial holes using charged particle beams, and using the fiducial holes to improve the sample positioning, acquisition, alignment, reconstruction, and visualization of tomography data sets. Some versions create fiducial holes with an ion beam during the process of milling the sample. Other versions create in situ fiducial holes within the TEM using the electron beam prior to acquiring a tomography data series. In some versions multiple sets of fiducial holes are made, positioned strategically around a region of interest. The fiducial holes may be employed to properly position the features of interest during the acquisition, and later to help better align the tilt-series, and improve the accuracy and resolution of the final reconstruction. The operator or software may identify the holes to be tracked with tomography feature tracking techniques.

Abstract: To provide a mass spectrometer capable of performing high-sensitivity measurement using water molecules. The mass spectrometer has a chamber in which a sample is disposed, an irradiation unit for emitting particles to the sample, and an extraction electrode which leads secondary ions emitted from the sample to a mass spectrometry unit, in which the irradiation unit switches a first mode of emitting primary ions for causing the secondary ions to be emitted from the sample and a second mode of emitting particles containing water molecules to be made to adhere to the sample and emits the particles to the sample.

Abstract: A charged particle beam drawing apparatus of an embodiment includes: a graphic information file for storing graphic information for each of elements (for example, patterns) at a level underlying an element (for example, a cell) at a particular level in hierarchically-structured drawing data which has elements at each level; and an attribute information file for storing attribute information to be given to each of the elements at the underlying level in association with information (for example, an index number) on the element at the particular level.

Abstract: Apparatus and method for aligning a rotatable substrate. In some embodiments, a circumferentially extending timing pattern is formed on a substrate. The timing pattern nominally extends about a center point of the substrate at a selected radius. The substrate is mounted to a support mechanism which rotates the substrate about a central axis. Due to mechanical tolerances, the central axis will be offset from the center point of the substrate as a result of an alignment error during the mounting of the substrate. The offset between the support mechanism central axis and the center point of the substrate is determined using a detector that detects two opposing cross-over transitions of the timing pattern during each revolution of the substrate. A feature may be written to the substrate by positioning a write element with respect to the substrate responsive to the detected offset.

Abstract: This invention relates in part to a method for cleaning an ion source component of an ion implanter used in semiconductor and microelectronic manufacturing. The ion source component includes an ionization chamber and one or more components contained within the ionization chamber. The interior of the ionization chamber and/or the one or more components contained within the ionization chamber have at least some deposits thereon of elements contained within a dopant gas, e.g., carborane (C2B10H12). The method involves introducing a cleaning gas into the ionization chamber, and reacting the cleaning gas with the deposits under conditions sufficient to remove at least a portion of the deposits from the interior of the ionization chamber and/or from the one or more components contained within the ionization chamber.

Abstract: There is provided an inductively coupled plasma etching apparatus capable of suppressing a wavelength effect within a RF antenna and performing a plasma process uniformly in both a circumferential and a radial direction. In the plasma etching apparatus, a RF antenna 54 is provided on a dielectric window 52 to generate inductively coupled plasma. The RF antenna 54 includes an inner coil 58, an intermediate coil 60 and an outer coil 62 in the radial direction. The inner coil 58 includes a single inner coil segment 59 or more than one inner coil segments 59 connected in series. The intermediate coil 60 includes two intermediate coil segments 61(1) and 61(2) separated in a circumferential direction and electrically connected with each other in parallel. The outer coil 62 includes three outer coil segments 63(1), 63(2) and 63(3) separated in a circumferential direction and electrically connected with each other in parallel.

Abstract: Systems and methods for tuning a parameter associated with plasma impedance are described. One of the methods includes receiving information to determine a variable. The information is measured at a transmission line and is measured when the parameter has a first value. The transmission line is used to provide power to a plasma chamber. The method further includes determining whether the variable is at a local minima and providing the first value to tune the impedance matching circuit upon determining that the variable is at the local minima. The method includes changing the first value to a second value of the parameter upon determining that the variable is not at the local minima and determining whether the variable is at a local minima when the parameter has the second value.

Abstract: To provide a plasma processing device, a plasma processing method and a method of manufacturing electronic devices capable of performing high-speed processing as well as using the plasma stably. In an inductively-coupled plasma torch unit, a coil, a first ceramic block and a second ceramic block are arranged in parallel, and a long chamber has an annular shape. Plasma generated in the chamber is ejected from an opening in the chamber toward a substrate. The substrate is processed by moving the long chamber and the substrate mounting table relatively in a direction perpendicular to a longitudinal direction of the opening. A discharge suppression gas is introduced into a space between the inductively-coupled plasma torch unit and the substrate inside the chamber through a discharge suppression gas supply hole, thereby generating long plasma stably.

Abstract: A plasma processing apparatus includes a processing chamber, in which a wafer W is plasma-processed, and a CPU controlling an operation of each component. A processing gas is introduced into the processing chamber under a first condition defined by a flow rate and a molecular weight of the processing gas, specifically based on a magnitude of a product A1 (=Q1×m1) of the flow rate Q1 and the molecular weight m1 of the processing gas, and a surface of the wafer W is physically or chemically etched. And then, a pre-purge gas which may be identical to or different from the processing gas is introduced into the processing chamber through a shower head under a second condition derived from the first condition.

Abstract: Methods and apparatus for in-situ cleaning of substrate processing chambers are provided herein. A substrate processing chamber may include a chamber body enclosing an inner volume; a chamber lid removably coupled to the chamber body and including a first flow channel fluidly coupled to the inner volume to selectively open or seal the inner volume to or from a first outlet; a chamber floor including a second flow channel fluidly coupled to the inner volume to selectively open or seal the inner volume to or from a first inlet; and a pump ring disposed in and in fluid communication with the inner volume, the pump ring comprising an upper chamber fluidly coupled to a lower chamber, and a second outlet fluidly coupled to the lower chamber to selectively open or seal the inner volume to or from the second outlet.

Abstract: A system and method monitoring a plasma with an optical sensor to determine the operations of a pulsed RF signal for plasma processing including a plasma chamber with an optical sensor directed toward a plasma region. An RF generator coupled to the plasma chamber through a match circuit. An RF timing system coupled to the RF generator. A system controller is coupled to the plasma chamber, the RF generator, the optical sensor, the RF timing system and the match circuit. The system controller includes a central processing unit, a memory system, a set of RF generator settings and an optical pulsed plasma analyzer coupled to the optical sensor and being capable to determine a timing of a change in state of an optical emission received in the optical sensor and/or a set of amplitude statistics corresponding to an amplitude of the optical emission received in the optical sensor.

Abstract: A sputtering apparatus includes a deposition preventing plate arranged between a substrate stage and a plurality of cathode electrodes, and a shutter plate arranged between the deposition preventing plate and the substrate stage. The deposition preventing plate has holes at positions respectively facing a plurality of targets held by the plurality of cathode electrodes. Concentric concavo-convex shapes centered on the rotation axis of the shutter plate are formed on surfaces, that face each other, of the deposition preventing plate and the shutter plate.

Abstract: This invention relates to systems and methods for measuring quantitatively multiple species or heavy metals, including mercury, and other toxic pollutants. More specifically, the systems and methods of the invention allows for determination of the analytes even at very low concentration, through concentration on a collection interface, desorption and analysis by mass spectrometry. The invention also provides for a portable device or kit for modifying an existing mass spectrometer.

Abstract: The invention concerns a vacuum system, comprising a first vacuum chamber and a second vacuum chamber, the first vacuum chamber being evacuated by a first vacuum pump, in particular a turbomolecular pump, the first and the second vacuum chamber being connected by a passage, wherein the passage is surrounded by a sealing arrangement comprising an inner seal and an outer seal with a plenum positioned between the inner seal and the outer seal, the plenum being evacuated by a support vacuum pump, and wherein at least one sealing face of the inner seal consists of the wall material of the first or the second vacuum chamber, in particular the inner seal being formed by direct contact between the wall material of the first vacuum chamber and the wall material of the second vacuum chamber. Additionally, the invention concerns a mass spectrometry system.

Abstract: A time-of-flight mass spectrometer (TOF-MS) utilizes an ion dispersion device and a position-sensitive ion detector or an energy-sensitive ion detector to enable measurement of time of flight and kinetic energy of ions arriving at the detector. The measurements may be utilized to improve accuracy in calculating ion masses.

Abstract: An extendable multi-tool comprising an extendable pole and a head unit selectively detachably coupled together. The head unit comprises a grasping mechanism configured to engage a light bulb, a control switch and a rotation mechanism. The control switch configured to cause the grasping mechanism to become secured to a light bulb, and to cause the rotation mechanism to automatically detect when a light bulb is secured to the grasping mechanism and then rotate the grasping unit and the secured light bulb in a first direction based on the position of the control switch. The tool further comprises an arm unit for positioning the grasping mechanism in a desired configuration to engage the light bulb, wherein the arm member is coupled to the grasping mechanism.

Abstract: Disclosed is a substrate processing apparatus (a substrate processing method, and a computer readable storage medium having a substrate processing program stored therein) of cleaning an etched substrate with a polymer removing liquid, in which any of isopropyl alcohol vapor, water vapor, deionized water and isopropyl alcohol, ammonia water, and ammonia water and isopropyl alcohol is supplied to the substrate before the substrate is cleaned with the polymer removing liquid.

Abstract: Described herein are precursors and methods for forming silicon-containing films. In one aspect, there is provided a precursor of Formula I: wherein R1 is selected from linear or branched C3 to C10 alkyl group, linear or branched C3 to C10 alkenyl group, linear or branched C3 to C10 alkynyl group, C1 to C6 dialkylamino group, electron withdrawing group, and C6 to C10 aryl group; R2 is selected from hydrogen, linear or branched C1 to C10 alkyl group, linear or branched C3 to C6 alkenyl group, linear or branched C3 to C6 alkynyl group, C1 to C6 dialkylamino group, C6 to C10 aryl group, linear or branched C1 to C6 fluorinated alkyl group, electron withdrawing group, and C4 to C10 aryl group; optionally wherein R1 and R2 are linked together to form ring selected from substituted or unsubstituted aromatic ring or substituted or unsubstituted aliphatic ring; and n=1 or 2.

Abstract: One or more masks may be used to control the application of protective (e.g., moisture-resistant, etc.) coatings to one or more portions of various components of an electronic device during assembly of the electronic device. A method for applying a protective coating to an electronic device includes assembling two or more components of the electronic device with one another. A mask may then be applied to the resulting electronic assembly. The mask may shield selected portions of the electronic assembly, while other portions of the electronic assembly, i.e., those to which a protective coating is to be applied, may remain exposed through the mask. With the mask in place, application of a protective coating to portions of the electronic assembly exposed through the mask may commence. After application of the protective coating, the mask may be removed from the electronic assembly. Embodiments of masked electronic assemblies are also disclosed.

Abstract: According to various embodiments, a method for processing a carrier may include: co-depositing at least one metal from a first source and carbon from a second source over a surface of the carrier to form a first layer; forming a second layer over the first layer, the second layer including a diffusion barrier material, wherein the solubility of carbon in the diffusion barrier material is less than in the at least one metal; and forming a graphene layer at the surface of the carrier from the first layer by a temperature treatment.

Abstract: The invention provides a composite substrate, a semiconductor device including such composite substrate, and a method of making the same. In particular, the composite substrate of the invention includes a nitride-based single crystal layer transformed from a nitride-based poly-crystal layer, which has a specific thickness of approximately between 2 nm and 100 nm.

Abstract: An object is to provide a semiconductor device with stable electric characteristics in which an oxide semiconductor is used. The impurity concentration in the oxide semiconductor layer is reduced in the following manner: a silicon oxide layer including many defects typified by dangling bonds is formed in contact with the oxide semiconductor layer, and an impurity such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H2O) included in the oxide semiconductor layer is diffused into the silicon oxide layer. Further, a mixed region is provided between the oxide semiconductor layer and the silicon oxide layer. The mixed region includes oxygen, silicon, and at least one kind of metal element that is included in the oxide semiconductor.

Abstract: Methods of fabricating micro- and nanostructures comprise top-down etching of lithographically patterned GaN layer to form an array of micro- or nanopillar structures, followed by selective growth of GaN shells over the pillar structures via selective epitaxy. Also provided are methods of forming micro- and nanodisk structures and microstructures formed from thereby.

Abstract: The present disclosure provides systems, processes, articles of manufacture, and compositions that relate to core/shell semiconductor nanowires. Specifically, the disclosure provides a novel semiconductor material, CdSe/ZnS core/shell nanowires, as well as a method of preparation thereof. The disclosure also provides a new continuous flow method of preparing core/shell nanowires, including CdSe/CdS core/shell nanowire and CdSe/ZnS core/shell nanowires.

Abstract: In a method of forming holes, a plurality of guide patterns physically spaced apart from each other is formed on an object layer. The guide pattern has a ring shape and includes a first opening therein. A self-aligned layer is formed on the object layer and the guide patterns to fill the first opening. Preliminary holes are formed by removing portions of the self-aligned layer which are self-assembled in the first opening and between the guide patterns neighboring each other. The object layer is partially etched through the preliminary holes.

Abstract: The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns.

Abstract: The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.

Abstract: The present invention provides a composition for forming a coating type BPSG film, which comprises: one or more structures comprising a silicic acid represented by the following general formula (1) as a skeletal structure, one or more structures comprising a phosphoric acid represented by the following general formula (2) as a skeletal structure and one or more structures comprising a boric acid represented by the following general formula (3) as a skeletal structure. There can be provided a composition for forming a coating type BPSG film which is excellent in adhesiveness in fine pattern, can be easily wet etched by a peeling solution which does not cause any damage to the semiconductor apparatus substrate, the coating type organic film or the CVD film mainly comprising carbon which are necessary in the patterning process, and can suppress generation of particles by forming it in the coating process.

Abstract: In a method of manufacturing a semiconductor device, a blend solution that includes a block copolymer and an adsorbent is prepared. The block copolymer is synthesized by a copolymerization between a first polymer unit and a second polymer unit having a hydrophilicity greater than that of the first polymer unit. The adsorbent on which the block copolymer is adsorbed is extracted. The block copolymer is separated from the adsorbent. The block copolymer is collected. The block copolymer may be used to form a mask on an object layer on a substrate and the mask used to etch the object layer.

Abstract: A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between the first mandrel and the second mandrel, and etching the third mandrel to cut the third mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the second, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material.

Abstract: Methods of forming a semiconductor device are provided. An active region is formed on a substrate. A temporary gate crossing the active region and a capping pattern covering the temporary gate are formed. Spacers are formed on sidewalls of the temporary gate. A growth-blocking layer is locally formed in an upper edge of the temporary gate. A source/drain region is formed on the active region adjacent to the temporary gate. The capping pattern, the first growth-blocking layer, and the temporary gate are removed to expose the active region. A gate electrode is formed on the exposed active region.

Abstract: According to an embodiment, a semiconductor switch includes a first insulating film on a semiconductor substrate, a first semiconductor layer on the first insulating film, a semiconductor switch circuit on the first semiconductor layer, and a wiring on the first insulating film. The first insulating film being between the wiring and the substrate. The wiring connects the semiconductor switch circuit and a terminal. A polycrystalline semiconductor layer is between the wiring and the first insulating film.

Abstract: A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body.

Abstract: A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.

Abstract: Methods for processing a substrate are described herein. A method for removing a layer from a substrate, can include positioning a substrate within a processing chamber, wherein the substrate can include an upper surface, and one or more metal features with a separation energy formed on the upper surface; forming a layer over the one or more metal features and the exposed portion of the upper surface; focusing a source of transmissive radiant energy at the layer; pulsing transmissive radiant energy at the upper surface of the substrate creating a separated portion and an attached portion of the layer; and removing the separated portion of the layer.

Abstract: A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction.

Abstract: A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.

Abstract: A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric.

Abstract: A method includes providing a substrate having a first conductive feature in a first dielectric material layer; forming a first etch stop layer on the first dielectric material layer, wherein the first etch stop layer is formed of a high-k dielectric material; forming a second etch stop layer on the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; forming a pattered mask layer on the second dielectric material layer; forming a first trench in the second dielectric material layer and the second etch stop layer; removing a portion of the first etch stop layer through the first trench to thereby form a second trench, wherein removing the portion of the first etch stop layer includes applying a solution to the portion of the first etch stop layer; and forming a second conductive feature in the second trench.

Abstract: Embodiments of methods for forming features in a silicon containing layer of a substrate disposed on a substrate support are provided herein. In some embodiments, a method for forming features in a silicon containing layer of a substrate disposed on a substrate support in a processing volume of a process chamber includes: exposing the substrate to a first plasma formed from a first process gas while providing a bias power to the substrate support, wherein the first process gas comprises one or more of a chlorine-containing gas or a bromine containing gas; and exposing the substrate to a second plasma formed from a second process gas while no bias power is provided to the substrate support, wherein the second process gas comprises one or more of an oxygen-containing gas or nitrogen gas, and wherein a source power provided to form the first plasma and the second plasma is continuously provided.

Abstract: There is provided a composition for forming an EUV resist underlayer film which shows a good resit form. A resist underlayer film-forming composition for EUV lithography, including: polysiloxane (A) containing a hydrolyzed condensate of hydrolyzable silane (a); and hydrolyzable silane compound (b) having a sulfonamide structure, a carboxylic acid amide structure, a urea structure, or an isocyanuric acid structure. A resist underlayer film-forming composition for EUV lithography, including: polysiloxane (B) containing a hydrolyzed condensate of hydrolyzable silane (a) and hydrolyzable silane compound (b) having a sulfonamide structure, a carboxylic acid amide structure, a urea structure, or an isocyanuric acid structure. The polysiloxane (A) is preferably a co-hydrolyzed condensate of a tetraalkoxysilane, an alkyltrialkoxysilane and an aryltrialkoxysilane.

Abstract: According to one embodiment, a mask material is formed on a processing layer, a mask pattern with a top surface and a bottom surface is formed on the mask material, a protective film is formed on the top surface of the mask pattern, and after the formation of the protective film, the bottom surface of the mask pattern is etched in a depth direction.

Abstract: Methods of forming a semiconductor device are presented. The method includes providing a wafer with top and bottom wafer surfaces. The wafer includes edge and non-edge regions. A dielectric layer having a desired concave top surface is provided on the top wafer surface. The method includes planarizing the dielectric layer to form a planar top surface of the dielectric layer. The desired concave top surface of the dielectric layer thicknesses compensates for different planarizing rates at the edge and non-edge regions of the wafer.

Abstract: Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. The methods may include two or more nitride removal steps during formation of gate layers in vertical memory cells. The two or more nitride removal steps may allow for wider gate layers increasing the gate fill-in, reducing the occurrence of voids, and thereby improving the word line resistance.

Abstract: A method of continuous fabrication of a layered structure on a substrate having a patterned recess, includes: (i) forming a dielectric layer on a substrate having a patterned recess in a reaction chamber by PEALD using a first RF power; (ii) continuously after completion of step (i) without breaking vacuum, etching the dielectric layer on the substrate in the reaction chamber by PEALE using a second RF power, wherein a pressure of the reaction chamber is controlled at 30 Pa to 1,333 Pa throughout steps (i) and (ii); a noble gas is supplied to the reaction chamber continuously throughout steps (i) and (ii); and the second RF power is higher than the first RF power.

Abstract: A method for fabricating a semiconductor device including: forming a silicon layer on an upper face of a nitride semiconductor layer including a channel layer of a FET; thermally treating the nitride semiconductor layer in the process of forming the silicon layer or after the process of forming the silicon layer; and forming an insulating layer on an upper face of the silicon layer after the process of forming the silicon layer.

Abstract: Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.

Abstract: A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board.

Abstract: A fabrication method of a semiconductor package is disclosed, which includes the steps of: disposing a plurality of first semiconductor elements on an interposer; forming a first encapsulant on the interposer for encapsulating the first semiconductor elements; disposing a plurality of second semiconductor elements on the first semiconductor elements; forming a second encapsulant on the first semiconductor elements and the first encapsulant for encapsulating the second semiconductor elements; and thinning the interposer, thereby reducing the overall stack thickness and preventing warpage of the interposer.